[llvm] Validate immediates for SCVTF, UCVTF and EXT (PR #214233)
Hamza Khan via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 06:37:54 PDT 2026
https://github.com/HamzaKodez created https://github.com/llvm/llvm-project/pull/214233
This fixes operand validation for the AArch64 SCVTF, UCVTF, and EXT instructions.
Symbolic operands such as f0, NaN, and Inf could previously reach encoding paths that expect integer immediates. This caused assertion failures in assertions-enabled builds and could produce incorrect encodings when assertions were disabled.
The patch assigns the appropriate parser match classes and immediate ranges so invalid operands are rejected during parsing.
Regression tests cover the affected fixed-point conversion scale operands and EXT byte-index operands.
Testing:
* llvm/test/MC/AArch64/arm64-diags.s
* llvm/test/MC/AArch64/neon-diagnostics.s
* Manual validation with assertions enabled and disabled
* Valid immediate boundary values continue to assemble correctly
Fixes #185358
Fixes #185361
>From e73402bd75a0a1ad0892692d2ab7e34a47881718 Mon Sep 17 00:00:00 2001
From: Hamza Khan <hamza.khan at arm.com>
Date: Thu, 23 Jul 2026 13:51:00 +0100
Subject: [PATCH] Validate immediates for SCVTF, UCVTF and EXT
Reject symbolic operands where fixed-point scale and EXT byte-index
integer immediates are required.
This prevents assertion failures in assertions-enabled builds and
incorrect encodings in assertions-disabled builds.
Add MC regression tests for the affected instructions.
Assisted-by ChatGPT. Human-reviewed, debugged, tested, and validated by the author.
---
llvm/lib/Target/AArch64/AArch64InstrFormats.td | 10 ++++++----
llvm/test/MC/AArch64/arm64-diags.s | 18 ++++++++++++++++++
llvm/test/MC/AArch64/neon-diagnostics.s | 9 +++++++++
3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 09ce713ea862c..e80ea0c1d4bbf 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -795,6 +795,7 @@ class fixedpoint_recip_i32<ValueType FloatVT>
ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<32>", [fpimm, ld]> {
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm32";
+ let ParserMatchClass = Imm1_32Operand;
}
class fixedpoint_recip_i64<ValueType FloatVT>
@@ -802,6 +803,7 @@ class fixedpoint_recip_i64<ValueType FloatVT>
ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<64>", [fpimm, ld]> {
let EncoderMethod = "getFixedPointScaleOpValue";
let DecoderMethod = "DecodeFixedPointScaleImm64";
+ let ParserMatchClass = Imm1_64Operand;
}
def fixedpoint_recip_f16_i32 : fixedpoint_recip_i32<f16>;
@@ -7499,8 +7501,8 @@ multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
//----------------------------------------------------------------------------
class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
- string asm, string kind>
- : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
+ Operand immtype, string asm, string kind>
+ : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, immtype:$imm), asm,
"{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
"|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
[(set (vty regtype:$Rd),
@@ -7523,10 +7525,10 @@ class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
multiclass SIMDBitwiseExtract<string asm> {
- def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
+ def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, imm32_0_7, asm, ".8b"> {
let imm{3} = 0;
}
- def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
+ def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, imm32_0_15, asm, ".16b">;
}
//----------------------------------------------------------------------------
diff --git a/llvm/test/MC/AArch64/arm64-diags.s b/llvm/test/MC/AArch64/arm64-diags.s
index bcd42d98cd5f3..3224051b8885a 100644
--- a/llvm/test/MC/AArch64/arm64-diags.s
+++ b/llvm/test/MC/AArch64/arm64-diags.s
@@ -144,6 +144,24 @@ ldr q1, [x3, w3, sxtw #1]
; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67
; CHECK-ERRORS: ^
+; Fixed-point conversion scale operands must be integer immediates.
+ scvtf s0, w0, f0
+ scvtf d0, w0, f0
+ ucvtf s0, w0, f0
+ ucvtf d0, x0, f0
+
+; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
+; CHECK-ERRORS: scvtf s0, w0, f0
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
+; CHECK-ERRORS: scvtf d0, w0, f0
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
+; CHECK-ERRORS: ucvtf s0, w0, f0
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: immediate must be an integer in range [1, 64].
+; CHECK-ERRORS: ucvtf d0, x0, f0
+; CHECK-ERRORS: ^
st1.s4 {v14, v15}, [x2], #32
; CHECK-ERRORS: error: invalid type suffix for instruction
diff --git a/llvm/test/MC/AArch64/neon-diagnostics.s b/llvm/test/MC/AArch64/neon-diagnostics.s
index 2610f4acf383b..989a8bbab4615 100644
--- a/llvm/test/MC/AArch64/neon-diagnostics.s
+++ b/llvm/test/MC/AArch64/neon-diagnostics.s
@@ -6418,6 +6418,15 @@
// CHECK-ERROR: ext v0.2d, v1.2d, v2.2d, #0x0
// CHECK-ERROR: ^
+ // Symbolic operands are not valid byte-index immediates.
+ ext v0.8b, v1.8b, v2.8b, f0
+// CHECK-ERROR: [[@LINE-1]]:34: error: immediate must be an integer in range [0, 7].
+ ext v0.16b, v1.16b, v2.16b, f0
+// CHECK-ERROR: [[@LINE-1]]:37: error: immediate must be an integer in range [0, 15].
+ ext v0.8b, v1.8b, v2.8b, NaN
+// CHECK-ERROR: [[@LINE-1]]:34: error: immediate must be an integer in range [0, 7].
+ ext v0.8b, v1.8b, v2.8b, Inf
+// CHECK-ERROR: [[@LINE-1]]:34: error: immediate must be an integer in range [0, 7].
//----------------------------------------------------------------------
// Permutation with 3 vectors
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