[llvm] [AArch64][GlobalISel] Pack i1 vector to scalar bitcasts in vector registers (PR #213946)

[Joel Walker via llvm-commits]

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Joel-Wwalker wrote:

Makes sense, moved it to #210514. Its only real producer is the load legalization there: bitcastIf turns the vector load into a scalar load plus a cast back to the vector type, and this fold is what collapses that round trip. Without those rules the only way to hit it is IR that casts to an i1 vector and straight back, which nothing generates.

The load fold below does fire on its own (load <8 x i1> then cast to i8 compiles to a single ldrb with just this PR, the cast legalizes first and the dead vector load gets cleaned up), so I've kept that one here.

https://github.com/llvm/llvm-project/pull/213946