[llvm] [RISCV] Remove isBarrier from PseudoCALLReg definition (PR #214155)
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Wed Aug 5 05:39:25 PDT 2026
=?utf-8?b?6JGj5rSl5rKF?= <t_tttie at 163.com>,T-Tie <t_tttie at 163.com>,T-Tie
<t_tttie at 163.com>
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In-Reply-To: <llvm.org/llvm/llvm-project/pull/214155 at github.com>
https://github.com/T-Tie updated https://github.com/llvm/llvm-project/pull/214155
>From db81040156c20a98ad8143bc092e164a647a5b57 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E8=91=A3=E6=B4=A5=E6=B2=85?= <t_tttie at 163.com>
Date: Wed, 5 Aug 2026 16:23:21 +0800
Subject: [PATCH 1/4] Remove isBarrier from PseudoCALLReg definition
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 09fa9fc0ead1b..e49a7abcd40f2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1802,7 +1802,7 @@ def : Pat<(brind (add GPRJALRNonX7:$rs1, simm12_lo:$imm12)),
// destination.
// Define AsmString to print "call" when compile with -S flag.
// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction.
-let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0,
+let isCall = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0,
mayStore = 0, mayLoad = 0 in
def PseudoCALLReg : Pseudo<(outs GPR:$rd), (ins call_symbol:$func), [],
"call", "$rd, $func">,
>From 51912e6a7cfd15f0647aca6311ae6666194f31b5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E8=91=A3=E6=B4=A5=E6=B2=85?= <t_tttie at 163.com>
Date: Wed, 5 Aug 2026 17:20:33 +0800
Subject: [PATCH 2/4] Create machine-outliner call fallthrough tests
Add MIR test cases for outlined calls with fallthrough.
---
.../machine-outliner-call-fallthrough.mir | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/machine-outliner-call-fallthrough.mir
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-call-fallthrough.mir b/llvm/test/CodeGen/RISCV/machine-outliner-call-fallthrough.mir
new file mode 100644
index 0000000000000..f6a04da9312ca
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-call-fallthrough.mir
@@ -0,0 +1,72 @@
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV32 %s
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: | FileCheck -check-prefix=RV64 %s
+
+# Check a normal outlined call at the end of a block that falls through to its
+# successor. PseudoCALLReg is a returning call and must not be a barrier.
+
+---
+name: outline_fallthrough_0
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.1
+ liveins: $x10, $x11
+
+ ; RV32-LABEL: name: outline_fallthrough_0
+ ; RV32: bb.0:
+ ; RV32: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0
+ ; RV32: bb.1:
+ ; RV32: PseudoRET implicit $x10
+ ; RV64-LABEL: name: outline_fallthrough_0
+ ; RV64: bb.0:
+ ; RV64: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0
+ ; RV64: bb.1:
+ ; RV64: PseudoRET implicit $x10
+ $x11 = ORI $x11, 1023
+ $x12 = ADDI $x10, 17
+ $x11 = AND $x12, $x11
+ $x10 = SUB $x10, $x11
+
+ bb.1:
+ liveins: $x10
+ PseudoRET implicit $x10
+
+...
+---
+name: outline_fallthrough_1
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.1
+ liveins: $x10, $x11
+
+ $x11 = ORI $x11, 1023
+ $x12 = ADDI $x10, 17
+ $x11 = AND $x12, $x11
+ $x10 = SUB $x10, $x11
+
+ bb.1:
+ liveins: $x10
+ PseudoRET implicit $x10
+
+...
+---
+name: outline_fallthrough_2
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.1
+ liveins: $x10, $x11
+
+ $x11 = ORI $x11, 1023
+ $x12 = ADDI $x10, 17
+ $x11 = AND $x12, $x11
+ $x10 = SUB $x10, $x11
+
+ bb.1:
+ liveins: $x10
+ PseudoRET implicit $x10
+
+...
>From 872c1908faa3434629f0a1334109cfada1d01cce Mon Sep 17 00:00:00 2001
From: T-Tie <t_tttie at 163.com>
Date: Wed, 5 Aug 2026 20:36:49 +0800
Subject: [PATCH 3/4] Remove isBarrier attribute from PseudoTLSDESCCall
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e49a7abcd40f2..7f661ac7370f7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1984,7 +1984,7 @@ def tlsdesc_call_symbol : Operand<XLenVT> {
// fourth operand to emit a relocation on a symbol relating to this instruction.
// The relocation does not affect any bits of the instruction itself but is used
// as a hint to the linker.
-let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0,
+let isCall = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0,
mayStore = 0, mayLoad = 0 in
def PseudoTLSDESCCall : Pseudo<(outs GPR:$rd),
(ins GPR:$rs1, simm12_lo:$imm12, tlsdesc_call_symbol:$src), [],
>From d96c7c0da35dc629e84a07093fb2a55d62b5aae2 Mon Sep 17 00:00:00 2001
From: T-Tie <t_tttie at 163.com>
Date: Wed, 5 Aug 2026 20:39:14 +0800
Subject: [PATCH 4/4] Create tlsdesc-call-fallthrough.mir test case
Add MIR test for PseudoTLSDESCCall fallthrough behavior in RISCV
---
.../RISCV/tlsdesc-call-fallthrough.mir | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/tlsdesc-call-fallthrough.mir
diff --git a/llvm/test/CodeGen/RISCV/tlsdesc-call-fallthrough.mir b/llvm/test/CodeGen/RISCV/tlsdesc-call-fallthrough.mir
new file mode 100644
index 0000000000000..cdddb99d70c1a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/tlsdesc-call-fallthrough.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machineverifier \
+# RUN: -verify-machineinstrs %s -o /dev/null
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machineverifier \
+# RUN: -verify-machineinstrs %s -o /dev/null
+
+# PseudoTLSDESCCall is a returning call. A block ending in this instruction
+# may fall through to its layout successor.
+
+---
+name: tlsdesc_call_fallthrough
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.1
+ liveins: $x10, $x11
+
+ dead $x5 = PseudoTLSDESCCall killed $x11, 0, target-flags(riscv-tlsdesc-call) <mcsymbol .Ltlsdesc_hi0>, implicit-def $x10, implicit $x10
+
+ bb.1:
+ liveins: $x10
+ $x10 = ADD $x10, $x4
+ PseudoRET implicit $x10
+...
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