[llvm] [AMDGPU] Pre-commit test for #214166 (PR #214196)

[Pierre van Houtryve via llvm-commits]

https://github.com/Pierre-vh created https://github.com/llvm/llvm-project/pull/214196

None

>From 796f71a1350ea1f6f9d217b8782c78679e51135a Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Wed, 5 Aug 2026 13:04:46 +0200
Subject: [PATCH] [AMDGPU] Pre-commit test for #214166

---
 .../AMDGPU/ds-atomic-barrier-convergent.ll    | 120 ++++++++++++++++++
 1 file changed, 120 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll

diff --git a/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll b/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll
new file mode 100644
index 0000000000000..417095ca69fd5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ds-atomic-barrier-convergent.ll
@@ -0,0 +1,120 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12.50 -O2 -tail-dup-size=1000 -tail-dup-placement-threshold=1000 -enable-tail-merge=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+
+; llvm.amdgcn.ds.atomic.*.barrier intrinsics do more than a simple r-m-w atomic.
+; They may issue a wakeup to other waves, and thus must be convergent.
+;
+; This tests that the optimizer cannot duplicate calls to these intrinsics.
+
+; test using taildup
+define void @taildup_ds_atomic_barrier_arrive(ptr addrspace(1) %a, ptr addrspace(3) %bar, i64 %data, i1 %cond) {
+; GCN-LABEL: taildup_ds_atomic_barrier_arrive:
+; GCN:       ; %bb.0: ; %entry
+; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GCN-NEXT:    s_wait_kmcnt 0x0
+; GCN-NEXT:    v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v6, v3
+; GCN-NEXT:    v_and_b32_e32 v3, 1, v5
+; GCN-NEXT:    s_mov_b32 s0, exec_lo
+; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT:    v_cmpx_ne_u32_e32 1, v3
+; GCN-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GCN-NEXT:    s_cbranch_execnz .LBB0_3
+; GCN-NEXT:  ; %bb.1: ; %Flow
+; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GCN-NEXT:    s_cbranch_execnz .LBB0_4
+; GCN-NEXT:  .LBB0_2: ; %call
+; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GCN-NEXT:    ds_atomic_barrier_arrive_rtn_b64 v[2:3], v2, v[6:7]
+; GCN-NEXT:    s_wait_dscnt 0x0
+; GCN-NEXT:    global_store_b64 v[0:1], v[2:3], off
+; GCN-NEXT:    s_set_pc_i64 s[30:31]
+; GCN-NEXT:  .LBB0_3: ; %bb2
+; GCN-NEXT:    v_mov_b32_e32 v3, 1
+; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:    s_wait_xcnt 0x0
+; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GCN-NEXT:    s_cbranch_execz .LBB0_2
+; GCN-NEXT:  .LBB0_4: ; %bb1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:    s_wait_xcnt 0x0
+; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GCN-NEXT:    ds_atomic_barrier_arrive_rtn_b64 v[2:3], v2, v[6:7]
+; GCN-NEXT:    s_wait_dscnt 0x0
+; GCN-NEXT:    global_store_b64 v[0:1], v[2:3], off
+; GCN-NEXT:    s_set_pc_i64 s[30:31]
+entry:
+  br i1 %cond, label %bb1, label %bb2
+
+bb1:
+  store i32 0, ptr addrspace(1) %a
+  br label %call
+
+bb2:
+  store i32 1, ptr addrspace(1) %a
+  br label %call
+
+call:
+  %r = call i64 @llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64(ptr addrspace(3) %bar, i64 %data)
+  store i64 %r, ptr addrspace(1) %a
+  br label %ret
+
+ret:
+  ret void
+}
+
+; async test using taildup
+define void @taildup_ds_atomic_async_barrier_arrive(ptr addrspace(1) %a, ptr addrspace(3) %bar, i64 %data, i1 %cond) {
+; GCN-LABEL: taildup_ds_atomic_async_barrier_arrive:
+; GCN:       ; %bb.0: ; %entry
+; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GCN-NEXT:    s_wait_kmcnt 0x0
+; GCN-NEXT:    v_and_b32_e32 v3, 1, v5
+; GCN-NEXT:    s_mov_b32 s0, exec_lo
+; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT:    v_cmpx_ne_u32_e32 1, v3
+; GCN-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GCN-NEXT:    s_cbranch_execnz .LBB1_3
+; GCN-NEXT:  ; %bb.1: ; %Flow
+; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GCN-NEXT:    s_cbranch_execnz .LBB1_4
+; GCN-NEXT:  .LBB1_2: ; %call
+; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
+; GCN-NEXT:    ds_atomic_async_barrier_arrive_b64 v2
+; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
+; GCN-NEXT:    s_set_pc_i64 s[30:31]
+; GCN-NEXT:  .LBB1_3: ; %bb2
+; GCN-NEXT:    v_mov_b32_e32 v3, 1
+; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GCN-NEXT:    s_wait_xcnt 0x0
+; GCN-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GCN-NEXT:    s_cbranch_execz .LBB1_2
+; GCN-NEXT:  .LBB1_4: ; %bb1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    global_store_b32 v[0:1], v3, off
+; GCN-NEXT:    s_wait_xcnt 0x0
+; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
+; GCN-NEXT:    ds_atomic_async_barrier_arrive_b64 v2
+; GCN-NEXT:    s_wait_alu depctr_vm_vsrc(0)
+; GCN-NEXT:    s_set_pc_i64 s[30:31]
+entry:
+  br i1 %cond, label %bb1, label %bb2
+
+bb1:
+  store i32 0, ptr addrspace(1) %a
+  br label %call
+
+bb2:
+  store i32 1, ptr addrspace(1) %a
+  br label %call
+
+call:
+  call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
+  br label %ret
+
+ret:
+  ret void
+}