[llvm] [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (PR #199544)

[Simon Pilgrim via llvm-commits]

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@@ -244,26 +219,26 @@ define i32 @extract_last_active_v4i32_penryn(<4 x i32> %a, <4 x i1> %c) "target-
 define i8 @extract_last_active_split(<32 x i8> %data, <32 x i8> %mask, i8 %passthru) {
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RKSimon wrote:

#214180

https://github.com/llvm/llvm-project/pull/199544