[llvm] ea2fb2a - [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (#199544)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 02:13:54 PDT 2026
Author: Simon Pilgrim
Date: 2026-08-05T09:13:48Z
New Revision: ea2fb2a1919eb64a7eb4e863be6aef17b570fb2d
URL: https://github.com/llvm/llvm-project/commit/ea2fb2a1919eb64a7eb4e863be6aef17b570fb2d
DIFF: https://github.com/llvm/llvm-project/commit/ea2fb2a1919eb64a7eb4e863be6aef17b570fb2d.diff
LOG: [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (#199544)
The middle-end (SLP, VectorCombine and InstCombine) recognition and
handling of vector logic reduction patterns is sufficient now, so the
backend can work with ISD::VECREDUCE_AND/OR/XOR nodes directly.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/pr53419.ll
llvm/test/CodeGen/X86/vector-extract-last-active.ll
llvm/test/CodeGen/X86/vector-reduce-and.ll
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
llvm/test/CodeGen/X86/vector-reduce-or.ll
llvm/test/CodeGen/X86/vector-reduce-xor.ll
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 84a38c3f5167a..7cb59d7198817 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1176,15 +1176,15 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
- setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
- setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
- setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
}
// SSE2 can use basic vector unrolling.
// SSE41 can use PHMINPOS to perform v16i8/v8i16 minmax reductions.
// Fallback to ReplaceNodeResults for vXi64 reductions on 32-bit targets.
for (auto VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i64}) {
+ setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
@@ -2836,6 +2836,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
ISD::ANY_EXTEND_VECTOR_INREG,
ISD::SIGN_EXTEND_VECTOR_INREG,
ISD::ZERO_EXTEND_VECTOR_INREG,
+ ISD::VECREDUCE_AND,
+ ISD::VECREDUCE_OR,
+ ISD::VECREDUCE_XOR,
ISD::VECREDUCE_MUL,
ISD::SINT_TO_FP,
ISD::UINT_TO_FP,
@@ -23673,16 +23676,13 @@ static SDValue MatchVectorAllEqualTest(SDValue OrigLHS, SDValue OrigRHS,
// Match icmp(reduce_or(X),0) anyof reduction patterns.
// Match icmp(reduce_and(X),-1) allof reduction patterns.
- if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- ISD::NodeType BinOp;
- if (SDValue Match =
- DAG.matchBinOpReduction(Op.getNode(), BinOp, {LogicOp})) {
- EVT MatchVT = Match.getValueType();
- return LowerVectorAllEqual(DL, Match,
- CmpNull ? DAG.getConstant(0, DL, MatchVT)
- : DAG.getAllOnesConstant(DL, MatchVT),
- CC, Mask, Subtarget, DAG, X86CC);
- }
+ if (Op.getOpcode() == (CmpNull ? ISD::VECREDUCE_OR : ISD::VECREDUCE_AND)) {
+ SDValue Match = Op.getOperand(0);
+ EVT MatchVT = Match.getValueType();
+ return LowerVectorAllEqual(DL, Match,
+ CmpNull ? DAG.getConstant(0, DL, MatchVT)
+ : DAG.getAllOnesConstant(DL, MatchVT),
+ CC, Mask, Subtarget, DAG, X86CC);
}
if (Mask.isAllOnes()) {
@@ -35334,6 +35334,14 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
}
return;
}
+ case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
+ case ISD::VECREDUCE_XOR: {
+ assert(N->getValueType(0) == MVT::i64 && "Unexpected vector reduction");
+ if (SDValue Res = LowerVECREDUCE(SDValue(N, 0), Subtarget, DAG, true))
+ Results.push_back(Res);
+ return;
+ }
case ISD::VECREDUCE_MUL: {
assert(N->getValueType(0) == MVT::i64 && "Unexpected vector reduction");
if (SDValue Res = LowerVECREDUCE(SDValue(N, 0), Subtarget, DAG, false))
@@ -47163,33 +47171,33 @@ static SDValue createPSADBW(SelectionDAG &DAG, SDValue N0, SDValue N1,
}
// Attempt to replace an all_of/any_of/parity style horizontal reduction with a MOVMSK.
-static SDValue combinePredicateReduction(SDNode *Extract, SelectionDAG &DAG,
- const X86Subtarget &Subtarget) {
+static SDValue combineVECREDUCE_LOGIC(SDNode *Reduce, SelectionDAG &DAG,
+ const X86Subtarget &Subtarget) {
// Bail without SSE2.
if (!Subtarget.hasSSE2())
return SDValue();
- EVT ExtractVT = Extract->getValueType(0);
+ // Check for OR(any_of)/AND(all_of)/XOR(parity) horizontal reduction patterns.
+ if (Reduce->getOpcode() != ISD::VECREDUCE_AND &&
+ Reduce->getOpcode() != ISD::VECREDUCE_OR &&
+ Reduce->getOpcode() != ISD::VECREDUCE_XOR)
+ return SDValue();
+
+ ISD::NodeType BinOp = ISD::getVecReduceBaseOpcode(Reduce->getOpcode());
+ SDValue Match = Reduce->getOperand(0);
+ EVT ExtractVT = Reduce->getValueType(0);
unsigned BitWidth = ExtractVT.getSizeInBits();
if (ExtractVT != MVT::i64 && ExtractVT != MVT::i32 && ExtractVT != MVT::i16 &&
ExtractVT != MVT::i8 && ExtractVT != MVT::i1)
return SDValue();
- // Check for OR(any_of)/AND(all_of)/XOR(parity) horizontal reduction patterns.
- ISD::NodeType BinOp;
- SDValue Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::OR, ISD::AND});
- if (!Match && ExtractVT == MVT::i1)
- Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::XOR});
- if (!Match)
- return SDValue();
-
- // EXTRACT_VECTOR_ELT can require implicit extension of the vector element
+ // ISD::VECREDUCE_* can require implicit extension of the vector element
// which we can't support here for now.
if (Match.getScalarValueSizeInBits() != BitWidth)
return SDValue();
SDValue Movmsk;
- SDLoc DL(Extract);
+ SDLoc DL(Reduce);
EVT MatchVT = Match.getValueType();
unsigned NumElts = MatchVT.getVectorNumElements();
unsigned MaxElts = Subtarget.hasInt256() ? 32 : 16;
@@ -48080,10 +48088,6 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
if (SDValue VPDPBUSD = combineVPDPBUSDPattern(N, DAG, Subtarget))
return VPDPBUSD;
- // Attempt to replace an all_of/any_of horizontal reduction with a MOVMSK.
- if (SDValue Cmp = combinePredicateReduction(N, DAG, Subtarget))
- return Cmp;
-
// Attempt to optimize ADD/FADD reductions with HADD, promotion etc..
if (SDValue V = combineArithReduction(N, DAG, Subtarget))
return V;
@@ -63121,6 +63125,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::VFCMULC:
case X86ISD::VFMULC: return combineFMulcFCMulc(N, DAG, Subtarget);
case ISD::FNEG: return combineFneg(N, DAG, DCI, Subtarget);
+ case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
+ case ISD::VECREDUCE_XOR: return combineVECREDUCE_LOGIC(N, DAG, Subtarget);
case ISD::VECREDUCE_MUL: return combineVECREDUCE_MUL(N, DAG, Subtarget);
case ISD::TRUNCATE: return combineTruncate(N, DAG, Subtarget);
case X86ISD::VTRUNC: return combineVTRUNC(N, DAG, DCI);
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 354eeeb583ba8..a421a02fd15db 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -6927,6 +6927,9 @@ bool X86TTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
switch (II->getIntrinsicID()) {
default:
return true;
+ case Intrinsic::vector_reduce_and:
+ case Intrinsic::vector_reduce_or:
+ case Intrinsic::vector_reduce_xor:
case Intrinsic::vector_reduce_mul:
case Intrinsic::vector_reduce_smax:
case Intrinsic::vector_reduce_smin:
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
index a2caf173dd8ae..24c358f52c794 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
@@ -6614,7 +6614,7 @@ define i64 @test_mm512_reduce_or_epi64(<8 x i64> %__W) nounwind {
; X86-LABEL: test_mm512_reduce_or_epi64:
; X86: # %bb.0: # %entry
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpor %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6627,7 +6627,7 @@ define i64 @test_mm512_reduce_or_epi64(<8 x i64> %__W) nounwind {
; X64-LABEL: test_mm512_reduce_or_epi64:
; X64: # %bb.0: # %entry
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6644,7 +6644,7 @@ define i64 @test_mm512_reduce_and_epi64(<8 x i64> %__W) nounwind {
; X86-LABEL: test_mm512_reduce_and_epi64:
; X86: # %bb.0: # %entry
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpand %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6657,7 +6657,7 @@ define i64 @test_mm512_reduce_and_epi64(<8 x i64> %__W) nounwind {
; X64-LABEL: test_mm512_reduce_and_epi64:
; X64: # %bb.0: # %entry
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpand %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6789,7 +6789,7 @@ define i64 @test_mm512_mask_reduce_and_epi64(i8 zeroext %__M, <8 x i64> %__W) no
; X86-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X86-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpandq %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpand %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6805,7 +6805,7 @@ define i64 @test_mm512_mask_reduce_and_epi64(i8 zeroext %__M, <8 x i64> %__W) no
; X64-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X64-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpandq %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpand %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6827,7 +6827,7 @@ define i64 @test_mm512_mask_reduce_or_epi64(i8 zeroext %__M, <8 x i64> %__W) nou
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpor %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6842,7 +6842,7 @@ define i64 @test_mm512_mask_reduce_or_epi64(i8 zeroext %__M, <8 x i64> %__W) nou
; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6901,7 +6901,7 @@ define i32 @test_mm512_reduce_or_epi32(<8 x i64> %__W) nounwind {
; CHECK-LABEL: test_mm512_reduce_or_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpor %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6921,7 +6921,7 @@ define i32 @test_mm512_reduce_and_epi32(<8 x i64> %__W) nounwind {
; CHECK-LABEL: test_mm512_reduce_and_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpand %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7029,7 +7029,7 @@ define i32 @test_mm512_mask_reduce_and_epi32(i16 zeroext %__M, <8 x i64> %__W) n
; X86-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X86-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpandd %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpand %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7046,7 +7046,7 @@ define i32 @test_mm512_mask_reduce_and_epi32(i16 zeroext %__M, <8 x i64> %__W) n
; X64-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X64-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpandd %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpand %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7071,7 +7071,7 @@ define i32 @test_mm512_mask_reduce_or_epi32(i16 zeroext %__M, <8 x i64> %__W) no
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vpord %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpor %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7087,7 +7087,7 @@ define i32 @test_mm512_mask_reduce_or_epi32(i16 zeroext %__M, <8 x i64> %__W) no
; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vpord %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
diff --git a/llvm/test/CodeGen/X86/pr53419.ll b/llvm/test/CodeGen/X86/pr53419.ll
index 750751d404f38..b4c01676d73b4 100644
--- a/llvm/test/CodeGen/X86/pr53419.ll
+++ b/llvm/test/CodeGen/X86/pr53419.ll
@@ -15,8 +15,8 @@ declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
define i1 @intrinsic_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X64-LABEL: intrinsic_v2i8:
; X64: # %bb.0: # %bb
-; X64-NEXT: movzwl (%rsi), %eax
-; X64-NEXT: cmpw (%rdi), %ax
+; X64-NEXT: movzwl (%rdi), %eax
+; X64-NEXT: cmpw %ax, (%rsi)
; X64-NEXT: sete %al
; X64-NEXT: retq
;
@@ -24,8 +24,8 @@ define i1 @intrinsic_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X86: # %bb.0: # %bb
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movzwl (%ecx), %ecx
-; X86-NEXT: cmpw (%eax), %cx
+; X86-NEXT: movzwl (%eax), %eax
+; X86-NEXT: cmpw %ax, (%ecx)
; X86-NEXT: sete %al
; X86-NEXT: retl
bb:
@@ -39,8 +39,8 @@ bb:
define i1 @intrinsic_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X64-LABEL: intrinsic_v4i8:
; X64: # %bb.0: # %bb
-; X64-NEXT: movl (%rsi), %eax
-; X64-NEXT: cmpl (%rdi), %eax
+; X64-NEXT: movl (%rdi), %eax
+; X64-NEXT: cmpl %eax, (%rsi)
; X64-NEXT: sete %al
; X64-NEXT: retq
;
@@ -48,8 +48,8 @@ define i1 @intrinsic_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X86: # %bb.0: # %bb
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl (%ecx), %ecx
-; X86-NEXT: cmpl (%eax), %ecx
+; X86-NEXT: movl (%eax), %eax
+; X86-NEXT: cmpl %eax, (%ecx)
; X86-NEXT: sete %al
; X86-NEXT: retl
bb:
@@ -63,8 +63,8 @@ bb:
define i1 @intrinsic_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X64-LABEL: intrinsic_v8i8:
; X64: # %bb.0: # %bb
-; X64-NEXT: movq (%rsi), %rax
-; X64-NEXT: cmpq (%rdi), %rax
+; X64-NEXT: movq (%rdi), %rax
+; X64-NEXT: cmpq %rax, (%rsi)
; X64-NEXT: sete %al
; X64-NEXT: retq
;
@@ -72,11 +72,11 @@ define i1 @intrinsic_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X86: # %bb.0: # %bb
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl (%ecx), %edx
-; X86-NEXT: movl 4(%ecx), %ecx
-; X86-NEXT: xorl 4(%eax), %ecx
-; X86-NEXT: xorl (%eax), %edx
-; X86-NEXT: orl %ecx, %edx
+; X86-NEXT: movl (%eax), %edx
+; X86-NEXT: movl 4(%eax), %eax
+; X86-NEXT: xorl 4(%ecx), %eax
+; X86-NEXT: xorl (%ecx), %edx
+; X86-NEXT: orl %eax, %edx
; X86-NEXT: sete %al
; X86-NEXT: retl
bb:
diff --git a/llvm/test/CodeGen/X86/vector-extract-last-active.ll b/llvm/test/CodeGen/X86/vector-extract-last-active.ll
index 3f0a0c587415e..d3469d561184f 100644
--- a/llvm/test/CodeGen/X86/vector-extract-last-active.ll
+++ b/llvm/test/CodeGen/X86/vector-extract-last-active.ll
@@ -8,35 +8,30 @@
define i32 @extract_last_active_v4i32(<4 x i32> %a, <4 x i1> %c) {
; CHECK-LABEL: extract_last_active_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
-; CHECK-NEXT: por %xmm1, %xmm2
; CHECK-NEXT: pslld $31, %xmm1
+; CHECK-NEXT: movmskps %xmm1, %ecx
; CHECK-NEXT: psrad $31, %xmm1
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
-; CHECK-NEXT: movdqa %xmm1, %xmm3
-; CHECK-NEXT: por %xmm0, %xmm3
-; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
-; CHECK-NEXT: por %xmm4, %xmm0
-; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
-; CHECK-NEXT: pand %xmm3, %xmm1
-; CHECK-NEXT: pandn %xmm4, %xmm3
-; CHECK-NEXT: por %xmm1, %xmm3
-; CHECK-NEXT: movd %xmm3, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1]
-; CHECK-NEXT: movd %xmm0, %ecx
-; CHECK-NEXT: cmpl %ecx, %eax
-; CHECK-NEXT: cmoval %eax, %ecx
-; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: por %xmm0, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: por %xmm3, %xmm0
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
+; CHECK-NEXT: pand %xmm2, %xmm1
+; CHECK-NEXT: pandn %xmm3, %xmm2
+; CHECK-NEXT: por %xmm1, %xmm2
+; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; CHECK-NEXT: por %xmm2, %xmm0
; CHECK-NEXT: movd %xmm0, %edx
-; CHECK-NEXT: andb $1, %dl
+; CHECK-NEXT: cmpl %edx, %eax
+; CHECK-NEXT: cmoval %eax, %edx
+; CHECK-NEXT: andl $3, %edx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb $1, %dl
+; CHECK-NEXT: cmpl $1, %ecx
; CHECK-NEXT: sbbl %eax, %eax
-; CHECK-NEXT: orl -24(%rsp,%rcx,4), %eax
+; CHECK-NEXT: orl -24(%rsp,%rdx,4), %eax
; CHECK-NEXT: retq
%res = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> %a, <4 x i1> %c, i32 -1)
ret i32 %res
@@ -74,14 +69,11 @@ define i32 @extract_last_active_v4i32_no_default(<4 x i32> %a, <4 x i1> %c) {
define i32 @extract_last_active_v2i32(<2 x i32> %a, <2 x i1> %c) {
; CHECK-LABEL: extract_last_active_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
-; CHECK-NEXT: por %xmm1, %xmm2
-; CHECK-NEXT: psllq $63, %xmm1
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movq %xmm2, %rcx
-; CHECK-NEXT: andb $1, %cl
+; CHECK-NEXT: psllq $63, %xmm1
+; CHECK-NEXT: movmskpd %xmm1, %ecx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb $1, %cl
+; CHECK-NEXT: cmpl $1, %ecx
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3]
; CHECK-NEXT: psrld $31, %xmm0
@@ -141,34 +133,28 @@ define i32 @extract_last_active_v3i32(<3 x i32> %a, <3 x i1> %c) {
define i32 @extract_last_active_v8i32(<8 x i32> %a, <8 x i1> %c) {
; CHECK-LABEL: extract_last_active_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
-; CHECK-NEXT: por %xmm2, %xmm3
-; CHECK-NEXT: psllw $15, %xmm2
-; CHECK-NEXT: psraw $15, %xmm2
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1]
-; CHECK-NEXT: por %xmm3, %xmm0
-; CHECK-NEXT: movdqa %xmm0, %xmm1
-; CHECK-NEXT: psrld $16, %xmm1
-; CHECK-NEXT: por %xmm0, %xmm1
-; CHECK-NEXT: movd %xmm1, %ecx
-; CHECK-NEXT: andb $1, %cl
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb $1, %cl
-; CHECK-NEXT: sbbl %eax, %eax
-; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
-; CHECK-NEXT: psubusw %xmm2, %xmm0
-; CHECK-NEXT: paddw %xmm2, %xmm0
-; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; CHECK-NEXT: psllw $15, %xmm2
+; CHECK-NEXT: movdqa %xmm2, %xmm0
+; CHECK-NEXT: psraw $15, %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; CHECK-NEXT: psubusw %xmm0, %xmm1
; CHECK-NEXT: paddw %xmm0, %xmm1
-; CHECK-NEXT: pextrw $1, %xmm1, %ecx
-; CHECK-NEXT: movd %xmm1, %edx
-; CHECK-NEXT: cmpw %cx, %dx
-; CHECK-NEXT: cmoval %edx, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; CHECK-NEXT: psubusw %xmm1, %xmm0
+; CHECK-NEXT: paddw %xmm1, %xmm0
+; CHECK-NEXT: pextrw $1, %xmm0, %ecx
+; CHECK-NEXT: movd %xmm0, %eax
+; CHECK-NEXT: cmpw %cx, %ax
+; CHECK-NEXT: cmoval %eax, %ecx
; CHECK-NEXT: andl $7, %ecx
+; CHECK-NEXT: packsswb %xmm2, %xmm2
+; CHECK-NEXT: pmovmskb %xmm2, %edx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb $1, %dl
+; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: orl -40(%rsp,%rcx,4), %eax
; CHECK-NEXT: retq
%res = call i32 @llvm.experimental.vector.extract.last.active.v8i32(<8 x i32> %a, <8 x i1> %c, i32 -1)
@@ -179,18 +165,16 @@ define i32 @extract_last_active_v8i32(<8 x i32> %a, <8 x i1> %c) {
define i32 @extract_last_active_v16i32(<16 x i32> %a, <16 x i1> %c) {
; CHECK-LABEL: extract_last_active_v16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
-; CHECK-NEXT: por %xmm4, %xmm5
+; CHECK-NEXT: pxor %xmm5, %xmm5
; CHECK-NEXT: psllw $7, %xmm4
-; CHECK-NEXT: pxor %xmm6, %xmm6
-; CHECK-NEXT: pcmpgtb %xmm4, %xmm6
+; CHECK-NEXT: pcmpgtb %xmm4, %xmm5
; CHECK-NEXT: movaps %xmm3, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm6[2,3,2,3]
-; CHECK-NEXT: pmaxub %xmm6, %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm5[2,3,2,3]
+; CHECK-NEXT: pmaxub %xmm5, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
; CHECK-NEXT: pmaxub %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
@@ -201,18 +185,9 @@ define i32 @extract_last_active_v16i32(<16 x i32> %a, <16 x i1> %c) {
; CHECK-NEXT: pmaxub %xmm0, %xmm1
; CHECK-NEXT: movd %xmm1, %ecx
; CHECK-NEXT: andl $15, %ecx
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,1,1]
-; CHECK-NEXT: por %xmm5, %xmm0
-; CHECK-NEXT: movdqa %xmm0, %xmm1
-; CHECK-NEXT: psrld $16, %xmm1
-; CHECK-NEXT: por %xmm0, %xmm1
-; CHECK-NEXT: movdqa %xmm1, %xmm0
-; CHECK-NEXT: psrlw $8, %xmm0
-; CHECK-NEXT: por %xmm1, %xmm0
-; CHECK-NEXT: movd %xmm0, %edx
-; CHECK-NEXT: andb $1, %dl
+; CHECK-NEXT: pmovmskb %xmm4, %edx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb $1, %dl
+; CHECK-NEXT: cmpl $1, %edx
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: orl -72(%rsp,%rcx,4), %eax
; CHECK-NEXT: retq
@@ -244,26 +219,26 @@ define i32 @extract_last_active_v4i32_penryn(<4 x i32> %a, <4 x i1> %c) "target-
define i8 @extract_last_active_split(<32 x i8> %data, <32 x i8> %mask, i8 %passthru) {
; CHECK-LABEL: extract_last_active_split:
; CHECK: # %bb.0:
-; CHECK-NEXT: movdqa %xmm2, %xmm4
-; CHECK-NEXT: por %xmm3, %xmm4
-; CHECK-NEXT: pxor %xmm5, %xmm5
-; CHECK-NEXT: pcmpeqb %xmm5, %xmm3
-; CHECK-NEXT: pcmpeqb %xmm5, %xmm2
+; CHECK-NEXT: pxor %xmm4, %xmm4
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: por %xmm3, %xmm2
+; CHECK-NEXT: pcmpeqb %xmm4, %xmm3
+; CHECK-NEXT: pcmpeqb %xmm4, %xmm5
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
-; CHECK-NEXT: pandn %xmm0, %xmm2
-; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
-; CHECK-NEXT: pmaxub %xmm2, %xmm1
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
-; CHECK-NEXT: pmaxub %xmm1, %xmm2
-; CHECK-NEXT: movdqa %xmm2, %xmm1
+; CHECK-NEXT: pandn %xmm0, %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm5[2,3,2,3]
+; CHECK-NEXT: pmaxub %xmm5, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,1,1]
+; CHECK-NEXT: pmaxub %xmm1, %xmm5
+; CHECK-NEXT: movdqa %xmm5, %xmm1
; CHECK-NEXT: psrld $16, %xmm1
-; CHECK-NEXT: pmaxub %xmm2, %xmm1
-; CHECK-NEXT: movdqa %xmm1, %xmm2
-; CHECK-NEXT: psrlw $8, %xmm2
-; CHECK-NEXT: pmaxub %xmm1, %xmm2
-; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: pmaxub %xmm5, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm5
+; CHECK-NEXT: psrlw $8, %xmm5
+; CHECK-NEXT: pmaxub %xmm1, %xmm5
+; CHECK-NEXT: movd %xmm5, %eax
; CHECK-NEXT: pmovmskb %xmm3, %ecx
; CHECK-NEXT: pandn %xmm0, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3]
@@ -282,9 +257,9 @@ define i8 @extract_last_active_split(<32 x i8> %data, <32 x i8> %mask, i8 %passt
; CHECK-NEXT: cmoveq %rax, %rdx
; CHECK-NEXT: andl $31, %edx
; CHECK-NEXT: movzbl -40(%rsp,%rdx), %eax
-; CHECK-NEXT: pcmpeqb %xmm5, %xmm4
-; CHECK-NEXT: pmovmskb %xmm4, %ecx
-; CHECK-NEXT: cmpl $65535, %ecx # imm = 0xFFFF
+; CHECK-NEXT: pcmpeqb %xmm4, %xmm2
+; CHECK-NEXT: pmovmskb %xmm2, %ecx
+; CHECK-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; CHECK-NEXT: cmovel %edi, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-reduce-and.ll b/llvm/test/CodeGen/X86/vector-reduce-and.ll
index 415939107e931..16d7fc8439ffc 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-and.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-and.ll
@@ -260,7 +260,7 @@ define i64 @test_v8i64(<8 x i64> %a0) nounwind {
; AVX512-LABEL: test_v8i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -280,17 +280,17 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE2-NEXT: pand 56(%ebp), %xmm2
-; X86-SSE2-NEXT: pand 24(%ebp), %xmm0
-; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: pand 72(%ebp), %xmm3
; X86-SSE2-NEXT: pand 40(%ebp), %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm1
-; X86-SSE2-NEXT: pand %xmm0, %xmm1
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE2-NEXT: pand 56(%ebp), %xmm2
+; X86-SSE2-NEXT: pand 24(%ebp), %xmm0
+; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0
-; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE2-NEXT: pand %xmm0, %xmm1
+; X86-SSE2-NEXT: movd %xmm1, %eax
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE2-NEXT: movd %xmm0, %edx
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
@@ -298,16 +298,16 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
;
; X64-SSE-LABEL: test_v16i64:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pand %xmm6, %xmm2
-; X64-SSE-NEXT: pand %xmm4, %xmm0
-; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm7, %xmm3
; X64-SSE-NEXT: pand %xmm5, %xmm1
; X64-SSE-NEXT: pand %xmm3, %xmm1
-; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pand %xmm6, %xmm2
+; X64-SSE-NEXT: pand %xmm4, %xmm0
+; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm1, %xmm0
-; X64-SSE-NEXT: movq %xmm0, %rax
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-SSE-NEXT: pand %xmm0, %xmm1
+; X64-SSE-NEXT: movq %xmm1, %rax
; X64-SSE-NEXT: retq
;
; X86-SSE4-LABEL: test_v16i64:
@@ -317,17 +317,17 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE4-NEXT: pand 56(%ebp), %xmm2
-; X86-SSE4-NEXT: pand 24(%ebp), %xmm0
-; X86-SSE4-NEXT: pand %xmm2, %xmm0
; X86-SSE4-NEXT: pand 72(%ebp), %xmm3
; X86-SSE4-NEXT: pand 40(%ebp), %xmm1
; X86-SSE4-NEXT: pand %xmm3, %xmm1
-; X86-SSE4-NEXT: pand %xmm0, %xmm1
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE4-NEXT: pand 56(%ebp), %xmm2
+; X86-SSE4-NEXT: pand 24(%ebp), %xmm0
+; X86-SSE4-NEXT: pand %xmm2, %xmm0
; X86-SSE4-NEXT: pand %xmm1, %xmm0
-; X86-SSE4-NEXT: movd %xmm0, %eax
-; X86-SSE4-NEXT: pextrd $1, %xmm0, %edx
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE4-NEXT: pand %xmm0, %xmm1
+; X86-SSE4-NEXT: movd %xmm1, %eax
+; X86-SSE4-NEXT: pextrd $1, %xmm1, %edx
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
; X86-SSE4-NEXT: retl
@@ -402,7 +402,7 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -568,7 +568,7 @@ define i32 @test_v16i32(<16 x i32> %a0) nounwind {
; AVX512-LABEL: test_v16i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -590,36 +590,36 @@ define i32 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: pand 56(%ebp), %xmm2
-; X86-SSE-NEXT: pand 24(%ebp), %xmm0
-; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand 72(%ebp), %xmm3
; X86-SSE-NEXT: pand 40(%ebp), %xmm1
; X86-SSE-NEXT: pand %xmm3, %xmm1
-; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: pand 56(%ebp), %xmm2
+; X86-SSE-NEXT: pand 24(%ebp), %xmm0
+; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: movd %xmm1, %eax
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X86-SSE-NEXT: pand %xmm1, %xmm0
+; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: test_v32i32:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pand %xmm6, %xmm2
-; X64-SSE-NEXT: pand %xmm4, %xmm0
-; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm7, %xmm3
; X64-SSE-NEXT: pand %xmm5, %xmm1
; X64-SSE-NEXT: pand %xmm3, %xmm1
-; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pand %xmm6, %xmm2
+; X64-SSE-NEXT: pand %xmm4, %xmm0
+; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: movd %xmm1, %eax
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X64-SSE-NEXT: pand %xmm1, %xmm0
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: retq
;
; X86-AVX1-LABEL: test_v32i32:
@@ -698,7 +698,7 @@ define i32 @test_v32i32(<32 x i32> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpandd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -811,9 +811,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
@@ -826,9 +826,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
@@ -841,9 +841,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -899,9 +899,9 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
@@ -915,9 +915,9 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
@@ -928,13 +928,13 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX512-LABEL: test_v32i16:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -953,21 +953,21 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: pand 56(%ebp), %xmm2
-; X86-SSE-NEXT: pand 24(%ebp), %xmm0
-; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand 72(%ebp), %xmm3
; X86-SSE-NEXT: pand 40(%ebp), %xmm1
; X86-SSE-NEXT: pand %xmm3, %xmm1
-; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: pand 56(%ebp), %xmm2
+; X86-SSE-NEXT: pand 24(%ebp), %xmm0
+; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: movdqa %xmm1, %xmm0
-; X86-SSE-NEXT: psrld $16, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE-NEXT: pand %xmm1, %xmm0
-; X86-SSE-NEXT: movd %xmm0, %eax
+; X86-SSE-NEXT: movdqa %xmm0, %xmm1
+; X86-SSE-NEXT: psrld $16, %xmm1
+; X86-SSE-NEXT: pand %xmm0, %xmm1
+; X86-SSE-NEXT: movd %xmm1, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
@@ -975,21 +975,21 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
;
; X64-SSE-LABEL: test_v64i16:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pand %xmm6, %xmm2
-; X64-SSE-NEXT: pand %xmm4, %xmm0
-; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm7, %xmm3
; X64-SSE-NEXT: pand %xmm5, %xmm1
; X64-SSE-NEXT: pand %xmm3, %xmm1
-; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pand %xmm6, %xmm2
+; X64-SSE-NEXT: pand %xmm4, %xmm0
+; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: movdqa %xmm1, %xmm0
-; X64-SSE-NEXT: psrld $16, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X64-SSE-NEXT: pand %xmm1, %xmm0
-; X64-SSE-NEXT: movd %xmm0, %eax
+; X64-SSE-NEXT: movdqa %xmm0, %xmm1
+; X64-SSE-NEXT: psrld $16, %xmm1
+; X64-SSE-NEXT: pand %xmm0, %xmm1
+; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X64-SSE-NEXT: retq
;
@@ -1005,9 +1005,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; X86-AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
@@ -1025,9 +1025,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; X64-AVX1-NEXT: vpand %xmm0, %xmm1, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
@@ -1047,9 +1047,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; X86-AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
@@ -1067,9 +1067,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; X64-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
+; X64-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; X64-AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
@@ -1081,13 +1081,13 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpand %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -1369,7 +1369,7 @@ define i8 @test_v64i8(<64 x i8> %a0) nounwind {
; AVX512-LABEL: test_v64i8:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -1396,24 +1396,24 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: pand 56(%ebp), %xmm2
-; X86-SSE-NEXT: pand 24(%ebp), %xmm0
-; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand 72(%ebp), %xmm3
; X86-SSE-NEXT: pand 40(%ebp), %xmm1
; X86-SSE-NEXT: pand %xmm3, %xmm1
-; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: pand 56(%ebp), %xmm2
+; X86-SSE-NEXT: pand 24(%ebp), %xmm0
+; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: movdqa %xmm1, %xmm0
-; X86-SSE-NEXT: psrld $16, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE-NEXT: pand %xmm1, %xmm0
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
-; X86-SSE-NEXT: psrlw $8, %xmm1
+; X86-SSE-NEXT: psrld $16, %xmm1
; X86-SSE-NEXT: pand %xmm0, %xmm1
-; X86-SSE-NEXT: movd %xmm1, %eax
+; X86-SSE-NEXT: movdqa %xmm1, %xmm0
+; X86-SSE-NEXT: psrlw $8, %xmm0
+; X86-SSE-NEXT: pand %xmm1, %xmm0
+; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: # kill: def $al killed $al killed $eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
@@ -1421,24 +1421,24 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
;
; X64-SSE-LABEL: test_v128i8:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pand %xmm6, %xmm2
-; X64-SSE-NEXT: pand %xmm4, %xmm0
-; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm7, %xmm3
; X64-SSE-NEXT: pand %xmm5, %xmm1
; X64-SSE-NEXT: pand %xmm3, %xmm1
-; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pand %xmm6, %xmm2
+; X64-SSE-NEXT: pand %xmm4, %xmm0
+; X64-SSE-NEXT: pand %xmm2, %xmm0
; X64-SSE-NEXT: pand %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: movdqa %xmm1, %xmm0
-; X64-SSE-NEXT: psrld $16, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X64-SSE-NEXT: pand %xmm1, %xmm0
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
-; X64-SSE-NEXT: psrlw $8, %xmm1
+; X64-SSE-NEXT: psrld $16, %xmm1
; X64-SSE-NEXT: pand %xmm0, %xmm1
-; X64-SSE-NEXT: movd %xmm1, %eax
+; X64-SSE-NEXT: movdqa %xmm1, %xmm0
+; X64-SSE-NEXT: psrlw $8, %xmm0
+; X64-SSE-NEXT: pand %xmm1, %xmm0
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: # kill: def $al killed $al killed $eax
; X64-SSE-NEXT: retq
;
@@ -1538,7 +1538,7 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index b47db1c9c8358..a1ff4327ac29e 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -17,7 +17,7 @@
; vXi64
;
-define i1 @test_v2i64(<2 x i64> %a0) nounwind {
+define i1 @test_v2i64(<2 x i64> %a0) {
; SSE2-LABEL: test_v2i64:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
@@ -43,7 +43,7 @@ define i1 @test_v2i64(<2 x i64> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v4i64(<4 x i64> %a0) nounwind {
+define i1 @test_v4i64(<4 x i64> %a0) {
; SSE2-LABEL: test_v4i64:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
@@ -72,11 +72,14 @@ define i1 @test_v4i64(<4 x i64> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v8i64(<8 x i64> %a0) nounwind {
+define i1 @test_v8i64(<8 x i64> %a0) {
; X86-SSE2-LABEL: test_v8i64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: por %xmm2, %xmm0
@@ -89,6 +92,7 @@ define i1 @test_v8i64(<8 x i64> %a0) nounwind {
; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v8i64:
@@ -106,7 +110,10 @@ define i1 @test_v8i64(<8 x i64> %a0) nounwind {
; X86-SSE4-LABEL: test_v8i64:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: por %xmm2, %xmm0
@@ -116,6 +123,7 @@ define i1 @test_v8i64(<8 x i64> %a0) nounwind {
; X86-SSE4-NEXT: sete %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v8i64:
@@ -155,11 +163,14 @@ define i1 @test_v8i64(<8 x i64> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v16i64(<16 x i64> %a0) nounwind {
+define i1 @test_v16i64(<16 x i64> %a0) {
; X86-SSE2-LABEL: test_v16i64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
@@ -177,6 +188,7 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v16i64:
@@ -198,7 +210,10 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE4-LABEL: test_v16i64:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
@@ -213,6 +228,7 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE4-NEXT: setne %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v16i64:
@@ -231,7 +247,10 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-AVX1-LABEL: test_v16i64:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: pushl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX1-NEXT: .cfi_offset %ebp, -8
; X86-AVX1-NEXT: movl %esp, %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX1-NEXT: andl $-32, %esp
; X86-AVX1-NEXT: subl $32, %esp
; X86-AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
@@ -241,6 +260,7 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-AVX1-NEXT: setne %al
; X86-AVX1-NEXT: movl %ebp, %esp
; X86-AVX1-NEXT: popl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -257,7 +277,10 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-AVX2-LABEL: test_v16i64:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: pushl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX2-NEXT: .cfi_offset %ebp, -8
; X86-AVX2-NEXT: movl %esp, %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX2-NEXT: andl $-32, %esp
; X86-AVX2-NEXT: subl $32, %esp
; X86-AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
@@ -267,6 +290,7 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-AVX2-NEXT: setne %al
; X86-AVX2-NEXT: movl %ebp, %esp
; X86-AVX2-NEXT: popl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -297,7 +321,7 @@ define i1 @test_v16i64(<16 x i64> %a0) nounwind {
; vXi32
;
-define i1 @test_v2i32(<2 x i32> %a0) nounwind {
+define i1 @test_v2i32(<2 x i32> %a0) {
; X86-SSE2-LABEL: test_v2i32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movd %xmm0, %eax
@@ -363,7 +387,7 @@ define i1 @test_v2i32(<2 x i32> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v4i32(<4 x i32> %a0) nounwind {
+define i1 @test_v4i32(<4 x i32> %a0) {
; SSE2-LABEL: test_v4i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
@@ -389,7 +413,7 @@ define i1 @test_v4i32(<4 x i32> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v8i32(<8 x i32> %a0) nounwind {
+define i1 @test_v8i32(<8 x i32> %a0) {
; SSE2-LABEL: test_v8i32:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
@@ -418,11 +442,14 @@ define i1 @test_v8i32(<8 x i32> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v16i32(<16 x i32> %a0) nounwind {
+define i1 @test_v16i32(<16 x i32> %a0) {
; X86-SSE2-LABEL: test_v16i32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: por %xmm2, %xmm0
@@ -435,6 +462,7 @@ define i1 @test_v16i32(<16 x i32> %a0) nounwind {
; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v16i32:
@@ -452,7 +480,10 @@ define i1 @test_v16i32(<16 x i32> %a0) nounwind {
; X86-SSE4-LABEL: test_v16i32:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: por %xmm2, %xmm0
@@ -462,6 +493,7 @@ define i1 @test_v16i32(<16 x i32> %a0) nounwind {
; X86-SSE4-NEXT: setne %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v16i32:
@@ -501,11 +533,14 @@ define i1 @test_v16i32(<16 x i32> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v32i32(<32 x i32> %a0) nounwind {
+define i1 @test_v32i32(<32 x i32> %a0) {
; X86-SSE2-LABEL: test_v32i32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
@@ -523,6 +558,7 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v32i32:
@@ -544,7 +580,10 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-SSE4-LABEL: test_v32i32:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
@@ -559,6 +598,7 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-SSE4-NEXT: sete %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v32i32:
@@ -577,7 +617,10 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-AVX1-LABEL: test_v32i32:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: pushl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX1-NEXT: .cfi_offset %ebp, -8
; X86-AVX1-NEXT: movl %esp, %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX1-NEXT: andl $-32, %esp
; X86-AVX1-NEXT: subl $32, %esp
; X86-AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
@@ -587,6 +630,7 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-AVX1-NEXT: sete %al
; X86-AVX1-NEXT: movl %ebp, %esp
; X86-AVX1-NEXT: popl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -603,7 +647,10 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-AVX2-LABEL: test_v32i32:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: pushl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX2-NEXT: .cfi_offset %ebp, -8
; X86-AVX2-NEXT: movl %esp, %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX2-NEXT: andl $-32, %esp
; X86-AVX2-NEXT: subl $32, %esp
; X86-AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
@@ -613,6 +660,7 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-AVX2-NEXT: sete %al
; X86-AVX2-NEXT: movl %ebp, %esp
; X86-AVX2-NEXT: popl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -643,7 +691,7 @@ define i1 @test_v32i32(<32 x i32> %a0) nounwind {
; vXi16
;
-define i1 @test_v2i16(<2 x i16> %a0) nounwind {
+define i1 @test_v2i16(<2 x i16> %a0) {
; SSE-LABEL: test_v2i16:
; SSE: # %bb.0:
; SSE-NEXT: movd %xmm0, %eax
@@ -662,7 +710,7 @@ define i1 @test_v2i16(<2 x i16> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v4i16(<4 x i16> %a0) nounwind {
+define i1 @test_v4i16(<4 x i16> %a0) {
; X86-SSE2-LABEL: test_v4i16:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movd %xmm0, %eax
@@ -728,7 +776,7 @@ define i1 @test_v4i16(<4 x i16> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v8i16(<8 x i16> %a0) nounwind {
+define i1 @test_v8i16(<8 x i16> %a0) {
; SSE2-LABEL: test_v8i16:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
@@ -754,7 +802,7 @@ define i1 @test_v8i16(<8 x i16> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v16i16(<16 x i16> %a0) nounwind {
+define i1 @test_v16i16(<16 x i16> %a0) {
; SSE2-LABEL: test_v16i16:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
@@ -783,11 +831,14 @@ define i1 @test_v16i16(<16 x i16> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v32i16(<32 x i16> %a0) nounwind {
+define i1 @test_v32i16(<32 x i16> %a0) {
; X86-SSE2-LABEL: test_v32i16:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: por %xmm2, %xmm0
@@ -800,6 +851,7 @@ define i1 @test_v32i16(<32 x i16> %a0) nounwind {
; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v32i16:
@@ -817,7 +869,10 @@ define i1 @test_v32i16(<32 x i16> %a0) nounwind {
; X86-SSE4-LABEL: test_v32i16:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: por %xmm2, %xmm0
@@ -827,6 +882,7 @@ define i1 @test_v32i16(<32 x i16> %a0) nounwind {
; X86-SSE4-NEXT: sete %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v32i16:
@@ -866,11 +922,14 @@ define i1 @test_v32i16(<32 x i16> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v64i16(<64 x i16> %a0) nounwind {
+define i1 @test_v64i16(<64 x i16> %a0) {
; X86-SSE2-LABEL: test_v64i16:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
@@ -888,6 +947,7 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v64i16:
@@ -909,7 +969,10 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-SSE4-LABEL: test_v64i16:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
@@ -924,6 +987,7 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-SSE4-NEXT: setne %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v64i16:
@@ -942,7 +1006,10 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX1-LABEL: test_v64i16:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: pushl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX1-NEXT: .cfi_offset %ebp, -8
; X86-AVX1-NEXT: movl %esp, %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX1-NEXT: andl $-32, %esp
; X86-AVX1-NEXT: subl $32, %esp
; X86-AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
@@ -952,6 +1019,7 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX1-NEXT: setne %al
; X86-AVX1-NEXT: movl %ebp, %esp
; X86-AVX1-NEXT: popl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -968,7 +1036,10 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX2-LABEL: test_v64i16:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: pushl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX2-NEXT: .cfi_offset %ebp, -8
; X86-AVX2-NEXT: movl %esp, %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX2-NEXT: andl $-32, %esp
; X86-AVX2-NEXT: subl $32, %esp
; X86-AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
@@ -978,6 +1049,7 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX2-NEXT: setne %al
; X86-AVX2-NEXT: movl %ebp, %esp
; X86-AVX2-NEXT: popl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1008,7 +1080,7 @@ define i1 @test_v64i16(<64 x i16> %a0) nounwind {
; vXi8
;
-define i1 @test_v2i8(<2 x i8> %a0) nounwind {
+define i1 @test_v2i8(<2 x i8> %a0) {
; SSE-LABEL: test_v2i8:
; SSE: # %bb.0:
; SSE-NEXT: movd %xmm0, %eax
@@ -1027,7 +1099,7 @@ define i1 @test_v2i8(<2 x i8> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v4i8(<4 x i8> %a0) nounwind {
+define i1 @test_v4i8(<4 x i8> %a0) {
; SSE-LABEL: test_v4i8:
; SSE: # %bb.0:
; SSE-NEXT: movd %xmm0, %eax
@@ -1046,7 +1118,7 @@ define i1 @test_v4i8(<4 x i8> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v8i8(<8 x i8> %a0) nounwind {
+define i1 @test_v8i8(<8 x i8> %a0) {
; X86-SSE2-LABEL: test_v8i8:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movd %xmm0, %eax
@@ -1112,7 +1184,7 @@ define i1 @test_v8i8(<8 x i8> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v16i8(<16 x i8> %a0) nounwind {
+define i1 @test_v16i8(<16 x i8> %a0) {
; SSE2-LABEL: test_v16i8:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
@@ -1138,7 +1210,7 @@ define i1 @test_v16i8(<16 x i8> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v32i8(<32 x i8> %a0) nounwind {
+define i1 @test_v32i8(<32 x i8> %a0) {
; SSE2-LABEL: test_v32i8:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
@@ -1167,11 +1239,14 @@ define i1 @test_v32i8(<32 x i8> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v64i8(<64 x i8> %a0) nounwind {
+define i1 @test_v64i8(<64 x i8> %a0) {
; X86-SSE2-LABEL: test_v64i8:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: por %xmm2, %xmm0
@@ -1184,6 +1259,7 @@ define i1 @test_v64i8(<64 x i8> %a0) nounwind {
; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v64i8:
@@ -1201,7 +1277,10 @@ define i1 @test_v64i8(<64 x i8> %a0) nounwind {
; X86-SSE4-LABEL: test_v64i8:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: por %xmm2, %xmm0
@@ -1211,6 +1290,7 @@ define i1 @test_v64i8(<64 x i8> %a0) nounwind {
; X86-SSE4-NEXT: setne %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v64i8:
@@ -1250,11 +1330,14 @@ define i1 @test_v64i8(<64 x i8> %a0) nounwind {
ret i1 %2
}
-define i1 @test_v128i8(<128 x i8> %a0) nounwind {
+define i1 @test_v128i8(<128 x i8> %a0) {
; X86-SSE2-LABEL: test_v128i8:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
@@ -1272,6 +1355,7 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: test_v128i8:
@@ -1293,7 +1377,10 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE4-LABEL: test_v128i8:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
@@ -1308,6 +1395,7 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE4-NEXT: sete %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: test_v128i8:
@@ -1326,7 +1414,10 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX1-LABEL: test_v128i8:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: pushl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX1-NEXT: .cfi_offset %ebp, -8
; X86-AVX1-NEXT: movl %esp, %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX1-NEXT: andl $-32, %esp
; X86-AVX1-NEXT: subl $32, %esp
; X86-AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
@@ -1336,6 +1427,7 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX1-NEXT: sete %al
; X86-AVX1-NEXT: movl %ebp, %esp
; X86-AVX1-NEXT: popl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1352,7 +1444,10 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX2-LABEL: test_v128i8:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: pushl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX2-NEXT: .cfi_offset %ebp, -8
; X86-AVX2-NEXT: movl %esp, %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX2-NEXT: andl $-32, %esp
; X86-AVX2-NEXT: subl $32, %esp
; X86-AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
@@ -1362,6 +1457,7 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX2-NEXT: sete %al
; X86-AVX2-NEXT: movl %ebp, %esp
; X86-AVX2-NEXT: popl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1392,15 +1488,24 @@ define i1 @test_v128i8(<128 x i8> %a0) nounwind {
; Compare Truncated/Masked OR Reductions
;
-define i1 @trunc_v2i64(<2 x i64> %a0) nounwind {
-; SSE2-LABEL: trunc_v2i64:
-; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE2-NEXT: por %xmm0, %xmm1
-; SSE2-NEXT: movd %xmm1, %eax
-; SSE2-NEXT: testw %ax, %ax
-; SSE2-NEXT: sete %al
-; SSE2-NEXT: ret{{[l|q]}}
+define i1 @trunc_v2i64(<2 x i64> %a0) {
+; X86-SSE2-LABEL: trunc_v2i64:
+; X86-SSE2: # %bb.0:
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE2-NEXT: por %xmm0, %xmm1
+; X86-SSE2-NEXT: movd %xmm1, %eax
+; X86-SSE2-NEXT: testw %ax, %ax
+; X86-SSE2-NEXT: sete %al
+; X86-SSE2-NEXT: retl
+;
+; X64-SSE2-LABEL: trunc_v2i64:
+; X64-SSE2: # %bb.0:
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-SSE2-NEXT: por %xmm0, %xmm1
+; X64-SSE2-NEXT: movq %xmm1, %rax
+; X64-SSE2-NEXT: testw %ax, %ax
+; X64-SSE2-NEXT: sete %al
+; X64-SSE2-NEXT: retq
;
; X86-SSE4-LABEL: trunc_v2i64:
; X86-SSE4: # %bb.0:
@@ -1462,7 +1567,7 @@ define i1 @trunc_v2i64(<2 x i64> %a0) nounwind {
ret i1 %3
}
-define i1 @mask_v8i32(<8 x i32> %a0) nounwind {
+define i1 @mask_v8i32(<8 x i32> %a0) {
; SSE2-LABEL: mask_v8i32:
; SSE2: # %bb.0:
; SSE2-NEXT: orps %xmm1, %xmm0
@@ -1497,7 +1602,7 @@ define i1 @mask_v8i32(<8 x i32> %a0) nounwind {
ret i1 %3
}
-define i1 @mask_v8i32_2(<8 x i32> %a0) nounwind {
+define i1 @mask_v8i32_2(<8 x i32> %a0) {
; SSE2-LABEL: mask_v8i32_2:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
@@ -1565,7 +1670,7 @@ define i1 @mask_v8i32_2(<8 x i32> %a0) nounwind {
}
-define i1 @signtest_v8i32(<8 x i32> %a0) nounwind {
+define i1 @signtest_v8i32(<8 x i32> %a0) {
; SSE2-LABEL: signtest_v8i32:
; SSE2: # %bb.0:
; SSE2-NEXT: orps %xmm1, %xmm0
@@ -1599,7 +1704,7 @@ define i1 @signtest_v8i32(<8 x i32> %a0) nounwind {
ret i1 %2
}
-define i1 @signtest_v4i64(<4 x i64> %a0) nounwind {
+define i1 @signtest_v4i64(<4 x i64> %a0) {
; X86-SSE2-LABEL: signtest_v4i64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: por %xmm1, %xmm0
@@ -1646,7 +1751,7 @@ define i1 @signtest_v4i64(<4 x i64> %a0) nounwind {
ret i1 %2
}
-define i1 @trunc_v16i16(<16 x i16> %a0) nounwind {
+define i1 @trunc_v16i16(<16 x i16> %a0) {
; X86-SSE2-LABEL: trunc_v16i16:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: por %xmm1, %xmm0
@@ -1723,11 +1828,14 @@ define i1 @trunc_v16i16(<16 x i16> %a0) nounwind {
ret i1 %3
}
-define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
+define i1 @mask_v128i8(<128 x i8> %a0) {
; X86-SSE2-LABEL: mask_v128i8:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
@@ -1744,6 +1852,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: mask_v128i8:
@@ -1764,7 +1873,10 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE4-LABEL: mask_v128i8:
; X86-SSE4: # %bb.0:
; X86-SSE4-NEXT: pushl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE4-NEXT: .cfi_offset %ebp, -8
; X86-SSE4-NEXT: movl %esp, %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
@@ -1779,6 +1891,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE4-NEXT: sete %al
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
+; X86-SSE4-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE4-NEXT: retl
;
; X64-SSE4-LABEL: mask_v128i8:
@@ -1797,7 +1910,10 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX1-LABEL: mask_v128i8:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: pushl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX1-NEXT: .cfi_offset %ebp, -8
; X86-AVX1-NEXT: movl %esp, %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX1-NEXT: andl $-32, %esp
; X86-AVX1-NEXT: subl $32, %esp
; X86-AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
@@ -1807,6 +1923,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX1-NEXT: sete %al
; X86-AVX1-NEXT: movl %ebp, %esp
; X86-AVX1-NEXT: popl %ebp
+; X86-AVX1-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl
;
@@ -1823,7 +1940,10 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX2-LABEL: mask_v128i8:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: pushl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_offset 8
+; X86-AVX2-NEXT: .cfi_offset %ebp, -8
; X86-AVX2-NEXT: movl %esp, %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X86-AVX2-NEXT: andl $-32, %esp
; X86-AVX2-NEXT: subl $32, %esp
; X86-AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
@@ -1834,6 +1954,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
; X86-AVX2-NEXT: sete %al
; X86-AVX2-NEXT: movl %ebp, %esp
; X86-AVX2-NEXT: popl %ebp
+; X86-AVX2-NEXT: .cfi_def_cfa %esp, 4
; X86-AVX2-NEXT: vzeroupper
; X86-AVX2-NEXT: retl
;
@@ -1863,7 +1984,7 @@ define i1 @mask_v128i8(<128 x i8> %a0) nounwind {
}
%struct.Box = type { i32, i32, i32, i32 }
-define zeroext i1 @PR44781(ptr %0) nounwind {
+define zeroext i1 @PR44781(ptr %0) {
; X86-SSE2-LABEL: PR44781:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or.ll b/llvm/test/CodeGen/X86/vector-reduce-or.ll
index fed059d7a3974..a5559523ea32e 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or.ll
@@ -260,7 +260,7 @@ define i64 @test_v8i64(<8 x i64> %a0) nounwind {
; AVX512-LABEL: test_v8i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -280,17 +280,17 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE2-NEXT: por 56(%ebp), %xmm2
-; X86-SSE2-NEXT: por 24(%ebp), %xmm0
-; X86-SSE2-NEXT: por %xmm2, %xmm0
; X86-SSE2-NEXT: por 72(%ebp), %xmm3
; X86-SSE2-NEXT: por 40(%ebp), %xmm1
; X86-SSE2-NEXT: por %xmm3, %xmm1
-; X86-SSE2-NEXT: por %xmm0, %xmm1
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE2-NEXT: por 56(%ebp), %xmm2
+; X86-SSE2-NEXT: por 24(%ebp), %xmm0
+; X86-SSE2-NEXT: por %xmm2, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0
-; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE2-NEXT: por %xmm0, %xmm1
+; X86-SSE2-NEXT: movd %xmm1, %eax
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE2-NEXT: movd %xmm0, %edx
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
@@ -298,16 +298,16 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
;
; X64-SSE-LABEL: test_v16i64:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: por %xmm6, %xmm2
-; X64-SSE-NEXT: por %xmm4, %xmm0
-; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm7, %xmm3
; X64-SSE-NEXT: por %xmm5, %xmm1
; X64-SSE-NEXT: por %xmm3, %xmm1
-; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: por %xmm6, %xmm2
+; X64-SSE-NEXT: por %xmm4, %xmm0
+; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm1, %xmm0
-; X64-SSE-NEXT: movq %xmm0, %rax
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-SSE-NEXT: por %xmm0, %xmm1
+; X64-SSE-NEXT: movq %xmm1, %rax
; X64-SSE-NEXT: retq
;
; X86-SSE4-LABEL: test_v16i64:
@@ -317,17 +317,17 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE4-NEXT: por 56(%ebp), %xmm2
-; X86-SSE4-NEXT: por 24(%ebp), %xmm0
-; X86-SSE4-NEXT: por %xmm2, %xmm0
; X86-SSE4-NEXT: por 72(%ebp), %xmm3
; X86-SSE4-NEXT: por 40(%ebp), %xmm1
; X86-SSE4-NEXT: por %xmm3, %xmm1
-; X86-SSE4-NEXT: por %xmm0, %xmm1
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE4-NEXT: por 56(%ebp), %xmm2
+; X86-SSE4-NEXT: por 24(%ebp), %xmm0
+; X86-SSE4-NEXT: por %xmm2, %xmm0
; X86-SSE4-NEXT: por %xmm1, %xmm0
-; X86-SSE4-NEXT: movd %xmm0, %eax
-; X86-SSE4-NEXT: pextrd $1, %xmm0, %edx
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE4-NEXT: por %xmm0, %xmm1
+; X86-SSE4-NEXT: movd %xmm1, %eax
+; X86-SSE4-NEXT: pextrd $1, %xmm1, %edx
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
; X86-SSE4-NEXT: retl
@@ -402,7 +402,7 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -568,7 +568,7 @@ define i32 @test_v16i32(<16 x i32> %a0) nounwind {
; AVX512-LABEL: test_v16i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpord %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -590,36 +590,36 @@ define i32 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: por 56(%ebp), %xmm2
-; X86-SSE-NEXT: por 24(%ebp), %xmm0
-; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: por 72(%ebp), %xmm3
; X86-SSE-NEXT: por 40(%ebp), %xmm1
; X86-SSE-NEXT: por %xmm3, %xmm1
-; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: por 56(%ebp), %xmm2
+; X86-SSE-NEXT: por 24(%ebp), %xmm0
+; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: movd %xmm1, %eax
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X86-SSE-NEXT: por %xmm1, %xmm0
+; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: test_v32i32:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: por %xmm6, %xmm2
-; X64-SSE-NEXT: por %xmm4, %xmm0
-; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm7, %xmm3
; X64-SSE-NEXT: por %xmm5, %xmm1
; X64-SSE-NEXT: por %xmm3, %xmm1
-; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: por %xmm6, %xmm2
+; X64-SSE-NEXT: por %xmm4, %xmm0
+; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: movd %xmm1, %eax
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X64-SSE-NEXT: por %xmm1, %xmm0
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: retq
;
; X86-AVX1-LABEL: test_v32i32:
@@ -698,7 +698,7 @@ define i32 @test_v32i32(<32 x i32> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpord %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpord %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -811,9 +811,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
@@ -826,9 +826,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
@@ -841,9 +841,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -899,9 +899,9 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX1-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
@@ -915,9 +915,9 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
@@ -928,13 +928,13 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX512-LABEL: test_v32i16:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -953,21 +953,21 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: por 56(%ebp), %xmm2
-; X86-SSE-NEXT: por 24(%ebp), %xmm0
-; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: por 72(%ebp), %xmm3
; X86-SSE-NEXT: por 40(%ebp), %xmm1
; X86-SSE-NEXT: por %xmm3, %xmm1
-; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: por 56(%ebp), %xmm2
+; X86-SSE-NEXT: por 24(%ebp), %xmm0
+; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: movdqa %xmm1, %xmm0
-; X86-SSE-NEXT: psrld $16, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE-NEXT: por %xmm1, %xmm0
-; X86-SSE-NEXT: movd %xmm0, %eax
+; X86-SSE-NEXT: movdqa %xmm0, %xmm1
+; X86-SSE-NEXT: psrld $16, %xmm1
+; X86-SSE-NEXT: por %xmm0, %xmm1
+; X86-SSE-NEXT: movd %xmm1, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
@@ -975,21 +975,21 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
;
; X64-SSE-LABEL: test_v64i16:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: por %xmm6, %xmm2
-; X64-SSE-NEXT: por %xmm4, %xmm0
-; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm7, %xmm3
; X64-SSE-NEXT: por %xmm5, %xmm1
; X64-SSE-NEXT: por %xmm3, %xmm1
-; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: por %xmm6, %xmm2
+; X64-SSE-NEXT: por %xmm4, %xmm0
+; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: movdqa %xmm1, %xmm0
-; X64-SSE-NEXT: psrld $16, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X64-SSE-NEXT: por %xmm1, %xmm0
-; X64-SSE-NEXT: movd %xmm0, %eax
+; X64-SSE-NEXT: movdqa %xmm0, %xmm1
+; X64-SSE-NEXT: psrld $16, %xmm1
+; X64-SSE-NEXT: por %xmm0, %xmm1
+; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X64-SSE-NEXT: retq
;
@@ -1005,9 +1005,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX1-NEXT: vorps %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX1-NEXT: vorps %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; X86-AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
@@ -1025,9 +1025,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX1-NEXT: vorps %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX1-NEXT: vorps %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; X64-AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
@@ -1047,9 +1047,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; X86-AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
@@ -1067,9 +1067,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; X64-AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
@@ -1081,13 +1081,13 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -1369,7 +1369,7 @@ define i8 @test_v64i8(<64 x i8> %a0) nounwind {
; AVX512-LABEL: test_v64i8:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -1396,24 +1396,24 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: por 56(%ebp), %xmm2
-; X86-SSE-NEXT: por 24(%ebp), %xmm0
-; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: por 72(%ebp), %xmm3
; X86-SSE-NEXT: por 40(%ebp), %xmm1
; X86-SSE-NEXT: por %xmm3, %xmm1
-; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: por 56(%ebp), %xmm2
+; X86-SSE-NEXT: por 24(%ebp), %xmm0
+; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: movdqa %xmm1, %xmm0
-; X86-SSE-NEXT: psrld $16, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE-NEXT: por %xmm1, %xmm0
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
-; X86-SSE-NEXT: psrlw $8, %xmm1
+; X86-SSE-NEXT: psrld $16, %xmm1
; X86-SSE-NEXT: por %xmm0, %xmm1
-; X86-SSE-NEXT: movd %xmm1, %eax
+; X86-SSE-NEXT: movdqa %xmm1, %xmm0
+; X86-SSE-NEXT: psrlw $8, %xmm0
+; X86-SSE-NEXT: por %xmm1, %xmm0
+; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: # kill: def $al killed $al killed $eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
@@ -1421,24 +1421,24 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
;
; X64-SSE-LABEL: test_v128i8:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: por %xmm6, %xmm2
-; X64-SSE-NEXT: por %xmm4, %xmm0
-; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm7, %xmm3
; X64-SSE-NEXT: por %xmm5, %xmm1
; X64-SSE-NEXT: por %xmm3, %xmm1
-; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: por %xmm6, %xmm2
+; X64-SSE-NEXT: por %xmm4, %xmm0
+; X64-SSE-NEXT: por %xmm2, %xmm0
; X64-SSE-NEXT: por %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: movdqa %xmm1, %xmm0
-; X64-SSE-NEXT: psrld $16, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X64-SSE-NEXT: por %xmm1, %xmm0
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
-; X64-SSE-NEXT: psrlw $8, %xmm1
+; X64-SSE-NEXT: psrld $16, %xmm1
; X64-SSE-NEXT: por %xmm0, %xmm1
-; X64-SSE-NEXT: movd %xmm1, %eax
+; X64-SSE-NEXT: movdqa %xmm1, %xmm0
+; X64-SSE-NEXT: psrlw $8, %xmm0
+; X64-SSE-NEXT: por %xmm1, %xmm0
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: # kill: def $al killed $al killed $eax
; X64-SSE-NEXT: retq
;
@@ -1538,7 +1538,7 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
diff --git a/llvm/test/CodeGen/X86/vector-reduce-xor.ll b/llvm/test/CodeGen/X86/vector-reduce-xor.ll
index 09e6318653538..b8009e5b3daed 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-xor.ll
@@ -260,7 +260,7 @@ define i64 @test_v8i64(<8 x i64> %a0) nounwind {
; AVX512-LABEL: test_v8i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -280,17 +280,17 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE2-NEXT: pxor 56(%ebp), %xmm2
-; X86-SSE2-NEXT: pxor 24(%ebp), %xmm0
-; X86-SSE2-NEXT: pxor %xmm2, %xmm0
; X86-SSE2-NEXT: pxor 72(%ebp), %xmm3
; X86-SSE2-NEXT: pxor 40(%ebp), %xmm1
; X86-SSE2-NEXT: pxor %xmm3, %xmm1
-; X86-SSE2-NEXT: pxor %xmm0, %xmm1
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE2-NEXT: pxor 56(%ebp), %xmm2
+; X86-SSE2-NEXT: pxor 24(%ebp), %xmm0
+; X86-SSE2-NEXT: pxor %xmm2, %xmm0
; X86-SSE2-NEXT: pxor %xmm1, %xmm0
-; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE2-NEXT: pxor %xmm0, %xmm1
+; X86-SSE2-NEXT: movd %xmm1, %eax
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE2-NEXT: movd %xmm0, %edx
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
@@ -298,16 +298,16 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
;
; X64-SSE-LABEL: test_v16i64:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pxor %xmm6, %xmm2
-; X64-SSE-NEXT: pxor %xmm4, %xmm0
-; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm7, %xmm3
; X64-SSE-NEXT: pxor %xmm5, %xmm1
; X64-SSE-NEXT: pxor %xmm3, %xmm1
-; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pxor %xmm6, %xmm2
+; X64-SSE-NEXT: pxor %xmm4, %xmm0
+; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm0
-; X64-SSE-NEXT: movq %xmm0, %rax
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-SSE-NEXT: pxor %xmm0, %xmm1
+; X64-SSE-NEXT: movq %xmm1, %rax
; X64-SSE-NEXT: retq
;
; X86-SSE4-LABEL: test_v16i64:
@@ -317,17 +317,17 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; X86-SSE4-NEXT: andl $-16, %esp
; X86-SSE4-NEXT: subl $16, %esp
; X86-SSE4-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE4-NEXT: pxor 56(%ebp), %xmm2
-; X86-SSE4-NEXT: pxor 24(%ebp), %xmm0
-; X86-SSE4-NEXT: pxor %xmm2, %xmm0
; X86-SSE4-NEXT: pxor 72(%ebp), %xmm3
; X86-SSE4-NEXT: pxor 40(%ebp), %xmm1
; X86-SSE4-NEXT: pxor %xmm3, %xmm1
-; X86-SSE4-NEXT: pxor %xmm0, %xmm1
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE4-NEXT: pxor 56(%ebp), %xmm2
+; X86-SSE4-NEXT: pxor 24(%ebp), %xmm0
+; X86-SSE4-NEXT: pxor %xmm2, %xmm0
; X86-SSE4-NEXT: pxor %xmm1, %xmm0
-; X86-SSE4-NEXT: movd %xmm0, %eax
-; X86-SSE4-NEXT: pextrd $1, %xmm0, %edx
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE4-NEXT: pxor %xmm0, %xmm1
+; X86-SSE4-NEXT: movd %xmm1, %eax
+; X86-SSE4-NEXT: pextrd $1, %xmm1, %edx
; X86-SSE4-NEXT: movl %ebp, %esp
; X86-SSE4-NEXT: popl %ebp
; X86-SSE4-NEXT: retl
@@ -402,7 +402,7 @@ define i64 @test_v16i64(<16 x i64> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -568,7 +568,7 @@ define i32 @test_v16i32(<16 x i32> %a0) nounwind {
; AVX512-LABEL: test_v16i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -590,36 +590,36 @@ define i32 @test_v32i32(<32 x i32> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: pxor 56(%ebp), %xmm2
-; X86-SSE-NEXT: pxor 24(%ebp), %xmm0
-; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: pxor 72(%ebp), %xmm3
; X86-SSE-NEXT: pxor 40(%ebp), %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm1
-; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: pxor 56(%ebp), %xmm2
+; X86-SSE-NEXT: pxor 24(%ebp), %xmm0
+; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: movd %xmm1, %eax
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X86-SSE-NEXT: pxor %xmm1, %xmm0
+; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
; X86-SSE-NEXT: retl
;
; X64-SSE-LABEL: test_v32i32:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pxor %xmm6, %xmm2
-; X64-SSE-NEXT: pxor %xmm4, %xmm0
-; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm7, %xmm3
; X64-SSE-NEXT: pxor %xmm5, %xmm1
; X64-SSE-NEXT: pxor %xmm3, %xmm1
-; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pxor %xmm6, %xmm2
+; X64-SSE-NEXT: pxor %xmm4, %xmm0
+; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: movd %xmm1, %eax
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X64-SSE-NEXT: pxor %xmm1, %xmm0
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: retq
;
; X86-AVX1-LABEL: test_v32i32:
@@ -698,7 +698,7 @@ define i32 @test_v32i32(<32 x i32> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -811,9 +811,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
@@ -826,9 +826,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
@@ -841,9 +841,9 @@ define i16 @test_v16i16(<16 x i16> %a0) nounwind {
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -899,9 +899,9 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1-NEXT: vxorps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX1-NEXT: vxorps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
@@ -915,9 +915,9 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovd %xmm0, %eax
@@ -928,13 +928,13 @@ define i16 @test_v32i16(<32 x i16> %a0) nounwind {
; AVX512-LABEL: test_v32i16:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -953,21 +953,21 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: pxor 56(%ebp), %xmm2
-; X86-SSE-NEXT: pxor 24(%ebp), %xmm0
-; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: pxor 72(%ebp), %xmm3
; X86-SSE-NEXT: pxor 40(%ebp), %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm1
-; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: pxor 56(%ebp), %xmm2
+; X86-SSE-NEXT: pxor 24(%ebp), %xmm0
+; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: movdqa %xmm1, %xmm0
-; X86-SSE-NEXT: psrld $16, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE-NEXT: pxor %xmm1, %xmm0
-; X86-SSE-NEXT: movd %xmm0, %eax
+; X86-SSE-NEXT: movdqa %xmm0, %xmm1
+; X86-SSE-NEXT: psrld $16, %xmm1
+; X86-SSE-NEXT: pxor %xmm0, %xmm1
+; X86-SSE-NEXT: movd %xmm1, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
@@ -975,21 +975,21 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
;
; X64-SSE-LABEL: test_v64i16:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pxor %xmm6, %xmm2
-; X64-SSE-NEXT: pxor %xmm4, %xmm0
-; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm7, %xmm3
; X64-SSE-NEXT: pxor %xmm5, %xmm1
; X64-SSE-NEXT: pxor %xmm3, %xmm1
-; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pxor %xmm6, %xmm2
+; X64-SSE-NEXT: pxor %xmm4, %xmm0
+; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: movdqa %xmm1, %xmm0
-; X64-SSE-NEXT: psrld $16, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X64-SSE-NEXT: pxor %xmm1, %xmm0
-; X64-SSE-NEXT: movd %xmm0, %eax
+; X64-SSE-NEXT: movdqa %xmm0, %xmm1
+; X64-SSE-NEXT: psrld $16, %xmm1
+; X64-SSE-NEXT: pxor %xmm0, %xmm1
+; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X64-SSE-NEXT: retq
;
@@ -1005,9 +1005,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX1-NEXT: vxorps %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX1-NEXT: vxorps %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; X86-AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; X86-AVX1-NEXT: vmovd %xmm0, %eax
@@ -1025,9 +1025,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX1-NEXT: vxorps %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX1-NEXT: vxorps %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrld $16, %xmm0, %xmm1
; X64-AVX1-NEXT: vpxor %xmm0, %xmm1, %xmm0
; X64-AVX1-NEXT: vmovd %xmm0, %eax
@@ -1047,9 +1047,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; X86-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax
@@ -1067,9 +1067,9 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpsrld $16, %xmm0, %xmm1
; X64-AVX2-NEXT: vpxor %xmm0, %xmm1, %xmm0
; X64-AVX2-NEXT: vmovd %xmm0, %eax
@@ -1081,13 +1081,13 @@ define i16 @test_v64i16(<64 x i16> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX512-NEXT: vpxor %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmovd %xmm0, %eax
@@ -1369,7 +1369,7 @@ define i8 @test_v64i8(<64 x i8> %a0) nounwind {
; AVX512-LABEL: test_v64i8:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -1396,24 +1396,24 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; X86-SSE-NEXT: andl $-16, %esp
; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: movdqa 8(%ebp), %xmm3
-; X86-SSE-NEXT: pxor 56(%ebp), %xmm2
-; X86-SSE-NEXT: pxor 24(%ebp), %xmm0
-; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: pxor 72(%ebp), %xmm3
; X86-SSE-NEXT: pxor 40(%ebp), %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm1
-; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X86-SSE-NEXT: pxor 56(%ebp), %xmm2
+; X86-SSE-NEXT: pxor 24(%ebp), %xmm0
+; X86-SSE-NEXT: pxor %xmm2, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm0
-; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: movdqa %xmm1, %xmm0
-; X86-SSE-NEXT: psrld $16, %xmm0
+; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X86-SSE-NEXT: pxor %xmm1, %xmm0
; X86-SSE-NEXT: movdqa %xmm0, %xmm1
-; X86-SSE-NEXT: psrlw $8, %xmm1
+; X86-SSE-NEXT: psrld $16, %xmm1
; X86-SSE-NEXT: pxor %xmm0, %xmm1
-; X86-SSE-NEXT: movd %xmm1, %eax
+; X86-SSE-NEXT: movdqa %xmm1, %xmm0
+; X86-SSE-NEXT: psrlw $8, %xmm0
+; X86-SSE-NEXT: pxor %xmm1, %xmm0
+; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: # kill: def $al killed $al killed $eax
; X86-SSE-NEXT: movl %ebp, %esp
; X86-SSE-NEXT: popl %ebp
@@ -1421,24 +1421,24 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
;
; X64-SSE-LABEL: test_v128i8:
; X64-SSE: # %bb.0:
-; X64-SSE-NEXT: pxor %xmm6, %xmm2
-; X64-SSE-NEXT: pxor %xmm4, %xmm0
-; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm7, %xmm3
; X64-SSE-NEXT: pxor %xmm5, %xmm1
; X64-SSE-NEXT: pxor %xmm3, %xmm1
-; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; X64-SSE-NEXT: pxor %xmm6, %xmm2
+; X64-SSE-NEXT: pxor %xmm4, %xmm0
+; X64-SSE-NEXT: pxor %xmm2, %xmm0
; X64-SSE-NEXT: pxor %xmm1, %xmm0
-; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: movdqa %xmm1, %xmm0
-; X64-SSE-NEXT: psrld $16, %xmm0
+; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
; X64-SSE-NEXT: pxor %xmm1, %xmm0
; X64-SSE-NEXT: movdqa %xmm0, %xmm1
-; X64-SSE-NEXT: psrlw $8, %xmm1
+; X64-SSE-NEXT: psrld $16, %xmm1
; X64-SSE-NEXT: pxor %xmm0, %xmm1
-; X64-SSE-NEXT: movd %xmm1, %eax
+; X64-SSE-NEXT: movdqa %xmm1, %xmm0
+; X64-SSE-NEXT: psrlw $8, %xmm0
+; X64-SSE-NEXT: pxor %xmm1, %xmm0
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: # kill: def $al killed $al killed $eax
; X64-SSE-NEXT: retq
;
@@ -1538,7 +1538,7 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; AVX512: # %bb.0:
; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
index 4edde669561b7..62e76c043f978 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
@@ -86,16 +86,8 @@ for.end:
define signext i8 @or_v16i8(ptr %p) {
; CHECK-LABEL: @or_v16i8(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[P:%.*]], align 1, !tbaa [[TBAA6:![0-9]+]]
-; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[BIN_RDX:%.*]] = or <16 x i8> [[TMP1]], [[RDX_SHUF]]
-; CHECK-NEXT: [[RDX_SHUF4:%.*]] = shufflevector <16 x i8> [[BIN_RDX]], <16 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[BIN_RDX5:%.*]] = or <16 x i8> [[BIN_RDX]], [[RDX_SHUF4]]
-; CHECK-NEXT: [[RDX_SHUF6:%.*]] = shufflevector <16 x i8> [[BIN_RDX5]], <16 x i8> poison, <16 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[BIN_RDX7:%.*]] = or <16 x i8> [[BIN_RDX5]], [[RDX_SHUF6]]
-; CHECK-NEXT: [[RDX_SHUF8:%.*]] = shufflevector <16 x i8> [[BIN_RDX7]], <16 x i8> poison, <16 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[BIN_RDX9:%.*]] = or <16 x i8> [[BIN_RDX7]], [[RDX_SHUF8]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i8> [[BIN_RDX9]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[P:%.*]], align 1, !tbaa [[TBAA6:![0-9]+]]
+; CHECK-NEXT: [[TMP2:%.*]] = tail call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])
; CHECK-NEXT: ret i8 [[TMP2]]
;
entry:
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