[llvm] [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (PR #199544)

[Simon Pilgrim via llvm-commits]

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RKSimon wrote:

For the moment - matchScalarReduction is on my list to remove entirely, but we're not there yet - there's a number of places in the DAG that still generate these patterns (splitting on large integers i256 etc. for instance).

https://github.com/llvm/llvm-project/pull/199544