[llvm] [PEI] Materialize registers before calling insertZeroCallUsedRegs (PR #214147)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Lucas Chollet (LucasChollet)

<details>
<summary>Changes</summary>

As insertZeroCallUsedRegs only supports physical registers, force the materialization of any virtual registers by calling scavengeFrameVirtualRegs.

Virtual registers can be added during the pass by
emit{Prologue,Epilogue}. For example, RISC-V uses a virtual register to store the size of a large alloca.

---
Full diff: https://github.com/llvm/llvm-project/pull/214147.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/PrologEpilogInserter.cpp (+5) 
- (modified) llvm/test/CodeGen/RISCV/zero-call-used-regs.ll (+17) 


``````````diff
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 4cfce20465e21..20ccaedd1f5c8 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1166,6 +1166,7 @@ void PEIImpl::calculateFrameObjectOffsets(MachineFunction &MF) {
 /// prolog and epilog code to the function.
 void PEIImpl::insertPrologEpilogCode(MachineFunction &MF) {
   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
+  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
 
   // Add prologue to the function...
   for (MachineBasicBlock *SaveBlock : SaveBlocks)
@@ -1175,6 +1176,10 @@ void PEIImpl::insertPrologEpilogCode(MachineFunction &MF) {
   for (MachineBasicBlock *RestoreBlock : RestoreBlocks)
     TFI.emitEpilogue(MF, *RestoreBlock);
 
+  // Force the materialization of any virtual registers as insertZeroCallRegs
+  // only handles physical registers.
+  if (TRI.requiresRegisterScavenging(MF) && FrameIndexVirtualScavenging)
+    scavengeFrameVirtualRegs(MF, *RS);
   // Zero call used registers before restoring callee-saved registers.
   insertZeroCallUsedRegs(MF);
 
diff --git a/llvm/test/CodeGen/RISCV/zero-call-used-regs.ll b/llvm/test/CodeGen/RISCV/zero-call-used-regs.ll
index 46b0cba76194b..78198b4876cd5 100644
--- a/llvm/test/CodeGen/RISCV/zero-call-used-regs.ll
+++ b/llvm/test/CodeGen/RISCV/zero-call-used-regs.ll
@@ -335,5 +335,22 @@ entry:
   ret double %mul2
 }
 
+define void @huge_stack() #0 "zero-call-used-regs"="used-gpr" {
+; CHECK-LABEL: huge_stack:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 10
+; CHECK-NEXT:    addi a0, a0, -944
+; CHECK-NEXT:    sub sp, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa_offset 40016
+; CHECK-NEXT:    lui a0, 10
+; CHECK-NEXT:    addi a0, a0, -944
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %1 = alloca [10000 x i32], align 4
+  ret void
+}
+
 attributes #0 = { "target-cpu"="generic" "target-features"="+m,+f,+d" }
 attributes #1 = { "target-cpu"="generic" "target-features"="+m,+zdinx" }

``````````

</details>


https://github.com/llvm/llvm-project/pull/214147