[llvm] dbacea2 - [AMDGPU] Reject non-fp16 image sample data in D16 detection while lowering image (#213272)

[via llvm-commits]

Author: Arseniy Obolenskiy
Date: 2026-08-05T05:10:46+02:00
New Revision: dbacea2912ae76f162ed622212a2804f2b32bd00

URL: https://github.com/llvm/llvm-project/commit/dbacea2912ae76f162ed622212a2804f2b32bd00
DIFF: https://github.com/llvm/llvm-project/commit/dbacea2912ae76f162ed622212a2804f2b32bd00.diff

LOG: [AMDGPU] Reject non-fp16 image sample data in D16 detection while lowering image (#213272)

Added: 
    llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.illegal-data-type.err.ll

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e55356ab3ea24..9159e425dfffd 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10464,7 +10464,13 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
       VData = Op.getOperand(2);
 
       MVT StoreVT = VData.getSimpleValueType();
-      if (StoreVT.getScalarType() == MVT::f16) {
+      MVT StoreScalarVT = StoreVT.getScalarType();
+      if (StoreScalarVT != MVT::f16 && StoreScalarVT.getSizeInBits() != 32 &&
+          StoreScalarVT.getSizeInBits() != 64) {
+        return diagnoseUnsupportedImage(DAG, Op, OrigResultTypes, DL,
+                                        "unsupported image store data type");
+      }
+      if (StoreScalarVT == MVT::f16) {
         if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
           return Op; // D16 is unsupported for this instruction
 
@@ -10477,7 +10483,13 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
       // Work out the num dwords based on the dmask popcount and underlying type
       // and whether packing is supported.
       MVT LoadVT = ResultTypes[0].getSimpleVT();
-      if (LoadVT.getScalarType() == MVT::f16) {
+      MVT LoadScalarVT = LoadVT.getScalarType();
+      if (LoadScalarVT != MVT::f16 && LoadScalarVT.getSizeInBits() != 32 &&
+          LoadScalarVT.getSizeInBits() != 64) {
+        return diagnoseUnsupportedImage(DAG, Op, OrigResultTypes, DL,
+                                        "unsupported image load data type");
+      }
+      if (LoadScalarVT == MVT::f16) {
         if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
           return Op; // D16 is unsupported for this instruction
 

diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.illegal-data-type.err.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.illegal-data-type.err.ll
new file mode 100644
index 0000000000000..fbc455d52c0d4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.illegal-data-type.err.ll
@@ -0,0 +1,28 @@
+; RUN: not llc -mtriple=amdgpu9.0a -filetype=null %s 2>&1 | FileCheck %s
+
+; llvm.amdgcn.image.{sample,load,store} support 32-bit and 64-bit
+; data, plus f16 under the D16 hardware conversion. Other 16-bit
+; scalar types (bf16, i16) are not valid D16 data and must be
+; rejected instead of silently mis-lowered or crashing.
+
+; CHECK: error: {{.*}}unsupported image load data type
+define amdgpu_ps <4 x bfloat> @sample_2d_v4bf16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
+  %v = call <4 x bfloat> @llvm.amdgcn.image.sample.2d.v4bf16.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+  ret <4 x bfloat> %v
+}
+
+; CHECK: error: {{.*}}unsupported image load data type
+define amdgpu_ps <4 x i16> @load_2d_v4i16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
+  %v = call <4 x i16> @llvm.amdgcn.image.load.2d.v4i16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret <4 x i16> %v
+}
+
+; CHECK: error: {{.*}}unsupported image store data type
+define amdgpu_ps void @store_2d_v4bf16(<8 x i32> inreg %rsrc, <4 x bfloat> %data, i32 %s, i32 %t) {
+  call void @llvm.amdgcn.image.store.2d.v4bf16.i32(<4 x bfloat> %data, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
+  ret void
+}
+
+declare <4 x bfloat> @llvm.amdgcn.image.sample.2d.v4bf16.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
+declare <4 x i16> @llvm.amdgcn.image.load.2d.v4i16.i32(i32, i32, i32, <8 x i32>, i32, i32)
+declare void @llvm.amdgcn.image.store.2d.v4bf16.i32(<4 x bfloat>, i32, i32, i32, <8 x i32>, i32, i32)