[llvm] [AArch64] Use only virtual registers in pre-RA test(NFC) (PR #213951)
Tomer Shafir via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 12:06:19 PDT 2026
https://github.com/tomershafir updated https://github.com/llvm/llvm-project/pull/213951
>From bf68759a0568bb46b9b79c5194da5cdcf0fc8192 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Tue, 4 Aug 2026 16:46:15 +0300
Subject: [PATCH 1/2] [AArch64] Use only virtual registers in pre-RA test(NFC)
---
.../misched-fusion-fmin-fmax-pre-ra.mir | 256 +++++++++---------
1 file changed, 128 insertions(+), 128 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir b/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
index a7e5244352209..58747fdb6ef77 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
@@ -15,10 +15,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr16 = FMAXHrr
- %0:fpr16 = FMAXHrr undef $h0, undef $h1, implicit $fpcr
- %1:fpr16 = FADDHrr undef $h3, undef $h4, implicit $fpcr
- %2:fpr16 = FMAXHrr %0, undef $h2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr16 = FMAXHrr
+ %0:fpr16 = FMAXHrr undef %1:fpr16, undef %2:fpr16, implicit $fpcr
+ %3:fpr16 = FADDHrr undef %4:fpr16, undef %5:fpr16, implicit $fpcr
+ %6:fpr16 = FMAXHrr %0, undef %7:fpr16, implicit $fpcr
...
---
name: fmax_fmin_h
@@ -29,10 +29,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr16 = FMINHrr
- %0:fpr16 = FMAXHrr undef $h0, undef $h1, implicit $fpcr
- %1:fpr16 = FADDHrr undef $h3, undef $h4, implicit $fpcr
- %2:fpr16 = FMINHrr %0, undef $h2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr16 = FMINHrr
+ %0:fpr16 = FMAXHrr undef %1:fpr16, undef %2:fpr16, implicit $fpcr
+ %3:fpr16 = FADDHrr undef %4:fpr16, undef %5:fpr16, implicit $fpcr
+ %6:fpr16 = FMINHrr %0, undef %7:fpr16, implicit $fpcr
...
---
name: fmin_fmax_h
@@ -43,10 +43,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr16 = FMAXHrr
- %0:fpr16 = FMINHrr undef $h0, undef $h1, implicit $fpcr
- %1:fpr16 = FADDHrr undef $h3, undef $h4, implicit $fpcr
- %2:fpr16 = FMAXHrr %0, undef $h2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr16 = FMAXHrr
+ %0:fpr16 = FMINHrr undef %1:fpr16, undef %2:fpr16, implicit $fpcr
+ %3:fpr16 = FADDHrr undef %4:fpr16, undef %5:fpr16, implicit $fpcr
+ %6:fpr16 = FMAXHrr %0, undef %7:fpr16, implicit $fpcr
...
---
name: fmin_fmin_h
@@ -57,10 +57,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr16 = FMINHrr
- %0:fpr16 = FMINHrr undef $h0, undef $h1, implicit $fpcr
- %1:fpr16 = FADDHrr undef $h3, undef $h4, implicit $fpcr
- %2:fpr16 = FMINHrr %0, undef $h2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr16 = FMINHrr
+ %0:fpr16 = FMINHrr undef %1:fpr16, undef %2:fpr16, implicit $fpcr
+ %3:fpr16 = FADDHrr undef %4:fpr16, undef %5:fpr16, implicit $fpcr
+ %6:fpr16 = FMINHrr %0, undef %7:fpr16, implicit $fpcr
...
---
name: fmax_fmax_s
@@ -71,10 +71,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr32 = FMAXSrr
- %0:fpr32 = FMAXSrr undef $s0, undef $s1, implicit $fpcr
- %1:fpr32 = FADDSrr undef $s3, undef $s4, implicit $fpcr
- %2:fpr32 = FMAXSrr %0, undef $s2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr32 = FMAXSrr
+ %0:fpr32 = FMAXSrr undef %1:fpr32, undef %2:fpr32, implicit $fpcr
+ %3:fpr32 = FADDSrr undef %4:fpr32, undef %5:fpr32, implicit $fpcr
+ %6:fpr32 = FMAXSrr %0, undef %7:fpr32, implicit $fpcr
...
---
name: fmax_fmin_s
@@ -85,10 +85,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr32 = FMINSrr
- %0:fpr32 = FMAXSrr undef $s0, undef $s1, implicit $fpcr
- %1:fpr32 = FADDSrr undef $s3, undef $s4, implicit $fpcr
- %2:fpr32 = FMINSrr %0, undef $s2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr32 = FMINSrr
+ %0:fpr32 = FMAXSrr undef %1:fpr32, undef %2:fpr32, implicit $fpcr
+ %3:fpr32 = FADDSrr undef %4:fpr32, undef %5:fpr32, implicit $fpcr
+ %6:fpr32 = FMINSrr %0, undef %7:fpr32, implicit $fpcr
...
---
name: fmin_fmax_s
@@ -99,10 +99,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr32 = FMAXSrr
- %0:fpr32 = FMINSrr undef $s0, undef $s1, implicit $fpcr
- %1:fpr32 = FADDSrr undef $s3, undef $s4, implicit $fpcr
- %2:fpr32 = FMAXSrr %0, undef $s2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr32 = FMAXSrr
+ %0:fpr32 = FMINSrr undef %1:fpr32, undef %2:fpr32, implicit $fpcr
+ %3:fpr32 = FADDSrr undef %4:fpr32, undef %5:fpr32, implicit $fpcr
+ %6:fpr32 = FMAXSrr %0, undef %7:fpr32, implicit $fpcr
...
---
name: fmin_fmin_s
@@ -113,10 +113,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr32 = FMINSrr
- %0:fpr32 = FMINSrr undef $s0, undef $s1, implicit $fpcr
- %1:fpr32 = FADDSrr undef $s3, undef $s4, implicit $fpcr
- %2:fpr32 = FMINSrr %0, undef $s2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr32 = FMINSrr
+ %0:fpr32 = FMINSrr undef %1:fpr32, undef %2:fpr32, implicit $fpcr
+ %3:fpr32 = FADDSrr undef %4:fpr32, undef %5:fpr32, implicit $fpcr
+ %6:fpr32 = FMINSrr %0, undef %7:fpr32, implicit $fpcr
...
---
name: fmax_fmax_d
@@ -127,10 +127,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMAXDrr
- %0:fpr64 = FMAXDrr undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDDrr undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMAXDrr %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMAXDrr
+ %0:fpr64 = FMAXDrr undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDDrr undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMAXDrr %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmax_fmin_d
@@ -141,10 +141,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMINDrr
- %0:fpr64 = FMAXDrr undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDDrr undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMINDrr %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMINDrr
+ %0:fpr64 = FMAXDrr undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDDrr undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMINDrr %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmin_fmax_d
@@ -155,10 +155,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMAXDrr
- %0:fpr64 = FMINDrr undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDDrr undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMAXDrr %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMAXDrr
+ %0:fpr64 = FMINDrr undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDDrr undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMAXDrr %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmin_fmin_d
@@ -169,10 +169,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMINDrr
- %0:fpr64 = FMINDrr undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDDrr undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMINDrr %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMINDrr
+ %0:fpr64 = FMINDrr undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDDrr undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMINDrr %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmax_fmax_v4f16
@@ -183,10 +183,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMAXv4f16
- %0:fpr64 = FMAXv4f16 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv4f16 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMAXv4f16 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMAXv4f16
+ %0:fpr64 = FMAXv4f16 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv4f16 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMAXv4f16 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmax_fmin_v4f16
@@ -197,10 +197,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMINv4f16
- %0:fpr64 = FMAXv4f16 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv4f16 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMINv4f16 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMINv4f16
+ %0:fpr64 = FMAXv4f16 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv4f16 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMINv4f16 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmin_fmax_v4f16
@@ -211,10 +211,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMAXv4f16
- %0:fpr64 = FMINv4f16 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv4f16 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMAXv4f16 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMAXv4f16
+ %0:fpr64 = FMINv4f16 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv4f16 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMAXv4f16 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmin_fmin_v4f16
@@ -225,10 +225,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMINv4f16
- %0:fpr64 = FMINv4f16 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv4f16 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMINv4f16 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMINv4f16
+ %0:fpr64 = FMINv4f16 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv4f16 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMINv4f16 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmax_fmax_v8f16
@@ -239,10 +239,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMAXv8f16
- %0:fpr128 = FMAXv8f16 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv8f16 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMAXv8f16 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMAXv8f16
+ %0:fpr128 = FMAXv8f16 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv8f16 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMAXv8f16 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmax_fmin_v8f16
@@ -253,10 +253,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMINv8f16
- %0:fpr128 = FMAXv8f16 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv8f16 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMINv8f16 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMINv8f16
+ %0:fpr128 = FMAXv8f16 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv8f16 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMINv8f16 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmin_fmax_v8f16
@@ -267,10 +267,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMAXv8f16
- %0:fpr128 = FMINv8f16 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv8f16 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMAXv8f16 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMAXv8f16
+ %0:fpr128 = FMINv8f16 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv8f16 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMAXv8f16 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmin_fmin_v8f16
@@ -281,10 +281,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMINv8f16
- %0:fpr128 = FMINv8f16 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv8f16 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMINv8f16 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMINv8f16
+ %0:fpr128 = FMINv8f16 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv8f16 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMINv8f16 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmax_fmax_v2f32
@@ -295,10 +295,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMAXv2f32
- %0:fpr64 = FMAXv2f32 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv2f32 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMAXv2f32 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMAXv2f32
+ %0:fpr64 = FMAXv2f32 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv2f32 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMAXv2f32 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmax_fmin_v2f32
@@ -309,10 +309,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMINv2f32
- %0:fpr64 = FMAXv2f32 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv2f32 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMINv2f32 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMINv2f32
+ %0:fpr64 = FMAXv2f32 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv2f32 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMINv2f32 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmin_fmax_v2f32
@@ -323,10 +323,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMAXv2f32
- %0:fpr64 = FMINv2f32 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv2f32 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMAXv2f32 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMAXv2f32
+ %0:fpr64 = FMINv2f32 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv2f32 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMAXv2f32 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmin_fmin_v2f32
@@ -337,10 +337,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr64 = FMINv2f32
- %0:fpr64 = FMINv2f32 undef $d0, undef $d1, implicit $fpcr
- %1:fpr64 = FADDv2f32 undef $d3, undef $d4, implicit $fpcr
- %2:fpr64 = FMINv2f32 %0, undef $d2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr64 = FMINv2f32
+ %0:fpr64 = FMINv2f32 undef %1:fpr64, undef %2:fpr64, implicit $fpcr
+ %3:fpr64 = FADDv2f32 undef %4:fpr64, undef %5:fpr64, implicit $fpcr
+ %6:fpr64 = FMINv2f32 %0, undef %7:fpr64, implicit $fpcr
...
---
name: fmax_fmax_v4f32
@@ -351,10 +351,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMAXv4f32
- %0:fpr128 = FMAXv4f32 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv4f32 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMAXv4f32 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMAXv4f32
+ %0:fpr128 = FMAXv4f32 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv4f32 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMAXv4f32 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmax_fmin_v4f32
@@ -365,10 +365,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMINv4f32
- %0:fpr128 = FMAXv4f32 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv4f32 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMINv4f32 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMINv4f32
+ %0:fpr128 = FMAXv4f32 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv4f32 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMINv4f32 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmin_fmax_v4f32
@@ -379,10 +379,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMAXv4f32
- %0:fpr128 = FMINv4f32 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv4f32 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMAXv4f32 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMAXv4f32
+ %0:fpr128 = FMINv4f32 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv4f32 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMAXv4f32 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmin_fmin_v4f32
@@ -393,10 +393,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMINv4f32
- %0:fpr128 = FMINv4f32 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv4f32 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMINv4f32 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMINv4f32
+ %0:fpr128 = FMINv4f32 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv4f32 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMINv4f32 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmax_fmax_v2f64
@@ -407,10 +407,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMAXv2f64
- %0:fpr128 = FMAXv2f64 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv2f64 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMAXv2f64 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMAXv2f64
+ %0:fpr128 = FMAXv2f64 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv2f64 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMAXv2f64 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmax_fmin_v2f64
@@ -421,10 +421,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMINv2f64
- %0:fpr128 = FMAXv2f64 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv2f64 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMINv2f64 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMINv2f64
+ %0:fpr128 = FMAXv2f64 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv2f64 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMINv2f64 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmin_fmax_v2f64
@@ -435,10 +435,10 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMAXv2f64
- %0:fpr128 = FMINv2f64 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv2f64 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMAXv2f64 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMAXv2f64
+ %0:fpr128 = FMINv2f64 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv2f64 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMAXv2f64 %0, undef %7:fpr128, implicit $fpcr
...
---
name: fmin_fmin_v2f64
@@ -449,8 +449,8 @@ body: |
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
; NOFUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
- ; CHECK: SU(2): %2:fpr128 = FMINv2f64
- %0:fpr128 = FMINv2f64 undef $q0, undef $q1, implicit $fpcr
- %1:fpr128 = FADDv2f64 undef $q3, undef $q4, implicit $fpcr
- %2:fpr128 = FMINv2f64 %0, undef $q2, implicit $fpcr
+ ; CHECK: SU(2): dead %6:fpr128 = FMINv2f64
+ %0:fpr128 = FMINv2f64 undef %1:fpr128, undef %2:fpr128, implicit $fpcr
+ %3:fpr128 = FADDv2f64 undef %4:fpr128, undef %5:fpr128, implicit $fpcr
+ %6:fpr128 = FMINv2f64 %0, undef %7:fpr128, implicit $fpcr
...
>From b5282818ddc819dc90334831e4aac1d369c85b97 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Tue, 4 Aug 2026 22:06:01 +0300
Subject: [PATCH 2/2] add missing label boundaries checks
---
.../misched-fusion-fmin-fmax-post-ra.mir | 72 +++++++++++++++++--
.../misched-fusion-fmin-fmax-pre-ra.mir | 40 +++++++++--
2 files changed, 104 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir b/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
index 9dd770310abea..1a679cd178bdd 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-post-ra.mir
@@ -1,10 +1,10 @@
# REQUIRES: asserts
-# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -mattr=+fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=FUSE
-# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=FUSE
+# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -mattr=+fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSE
+# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSE
-# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=NOFUSE
-# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -mattr=-fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=NOFUSE
+# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE
+# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -mattr=-fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE
---
name: fmax_fmax_h_waw
@@ -12,6 +12,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmax_fmax_h_waw
; CHECK: SU(0): $h5 = FMAXHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -27,6 +28,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmax_fmax_h_nowaw
; CHECK: SU(0): $h5 = FMAXHrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -42,6 +44,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmax_fmin_h_waw
; CHECK: SU(0): $h5 = FMAXHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -57,6 +60,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmax_fmin_h_nowaw
; CHECK: SU(0): $h5 = FMAXHrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -72,6 +76,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmin_fmax_h_waw
; CHECK: SU(0): $h5 = FMINHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -87,6 +92,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmin_fmax_h_nowaw
; CHECK: SU(0): $h5 = FMINHrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -102,6 +108,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmin_fmin_h_waw
; CHECK: SU(0): $h5 = FMINHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -117,6 +124,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $h0, $h1, $h2, $h3, $h4
+ ; CHECK-LABEL: fmin_fmin_h_nowaw
; CHECK: SU(0): $h5 = FMINHrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -132,6 +140,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmax_fmax_s_waw
; CHECK: SU(0): $s5 = FMAXSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -147,6 +156,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmax_fmax_s_nowaw
; CHECK: SU(0): $s5 = FMAXSrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -162,6 +172,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmax_fmin_s_waw
; CHECK: SU(0): $s5 = FMAXSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -177,6 +188,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmax_fmin_s_nowaw
; CHECK: SU(0): $s5 = FMAXSrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -192,6 +204,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmin_fmax_s_waw
; CHECK: SU(0): $s5 = FMINSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -207,6 +220,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmin_fmax_s_nowaw
; CHECK: SU(0): $s5 = FMINSrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -222,6 +236,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmin_fmin_s_waw
; CHECK: SU(0): $s5 = FMINSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -237,6 +252,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $s0, $s1, $s2, $s3, $s4
+ ; CHECK-LABEL: fmin_fmin_s_nowaw
; CHECK: SU(0): $s5 = FMINSrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -252,6 +268,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmax_d_waw
; CHECK: SU(0): $d5 = FMAXDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -267,6 +284,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmax_d_nowaw
; CHECK: SU(0): $d5 = FMAXDrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -282,6 +300,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmin_d_waw
; CHECK: SU(0): $d5 = FMAXDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -297,6 +316,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmin_d_nowaw
; CHECK: SU(0): $d5 = FMAXDrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -312,6 +332,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmax_d_waw
; CHECK: SU(0): $d5 = FMINDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -327,6 +348,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmax_d_nowaw
; CHECK: SU(0): $d5 = FMINDrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -342,6 +364,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmin_d_waw
; CHECK: SU(0): $d5 = FMINDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -357,6 +380,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmin_d_nowaw
; CHECK: SU(0): $d5 = FMINDrr
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -372,6 +396,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmax_v4f16_waw
; CHECK: SU(0): $d5 = FMAXv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -387,6 +412,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmax_v4f16_nowaw
; CHECK: SU(0): $d5 = FMAXv4f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -402,6 +428,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmin_v4f16_waw
; CHECK: SU(0): $d5 = FMAXv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -417,6 +444,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmin_v4f16_nowaw
; CHECK: SU(0): $d5 = FMAXv4f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -432,6 +460,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmax_v4f16_waw
; CHECK: SU(0): $d5 = FMINv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -447,6 +476,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmax_v4f16_nowaw
; CHECK: SU(0): $d5 = FMINv4f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -462,6 +492,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmin_v4f16_waw
; CHECK: SU(0): $d5 = FMINv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -477,6 +508,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmin_v4f16_nowaw
; CHECK: SU(0): $d5 = FMINv4f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -492,6 +524,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmax_v8f16_waw
; CHECK: SU(0): $q5 = FMAXv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -507,6 +540,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmax_v8f16_nowaw
; CHECK: SU(0): $q5 = FMAXv8f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -522,6 +556,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmin_v8f16_waw
; CHECK: SU(0): $q5 = FMAXv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -537,6 +572,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmin_v8f16_nowaw
; CHECK: SU(0): $q5 = FMAXv8f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -552,6 +588,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmax_v8f16_waw
; CHECK: SU(0): $q5 = FMINv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -567,6 +604,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmax_v8f16_nowaw
; CHECK: SU(0): $q5 = FMINv8f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -582,6 +620,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmin_v8f16_waw
; CHECK: SU(0): $q5 = FMINv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -597,6 +636,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmin_v8f16_nowaw
; CHECK: SU(0): $q5 = FMINv8f16
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -612,6 +652,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmax_v2f32_waw
; CHECK: SU(0): $d5 = FMAXv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -627,6 +668,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmax_v2f32_nowaw
; CHECK: SU(0): $d5 = FMAXv2f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -642,6 +684,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmin_v2f32_waw
; CHECK: SU(0): $d5 = FMAXv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -657,6 +700,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmax_fmin_v2f32_nowaw
; CHECK: SU(0): $d5 = FMAXv2f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -672,6 +716,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmax_v2f32_waw
; CHECK: SU(0): $d5 = FMINv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -687,6 +732,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmax_v2f32_nowaw
; CHECK: SU(0): $d5 = FMINv2f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -702,6 +748,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmin_v2f32_waw
; CHECK: SU(0): $d5 = FMINv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -717,6 +764,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1, $d2, $d3, $d4
+ ; CHECK-LABEL: fmin_fmin_v2f32_nowaw
; CHECK: SU(0): $d5 = FMINv2f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -732,6 +780,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmax_v4f32_waw
; CHECK: SU(0): $q5 = FMAXv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -747,6 +796,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmax_v4f32_nowaw
; CHECK: SU(0): $q5 = FMAXv4f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -762,6 +812,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmin_v4f32_waw
; CHECK: SU(0): $q5 = FMAXv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -777,6 +828,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmin_v4f32_nowaw
; CHECK: SU(0): $q5 = FMAXv4f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -792,6 +844,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmax_v4f32_waw
; CHECK: SU(0): $q5 = FMINv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -807,6 +860,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmax_v4f32_nowaw
; CHECK: SU(0): $q5 = FMINv4f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -822,6 +876,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmin_v4f32_waw
; CHECK: SU(0): $q5 = FMINv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -837,6 +892,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmin_v4f32_nowaw
; CHECK: SU(0): $q5 = FMINv4f32
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -852,6 +908,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmax_v2f64_waw
; CHECK: SU(0): $q5 = FMAXv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -867,6 +924,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmax_v2f64_nowaw
; CHECK: SU(0): $q5 = FMAXv2f64
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -882,6 +940,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmin_v2f64_waw
; CHECK: SU(0): $q5 = FMAXv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -897,6 +956,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmax_fmin_v2f64_nowaw
; CHECK: SU(0): $q5 = FMAXv2f64
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -912,6 +972,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmax_v2f64_waw
; CHECK: SU(0): $q5 = FMINv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -927,6 +988,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmax_v2f64_nowaw
; CHECK: SU(0): $q5 = FMINv2f64
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -942,6 +1004,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmin_v2f64_waw
; CHECK: SU(0): $q5 = FMINv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -957,6 +1020,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3, $q4
+ ; CHECK-LABEL: fmin_fmin_v2f64_nowaw
; CHECK: SU(0): $q5 = FMINv2f64
; CHECK: Successors:
; FUSE-NOT: SU(2): Ord Latency={{[0-9]+}} Cluster
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir b/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
index 58747fdb6ef77..21e7b291f0188 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-fmin-fmax-pre-ra.mir
@@ -1,16 +1,17 @@
# REQUIRES: asserts
-# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -mattr=+fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=FUSE
-# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=FUSE
+# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -mattr=+fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSE
+# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSE
-# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=NOFUSE
-# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -mattr=-fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=NOFUSE
+# RUN: llc -o /dev/null %s -mtriple=aarch64-linux-gnu -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE
+# RUN: llc -o /dev/null %s -mtriple=arm64-apple-macosx -mcpu=apple-m5 -mattr=-fuse-fmin-fmax -passes=machine-scheduler -misched-print-dags -print-before=machine-scheduler 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE
---
name: fmax_fmax_h
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_h
; CHECK: SU(0): %0:fpr16 = FMAXHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -25,6 +26,7 @@ name: fmax_fmin_h
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_h
; CHECK: SU(0): %0:fpr16 = FMAXHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -39,6 +41,7 @@ name: fmin_fmax_h
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_h
; CHECK: SU(0): %0:fpr16 = FMINHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -53,6 +56,7 @@ name: fmin_fmin_h
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_h
; CHECK: SU(0): %0:fpr16 = FMINHrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -67,6 +71,7 @@ name: fmax_fmax_s
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_s
; CHECK: SU(0): %0:fpr32 = FMAXSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -81,6 +86,7 @@ name: fmax_fmin_s
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_s
; CHECK: SU(0): %0:fpr32 = FMAXSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -95,6 +101,7 @@ name: fmin_fmax_s
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_s
; CHECK: SU(0): %0:fpr32 = FMINSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -109,6 +116,7 @@ name: fmin_fmin_s
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_s
; CHECK: SU(0): %0:fpr32 = FMINSrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -123,6 +131,7 @@ name: fmax_fmax_d
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_d
; CHECK: SU(0): %0:fpr64 = FMAXDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -137,6 +146,7 @@ name: fmax_fmin_d
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_d
; CHECK: SU(0): %0:fpr64 = FMAXDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -151,6 +161,7 @@ name: fmin_fmax_d
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_d
; CHECK: SU(0): %0:fpr64 = FMINDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -165,6 +176,7 @@ name: fmin_fmin_d
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_d
; CHECK: SU(0): %0:fpr64 = FMINDrr
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -179,6 +191,7 @@ name: fmax_fmax_v4f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_v4f16
; CHECK: SU(0): %0:fpr64 = FMAXv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -193,6 +206,7 @@ name: fmax_fmin_v4f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_v4f16
; CHECK: SU(0): %0:fpr64 = FMAXv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -207,6 +221,7 @@ name: fmin_fmax_v4f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_v4f16
; CHECK: SU(0): %0:fpr64 = FMINv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -221,6 +236,7 @@ name: fmin_fmin_v4f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_v4f16
; CHECK: SU(0): %0:fpr64 = FMINv4f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -235,6 +251,7 @@ name: fmax_fmax_v8f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_v8f16
; CHECK: SU(0): %0:fpr128 = FMAXv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -249,6 +266,7 @@ name: fmax_fmin_v8f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_v8f16
; CHECK: SU(0): %0:fpr128 = FMAXv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -263,6 +281,7 @@ name: fmin_fmax_v8f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_v8f16
; CHECK: SU(0): %0:fpr128 = FMINv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -277,6 +296,7 @@ name: fmin_fmin_v8f16
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_v8f16
; CHECK: SU(0): %0:fpr128 = FMINv8f16
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -291,6 +311,7 @@ name: fmax_fmax_v2f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_v2f32
; CHECK: SU(0): %0:fpr64 = FMAXv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -305,6 +326,7 @@ name: fmax_fmin_v2f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_v2f32
; CHECK: SU(0): %0:fpr64 = FMAXv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -319,6 +341,7 @@ name: fmin_fmax_v2f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_v2f32
; CHECK: SU(0): %0:fpr64 = FMINv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -333,6 +356,7 @@ name: fmin_fmin_v2f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_v2f32
; CHECK: SU(0): %0:fpr64 = FMINv2f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -347,6 +371,7 @@ name: fmax_fmax_v4f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_v4f32
; CHECK: SU(0): %0:fpr128 = FMAXv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -361,6 +386,7 @@ name: fmax_fmin_v4f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_v4f32
; CHECK: SU(0): %0:fpr128 = FMAXv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -375,6 +401,7 @@ name: fmin_fmax_v4f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_v4f32
; CHECK: SU(0): %0:fpr128 = FMINv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -389,6 +416,7 @@ name: fmin_fmin_v4f32
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_v4f32
; CHECK: SU(0): %0:fpr128 = FMINv4f32
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -403,6 +431,7 @@ name: fmax_fmax_v2f64
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmax_v2f64
; CHECK: SU(0): %0:fpr128 = FMAXv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -417,6 +446,7 @@ name: fmax_fmin_v2f64
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmax_fmin_v2f64
; CHECK: SU(0): %0:fpr128 = FMAXv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -431,6 +461,7 @@ name: fmin_fmax_v2f64
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmax_v2f64
; CHECK: SU(0): %0:fpr128 = FMINv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
@@ -445,6 +476,7 @@ name: fmin_fmin_v2f64
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: fmin_fmin_v2f64
; CHECK: SU(0): %0:fpr128 = FMINv2f64
; CHECK: Successors:
; FUSE: SU(2): Ord Latency={{[0-9]+}} Cluster
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