[llvm] [SLP][AArch64]Support masked div/rem on non-pow-2 vectors (PR #210623)

[Alexey Bataev via llvm-commits]

alexey-bataev wrote:

> hello, it seems not all backends support this intrinsic, which is fine but the vector operand splitter doesn't seem to support this intrinsic. please find attached a reproducer if you have time to take a look
> 
> ```llvm
> target triple = "nvptx64-nvidia-cuda"
> 
> declare <8 x i32> @llvm.masked.srem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>)
> 
> define <8 x i32> @masked_srem(<8 x i32> %x, <8 x i32> %y) {
> entry:
>   %r = call <8 x i32> @llvm.masked.srem.v8i32(
>       <8 x i32> %x, <8 x i32> %y,
>       <8 x i1> <i1 true, i1 true, i1 true, i1 true,
>                   i1 true, i1 false, i1 false, i1 false>)
>   ret <8 x i32> %r
> }
> ```
> 
> ```
> llc -mtriple=nvptx64-nvidia-cuda -mcpu=sm_100a \
>   /tmp/masked-srem-nvptx.ll -o /tmp/out.ptx
> ```
> 
> crashes with
> 
> ```
> LLVM ERROR: Do not know how to split this operator's operand!
> ```
> 
> happy to send a PR if necessary as well.

Looks like a codegen (lowering) issue for type legalization. Create and issue for NVPTX codegen

https://github.com/llvm/llvm-project/pull/210623