[llvm] [AMDGPU] Move EU and Wave Queries into TargetParser (PR #211312)
Soumil Kushwaha via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 09:48:01 PDT 2026
https://github.com/theSK2005 updated https://github.com/llvm/llvm-project/pull/211312
>From f7b1bb2d17b477fc8028af3ecd85bf01e5e6c607 Mon Sep 17 00:00:00 2001
From: Soumil Kushwaha <Soumil.Kushwaha at amd.com>
Date: Mon, 27 Jul 2026 12:22:07 -0500
Subject: [PATCH] moving VGPR/AGPR to stacked PR
---
.../llvm/TargetParser/AMDGPUTargetParser.h | 11 ++-
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td | 1 +
llvm/lib/Target/AMDGPU/GCNProcessors.td | 10 +--
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 2 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 51 ++++----------
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 8 ---
llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 69 +++++++++++++++++++
.../TargetParser/TargetParserTest.cpp | 35 ++++++++++
10 files changed, 139 insertions(+), 54 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
index f8e283db55fec..6cfe777df49bb 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
@@ -98,7 +98,10 @@ enum ArchFeatureKind : uint32_t {
FEATURE_XNACK_ON_OFF_MODES = 1 << 6,
// VI SGPR initialization bug requiring a fixed SGPR allocation size.
- FEATURE_SGPR_INIT_BUG = 1 << 7
+ FEATURE_SGPR_INIT_BUG = 1 << 7,
+
+ // AGPRs share a unified register file with VGPRs (gfx90a-insts).
+ FEATURE_AGPRS_UNIFIED_FILE = 1 << 8
};
enum FeatureError : uint32_t {
@@ -194,6 +197,12 @@ LLVM_ABI unsigned getAddressableNumSGPRs(Triple::SubArchType SubArch);
LLVM_ABI unsigned getSGPRAllocGranule(GPUKind AK);
LLVM_ABI unsigned getSGPRAllocGranule(Triple::SubArchType SubArch);
+LLVM_ABI unsigned getEUsPerCU(GPUKind AK, bool CuMode);
+LLVM_ABI unsigned getEUsPerCU(Triple::SubArchType SubArch, bool CuMode);
+
+LLVM_ABI unsigned getMaxWavesPerEU(GPUKind AK);
+LLVM_ABI unsigned getMaxWavesPerEU(Triple::SubArchType SubArch);
+
/// Fills Features map with default values for given target GPU.
/// \p Features contains overriding target features and this function returns
/// default target features with entries overridden by \p Features.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 3d337a466a75e..bc6bf709f3692 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -419,7 +419,7 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
const MCExpr *NumVGPRs,
unsigned DynamicVGPRBlockSize,
const GCNSubtarget &STM, MCContext &Ctx) {
- unsigned MaxWaves = IsaInfo::getMaxWavesPerEU(STM);
+ unsigned MaxWaves = AMDGPU::getMaxWavesPerEU(STM.getTargetID().getGPUKind());
unsigned Granule = IsaInfo::getVGPRAllocGranule(STM, DynamicVGPRBlockSize);
unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(STM);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td b/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
index e6ea319017436..1226b6eff1136 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
@@ -29,6 +29,7 @@ def FEATURE_SRAMECC : AMDGPUArchFeature<"FEATURE_SRAMECC">;
def FEATURE_WGP : AMDGPUArchFeature<"FEATURE_WGP">;
def FEATURE_XNACK_ON_OFF_MODES : AMDGPUArchFeature<"FEATURE_XNACK_ON_OFF_MODES">;
def FEATURE_SGPR_INIT_BUG : AMDGPUArchFeature<"FEATURE_SGPR_INIT_BUG">;
+def FEATURE_AGPRS_UNIFIED_FILE : AMDGPUArchFeature<"FEATURE_AGPRS_UNIFIED_FILE">;
// Marks a Processor/ProcessorModel record as a canonical GPU.
//
diff --git a/llvm/lib/Target/AMDGPU/GCNProcessors.td b/llvm/lib/Target/AMDGPU/GCNProcessors.td
index 47dc1f182c7b4..7e0bc9f45fd29 100644
--- a/llvm/lib/Target/AMDGPU/GCNProcessors.td
+++ b/llvm/lib/Target/AMDGPU/GCNProcessors.td
@@ -11,6 +11,8 @@
defvar ArchFeaturesW64Xnack = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32,
FEATURE_XNACK, FEATURE_XNACK_ON_OFF_MODES];
defvar ArchFeaturesW64XnackSramEcc = ArchFeaturesW64Xnack # [FEATURE_SRAMECC];
+defvar ArchFeaturesW64XnackSramEccAgprs =
+ ArchFeaturesW64XnackSramEcc # [FEATURE_AGPRS_UNIFIED_FILE];
defvar ArchFeaturesW32XnackWgp = [FEATURE_FAST_FMA_F32, FEATURE_FAST_DENORMAL_F32,
FEATURE_WAVE32, FEATURE_XNACK,
FEATURE_XNACK_ON_OFF_MODES, FEATURE_WGP];
@@ -170,7 +172,7 @@ def GFX909 : AMDGPUProcessorModel<"gfx909", SIQuarterSpeedModel,
def GFX90A : AMDGPUProcessorModel<"gfx90a", SIDPFullSpeedModel,
FeatureISAVersion9_0_A.Features, [9, 0, 0xa]> {
- let ArchFeatures = ArchFeaturesW64XnackSramEcc;
+ let ArchFeatures = ArchFeaturesW64XnackSramEccAgprs;
}
def GFX90C : AMDGPUProcessorModel<"gfx90c", SIQuarterSpeedModel,
@@ -180,12 +182,12 @@ def GFX90C : AMDGPUProcessorModel<"gfx90c", SIQuarterSpeedModel,
def GFX942 : AMDGPUProcessorModel<"gfx942", SIDPGFX942FullSpeedModel,
FeatureISAVersion9_4_2.Features, [9, 4, 2]> {
- let ArchFeatures = ArchFeaturesW64XnackSramEcc;
+ let ArchFeatures = ArchFeaturesW64XnackSramEccAgprs;
}
def GFX950 : AMDGPUProcessorModel<"gfx950", SIDPGFX950FullSpeedModel,
FeatureISAVersion9_5_0.Features, [9, 5, 0]> {
- let ArchFeatures = ArchFeaturesW64XnackSramEcc;
+ let ArchFeatures = ArchFeaturesW64XnackSramEccAgprs;
}
def GFX9_GENERIC : AMDGPUProcessorModel<"gfx9-generic", SIQuarterSpeedModel,
@@ -196,7 +198,7 @@ def GFX9_GENERIC : AMDGPUProcessorModel<"gfx9-generic", SIQuarterSpeedModel,
def GFX9_4_GENERIC : AMDGPUProcessorModel<"gfx9-4-generic", SIDPGFX942FullSpeedModel,
FeatureISAVersion9_4_Generic.Features, [9, 4, 0]> {
- let ArchFeatures = ArchFeaturesW64XnackSramEcc;
+ let ArchFeatures = ArchFeaturesW64XnackSramEccAgprs;
let CoveredGPUs = [GFX942, GFX950];
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 1c0e718bd8d97..7389aa9bb0f78 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -245,8 +245,8 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
LLVM_DEBUG(dbgs() << "sramecc setting for subtarget: "
<< TargetID.getSramEccSetting() << '\n');
- MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(*this);
- EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(*this);
+ MaxWavesPerEU = AMDGPU::getMaxWavesPerEU(getTargetID().getGPUKind());
+ EUsPerCU = AMDGPU::getEUsPerCU(getTargetID().getGPUKind(), isCuModeEnabled());
TSInfo = std::make_unique<AMDGPUSelectionDAGInfo>();
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 64188ad64061a..c2a315627b129 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -3689,7 +3689,7 @@ bool SIInsertWaitcnts::run() {
ST.getOccupancyWithNumVGPRs(
TRI.getNumUsedPhysRegs(MRI, AMDGPU::VGPR_32RegClass),
/*IsDynamicVGPR=*/false) <
- AMDGPU::IsaInfo::getMaxWavesPerEU(ST))) {
+ AMDGPU::getMaxWavesPerEU(ST.getTargetID().getGPUKind()))) {
for (auto [MI, Flag] : EndPgmInsts) {
if (Flag) {
if (ST.requiresNopBeforeDeallocVGPRs()) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 38329d6295538..f2dc920b36fb2 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1200,32 +1200,14 @@ unsigned getAddressableLocalMemorySize(const MCSubtargetInfo &STI) {
return 32768;
}
-unsigned getEUsPerCU(const MCSubtargetInfo &STI) {
- // "Per CU" really means "per whatever functional block the waves of a
- // workgroup must share".
-
- // GFX12.5 only supports CU mode, which contains four SIMDs.
- if (isGFX1250(STI)) {
- assert(STI.getFeatureBits().test(FeatureCuMode));
- return 4;
- }
-
- // For gfx10 in CU mode the functional block is the CU, which contains
- // two SIMDs.
- if (isGFX10Plus(STI) && STI.getFeatureBits().test(FeatureCuMode))
- return 2;
-
- // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP
- // contains two CUs, so a total of four SIMDs.
- return 4;
-}
-
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
unsigned FlatWorkGroupSize) {
assert(FlatWorkGroupSize != 0);
if (!STI.getTargetTriple().isAMDGCN())
return 8;
- unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool CuMode = STI.getFeatureBits().test(FeatureCuMode);
+ unsigned MaxWaves = getMaxWavesPerEU(Kind) * getEUsPerCU(Kind, CuMode);
unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
if (N == 1) {
// Single-wave workgroups don't consume barrier resources.
@@ -1241,19 +1223,12 @@ unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
unsigned getMinWavesPerEU(const MCSubtargetInfo &STI) { return 1; }
-unsigned getMaxWavesPerEU(const MCSubtargetInfo &STI) {
- // FIXME: Need to take scratch memory into account.
- if (isGFX90A(STI))
- return 8;
- if (!isGFX10Plus(STI))
- return 10;
- return hasGFX10_3Insts(STI) ? 16 : 20;
-}
-
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo &STI,
unsigned FlatWorkGroupSize) {
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool CuMode = STI.getFeatureBits().test(FeatureCuMode);
return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
- getEUsPerCU(STI));
+ getEUsPerCU(Kind, CuMode));
}
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo &STI) { return 1; }
@@ -1291,10 +1266,10 @@ unsigned getMinNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU) {
if (Version.Major >= 10)
return 0;
- if (WavesPerEU >= getMaxWavesPerEU(STI))
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ if (WavesPerEU >= getMaxWavesPerEU(Kind))
return 0;
- GPUKind Kind = parseArchAMDGCN(STI.getCPU());
unsigned MinNumSGPRs =
getSGPRBudgetPerWave(getTotalNumSGPRs(Kind), WavesPerEU + 1,
getSGPRTrapHandlerReserve(STI),
@@ -1442,9 +1417,10 @@ unsigned getAddressableNumVGPRs(const MCSubtargetInfo &STI,
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo &STI,
unsigned NumVGPRs,
unsigned DynamicVGPRBlockSize) {
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
return getNumWavesPerEUWithNumVGPRs(
NumVGPRs, getVGPRAllocGranule(STI, DynamicVGPRBlockSize),
- getMaxWavesPerEU(STI), getTotalNumVGPRs(STI));
+ getMaxWavesPerEU(Kind), getTotalNumVGPRs(STI));
}
unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
@@ -1467,12 +1443,12 @@ unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
}
unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs) {
- unsigned MaxWaves = getMaxWavesPerEU(STI);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ unsigned MaxWaves = getMaxWavesPerEU(Kind);
if (!isSGPROccupancyLimited(STI))
return MaxWaves;
- GPUKind Kind = parseArchAMDGCN(STI.getCPU());
return getOccupancyWithNumSGPRs(SGPRs, MaxWaves, getTotalNumSGPRs(Kind),
getSGPRAllocGranule(Kind),
getSGPRTrapHandlerReserve(STI));
@@ -1490,7 +1466,8 @@ unsigned getMinNumVGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
if (DynamicVGPREnabled)
return 0;
- unsigned MaxWavesPerEU = getMaxWavesPerEU(STI);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ unsigned MaxWavesPerEU = getMaxWavesPerEU(Kind);
if (WavesPerEU >= MaxWavesPerEU)
return 0;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 44476d4d555c0..03651f7fea1a0 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -183,10 +183,6 @@ unsigned getLocalMemorySize(const MCSubtargetInfo &STI);
/// \p STI.
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo &STI);
-/// \returns Number of execution units per compute unit for given subtarget \p
-/// STI.
-unsigned getEUsPerCU(const MCSubtargetInfo &STI);
-
/// \returns Maximum number of work groups per compute unit for given subtarget
/// \p STI and limited by given \p FlatWorkGroupSize.
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
@@ -196,10 +192,6 @@ unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
/// STI.
unsigned getMinWavesPerEU(const MCSubtargetInfo &STI);
-/// \returns Maximum number of waves per execution unit for given subtarget \p
-/// STI without any kind of limitation.
-unsigned getMaxWavesPerEU(const MCSubtargetInfo &STI);
-
/// \returns Number of waves per execution unit required to support the given \p
/// FlatWorkGroupSize.
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo &STI,
diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index d8abaf7474cd6..2953960d252f2 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -422,6 +422,75 @@ unsigned AMDGPU::getSGPRAllocGranule(Triple::SubArchType SubArch) {
return 8;
}
+unsigned AMDGPU::getEUsPerCU(GPUKind AK, bool CuMode) {
+ // "Per CU" really means "per whatever functional block the waves of a
+ // workgroup must share".
+ IsaVersion Version = getIsaVersion(getSubArch(AK));
+
+ // GFX12.5 only supports CU mode, which contains four SIMDs.
+ if (Version.Major == 12 && Version.Minor == 5) {
+ assert(CuMode);
+ return 4;
+ }
+
+ // For gfx10+ in CU mode the functional block is the CU, which contains
+ // two SIMDs.
+ if (Version.Major >= 10 && CuMode)
+ return 2;
+
+ // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP
+ // contains two CUs, so a total of four SIMDs.
+ return 4;
+}
+
+unsigned AMDGPU::getEUsPerCU(Triple::SubArchType SubArch, bool CuMode) {
+ // "Per CU" really means "per whatever functional block the waves of a
+ // workgroup must share".
+ IsaVersion Version = getIsaVersion(SubArch);
+
+ // GFX12.5 only supports CU mode, which contains four SIMDs.
+ if (Version.Major == 12 && Version.Minor == 5) {
+ assert(CuMode);
+ return 4;
+ }
+
+ // For gfx10+ in CU mode the functional block is the CU, which contains
+ // two SIMDs.
+ if (Version.Major >= 10 && CuMode)
+ return 2;
+
+ // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP
+ // contains two CUs, so a total of four SIMDs.
+ return 4;
+}
+
+// GFX10.3-style instructions are present on gfx10.3 and every later
+// generation (gfx11+). This matches the transitive expansion of the
+// FeatureGFX10_3Insts subtarget feature, which gfx11+ imply.
+static bool hasGFX10_3Insts(IsaVersion Version) {
+ return Version.Major >= 11 || (Version.Major == 10 && Version.Minor == 3);
+}
+
+unsigned AMDGPU::getMaxWavesPerEU(GPUKind AK) {
+ // FIXME: Need to take scratch memory into account.
+ if (getArchAttrAMDGCN(AK) & FEATURE_AGPRS_UNIFIED_FILE)
+ return 8;
+ IsaVersion Version = getIsaVersion(getSubArch(AK));
+ if (Version.Major < 10)
+ return 10;
+ return hasGFX10_3Insts(Version) ? 16 : 20;
+}
+
+unsigned AMDGPU::getMaxWavesPerEU(Triple::SubArchType SubArch) {
+ // FIXME: Need to take scratch memory into account.
+ if (getArchAttrAMDGCN(SubArch) & FEATURE_AGPRS_UNIFIED_FILE)
+ return 8;
+ IsaVersion Version = getIsaVersion(SubArch);
+ if (Version.Major < 10)
+ return 10;
+ return hasGFX10_3Insts(Version) ? 16 : 20;
+}
+
StringRef AMDGPU::getCanonicalArchName(const Triple &T, StringRef Arch) {
assert(T.isAMDGPU());
auto ProcKind = T.isAMDGCN() ? parseArchAMDGCN(Arch) : parseArchR600(Arch);
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 8939c0e7a162c..a2731e3fd88f8 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -3027,6 +3027,41 @@ TEST(TargetParserTest, testAMDGPUgetSGPRAllocGranule) {
EXPECT_EQ(AMDGPU::getSGPRAllocGranule(AMDGPU::GK_GFX1030), 106u);
}
+TEST(TargetParserTest, testAMDGPUgetEUsPerCU) {
+ // GFX12.5 is CU-mode only and always has four SIMDs. GFX10+ has two SIMDs in
+ // CU mode and four in WGP mode; pre-GFX10 always has four. Second arg is the
+ // CU-mode flag.
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1250, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, true), 2u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, false), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch600, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch900, false), 4u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1250, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1030, true), 2u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX600, false), 4u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetMaxWavesPerEU) {
+ // GFX90A -> 8, pre-GFX10 -> 10, gfx10.1 -> 20; GFX10.3-style instructions
+ // (gfx10.3 and every later generation, gfx11+) -> 16.
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch90A), 8u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch600), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch900), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1010), 20u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1030), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1100), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1250), 16u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX90A), 8u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX900), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1010), 20u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1030), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1100), 16u);
+}
+
TEST(TargetParserTest, testAMDGPUParseTargetIDString) {
using AMDGPU::TargetID;
using AMDGPU::TargetIDSetting;
More information about the llvm-commits
mailing list