[llvm] [AArch64][NEON] Fold insert(zero, extract(X, 0), 0) -> X when X is known to zero lanes 1-N (PR #213940)

[Paul Walker via llvm-commits]

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paulwalker-arm wrote:

I don't think these are universally safe.  If you look at ISel you'll see things like:
```
def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
          (ADDPv2i32 V64:$Rn, V64:$Rn)>;
```
where ADDPv2i32 is not going to zero bits 33-127. Searching for AArch64uaddv, I can see many patterns that look like they don't emit the necessary uaddv instruction. It looks like a similar story for the other reductions. I think the safest option is to add dedicated isel patterns.

https://github.com/llvm/llvm-project/pull/213940