[llvm] [AArch64][GlobalISel] Legalize <8 x i1> and <16 x i1> loads and stores (PR #210514)

[Joel Walker via llvm-commits]

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Joel-Wwalker wrote:

I poked at this while reworking the patch. The two shapes the bitcast route would create both legalize cleanly on current main — I ran G_TRUNC of <2 x s32> to <2 x s8> and G_BITCAST of s16 to <2 x s8> through -run-pass=legalizer, and both go through widen/unmerge sequences without falling back or looping. So whatever the G_TRUNC problem was when the TODO was written, at least the basic shapes work now.

Today a <2 x i8> load scalarizes into two byte loads plus a lane insert, where SelectionDAG does one ldrh and widens. So the TODO looks worth trying, but flipping it changes codegen for the existing v2i8/v2i16 tests and deserves its own sweep, so I'd rather attempt it as a separate change after these land.

https://github.com/llvm/llvm-project/pull/210514