[llvm] [AMDGPU] Fix combineMasks dropping condition (PR #203180)

[Arseniy Obolenskiy via llvm-commits]

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@@ -602,22 +602,41 @@ void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
 // One of the operands is exec mask.
 void SILowerControlFlow::combineMasks(MachineInstr &MI) {
   assert(MI.getNumExplicitOperands() == 3);
-  SmallVector<MachineOperand, 4> Ops;
-  unsigned OpToReplace = 1;
-  findMaskOperands(MI, 1, Ops);
-  if (Ops.size() == 1) OpToReplace = 2; // First operand can be exec or its copy
-  findMaskOperands(MI, 2, Ops);
-  if (Ops.size() != 3) return;
-
-  unsigned UniqueOpndIdx;
-  if (Ops[0].isIdenticalTo(Ops[1])) UniqueOpndIdx = 2;
-  else if (Ops[0].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;
-  else if (Ops[1].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;
-  else return;
+  SmallVector<MachineOperand, 2> Src1, Src2;
+  findMaskOperands(MI, 1, Src1);
+  findMaskOperands(MI, 2, Src2);
+
+  // Exactly one of the two operands must resolve to the nested LHS and RHS.
+  // Another one must resolve to a single value, exec or its copy.
+  unsigned OpToReplace;
+  MachineOperand *Leaf, *NestedLHS, *NestedRHS;
+  if (Src1.size() == 2 && Src2.size() == 1) {
+    OpToReplace = 1;
+    NestedLHS = &Src1[0];
+    NestedRHS = &Src1[1];
+    Leaf = &Src2[0];
+  } else if (Src1.size() == 1 && Src2.size() == 2) {
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aobolensk wrote:

added combine_masks_nested_second_operand covering the case where the nested op is the second operand

https://github.com/llvm/llvm-project/pull/203180