[llvm] [AArch64][GlobalISel] Legalize <8 x i1> and <16 x i1> loads and stores (PR #210514)

[Joel Walker via llvm-commits]

Joel-Wwalker wrote:

@osa1 done: #213946 has the bitcast changes (the two folds and the pack), and this PR is down to the load/store rules stacked on top — the first commit here is #213946, the second is what's left to review.

On the `<128 x i1>` case: I ran it against this patch and it still fails, just later. 128 lanes is outside the pack's gate, so the cast falls back to the stack round-trip, and the v128s1 stack store then fails to legalize — so it's more than extending the type sets. SelectionDAG compiles it with the same sext-and-mask idiom followed by a halving addp tree. Extending the pack that way (or chunking into 16-lane packs and merging the pieces) fits naturally in #213946's code, but I'd rather do it as a follow-up on top so each piece stays reviewable. One aside: SelectionDAG doesn't constant-fold the zeroinitializer form either, it emits the full pack of a zero vector.

https://github.com/llvm/llvm-project/pull/210514