[llvm] [X86] Replace custom AND/OR/XOR reduction pattern matching with ISD::VECREDUCE_AND/OR/XOR support (PR #199544)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 06:33:02 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
The middle-end (SLP, VectorCombine and InstCombine) recognition and handling of vector logic reduction patterns is sufficient now, so the backend can work with ISD::VECREDUCE_AND/OR/XOR nodes directly.
---
Patch is 88.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/199544.diff
10 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+43-29)
- (modified) llvm/lib/Target/X86/X86TargetTransformInfo.cpp (+3)
- (modified) llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll (+14-14)
- (modified) llvm/test/CodeGen/X86/pr53419.ll (+15-15)
- (modified) llvm/test/CodeGen/X86/vector-extract-last-active.ll (+61-86)
- (modified) llvm/test/CodeGen/X86/vector-reduce-and.ll (+102-102)
- (modified) llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll (+17-8)
- (modified) llvm/test/CodeGen/X86/vector-reduce-or.ll (+102-102)
- (modified) llvm/test/CodeGen/X86/vector-reduce-xor.ll (+102-102)
- (modified) llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll (+2-10)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dfda1157a720e..c84e69e66d86b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1176,15 +1176,15 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
- setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
- setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
- setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
}
// SSE2 can use basic vector unrolling.
// SSE41 can use PHMINPOS to perform v16i8/v8i16 minmax reductions.
// Fallback to ReplaceNodeResults for vXi64 reductions on 32-bit targets.
for (auto VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::i64}) {
+ setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
@@ -2836,6 +2836,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
ISD::ANY_EXTEND_VECTOR_INREG,
ISD::SIGN_EXTEND_VECTOR_INREG,
ISD::ZERO_EXTEND_VECTOR_INREG,
+ ISD::VECREDUCE_AND,
+ ISD::VECREDUCE_OR,
+ ISD::VECREDUCE_XOR,
ISD::VECREDUCE_MUL,
ISD::SINT_TO_FP,
ISD::UINT_TO_FP,
@@ -23673,16 +23676,14 @@ static SDValue MatchVectorAllEqualTest(SDValue OrigLHS, SDValue OrigRHS,
// Match icmp(reduce_or(X),0) anyof reduction patterns.
// Match icmp(reduce_and(X),-1) allof reduction patterns.
- if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- ISD::NodeType BinOp;
- if (SDValue Match =
- DAG.matchBinOpReduction(Op.getNode(), BinOp, {LogicOp})) {
- EVT MatchVT = Match.getValueType();
- return LowerVectorAllEqual(DL, Match,
- CmpNull ? DAG.getConstant(0, DL, MatchVT)
- : DAG.getAllOnesConstant(DL, MatchVT),
- CC, Mask, Subtarget, DAG, X86CC);
- }
+ if ((LogicOp == ISD::AND && Op.getOpcode() == ISD::VECREDUCE_AND) ||
+ (LogicOp == ISD::OR && Op.getOpcode() == ISD::VECREDUCE_OR)) {
+ SDValue Match = Op.getOperand(0);
+ EVT MatchVT = Match.getValueType();
+ return LowerVectorAllEqual(DL, Match,
+ CmpNull ? DAG.getConstant(0, DL, MatchVT)
+ : DAG.getAllOnesConstant(DL, MatchVT),
+ CC, Mask, Subtarget, DAG, X86CC);
}
if (Mask.isAllOnes()) {
@@ -35335,6 +35336,14 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
}
return;
}
+ case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
+ case ISD::VECREDUCE_XOR: {
+ assert(N->getValueType(0) == MVT::i64 && "Unexpected vector reduction");
+ if (SDValue Res = LowerVECREDUCE(SDValue(N, 0), Subtarget, DAG, true))
+ Results.push_back(Res);
+ return;
+ }
case ISD::VECREDUCE_MUL: {
assert(N->getValueType(0) == MVT::i64 && "Unexpected vector reduction");
if (SDValue Res = LowerVECREDUCE(SDValue(N, 0), Subtarget, DAG, false))
@@ -47164,33 +47173,33 @@ static SDValue createPSADBW(SelectionDAG &DAG, SDValue N0, SDValue N1,
}
// Attempt to replace an all_of/any_of/parity style horizontal reduction with a MOVMSK.
-static SDValue combinePredicateReduction(SDNode *Extract, SelectionDAG &DAG,
+static SDValue combinePredicateReduction(SDNode *Reduce, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
// Bail without SSE2.
if (!Subtarget.hasSSE2())
return SDValue();
- EVT ExtractVT = Extract->getValueType(0);
+ // Check for OR(any_of)/AND(all_of)/XOR(parity) horizontal reduction patterns.
+ if (Reduce->getOpcode() != ISD::VECREDUCE_AND &&
+ Reduce->getOpcode() != ISD::VECREDUCE_OR &&
+ Reduce->getOpcode() != ISD::VECREDUCE_XOR)
+ return SDValue();
+
+ ISD::NodeType BinOp = ISD::getVecReduceBaseOpcode(Reduce->getOpcode());
+ SDValue Match = Reduce->getOperand(0);
+ EVT ExtractVT = Reduce->getValueType(0);
unsigned BitWidth = ExtractVT.getSizeInBits();
if (ExtractVT != MVT::i64 && ExtractVT != MVT::i32 && ExtractVT != MVT::i16 &&
ExtractVT != MVT::i8 && ExtractVT != MVT::i1)
return SDValue();
- // Check for OR(any_of)/AND(all_of)/XOR(parity) horizontal reduction patterns.
- ISD::NodeType BinOp;
- SDValue Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::OR, ISD::AND});
- if (!Match && ExtractVT == MVT::i1)
- Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::XOR});
- if (!Match)
- return SDValue();
-
- // EXTRACT_VECTOR_ELT can require implicit extension of the vector element
+ // ISD::VECREDUCE_* can require implicit extension of the vector element
// which we can't support here for now.
if (Match.getScalarValueSizeInBits() != BitWidth)
return SDValue();
SDValue Movmsk;
- SDLoc DL(Extract);
+ SDLoc DL(Reduce);
EVT MatchVT = Match.getValueType();
unsigned NumElts = MatchVT.getVectorNumElements();
unsigned MaxElts = Subtarget.hasInt256() ? 32 : 16;
@@ -48081,10 +48090,6 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
if (SDValue VPDPBUSD = combineVPDPBUSDPattern(N, DAG, Subtarget))
return VPDPBUSD;
- // Attempt to replace an all_of/any_of horizontal reduction with a MOVMSK.
- if (SDValue Cmp = combinePredicateReduction(N, DAG, Subtarget))
- return Cmp;
-
// Attempt to optimize ADD/FADD reductions with HADD, promotion etc..
if (SDValue V = combineArithReduction(N, DAG, Subtarget))
return V;
@@ -48174,6 +48179,12 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+static SDValue combineVECREDUCE_LOGIC(SDNode *N, SelectionDAG &DAG,
+ const X86Subtarget &Subtarget) {
+ // Attempt to replace an all_of/any_of horizontal reduction with a MOVMSK.
+ return combinePredicateReduction(N, DAG, Subtarget);
+}
+
static SDValue combineVECREDUCE_MUL(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
SDValue Src = N->getOperand(0);
@@ -63099,6 +63110,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::VFCMULC:
case X86ISD::VFMULC: return combineFMulcFCMulc(N, DAG, Subtarget);
case ISD::FNEG: return combineFneg(N, DAG, DCI, Subtarget);
+ case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
+ case ISD::VECREDUCE_XOR: return combineVECREDUCE_LOGIC(N, DAG, Subtarget);
case ISD::VECREDUCE_MUL: return combineVECREDUCE_MUL(N, DAG, Subtarget);
case ISD::TRUNCATE: return combineTruncate(N, DAG, Subtarget);
case X86ISD::VTRUNC: return combineVTRUNC(N, DAG, DCI);
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 421a2829cb509..2f14d905f779c 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -6937,6 +6937,9 @@ bool X86TTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
switch (II->getIntrinsicID()) {
default:
return true;
+ case Intrinsic::vector_reduce_and:
+ case Intrinsic::vector_reduce_or:
+ case Intrinsic::vector_reduce_xor:
case Intrinsic::vector_reduce_mul:
case Intrinsic::vector_reduce_smax:
case Intrinsic::vector_reduce_smin:
diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
index a2caf173dd8ae..24c358f52c794 100644
--- a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
@@ -6614,7 +6614,7 @@ define i64 @test_mm512_reduce_or_epi64(<8 x i64> %__W) nounwind {
; X86-LABEL: test_mm512_reduce_or_epi64:
; X86: # %bb.0: # %entry
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpor %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6627,7 +6627,7 @@ define i64 @test_mm512_reduce_or_epi64(<8 x i64> %__W) nounwind {
; X64-LABEL: test_mm512_reduce_or_epi64:
; X64: # %bb.0: # %entry
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6644,7 +6644,7 @@ define i64 @test_mm512_reduce_and_epi64(<8 x i64> %__W) nounwind {
; X86-LABEL: test_mm512_reduce_and_epi64:
; X86: # %bb.0: # %entry
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpand %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6657,7 +6657,7 @@ define i64 @test_mm512_reduce_and_epi64(<8 x i64> %__W) nounwind {
; X64-LABEL: test_mm512_reduce_and_epi64:
; X64: # %bb.0: # %entry
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpand %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6789,7 +6789,7 @@ define i64 @test_mm512_mask_reduce_and_epi64(i8 zeroext %__M, <8 x i64> %__W) no
; X86-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X86-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpandq %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpand %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6805,7 +6805,7 @@ define i64 @test_mm512_mask_reduce_and_epi64(i8 zeroext %__M, <8 x i64> %__W) no
; X64-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X64-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpandq %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpand %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6827,7 +6827,7 @@ define i64 @test_mm512_mask_reduce_or_epi64(i8 zeroext %__M, <8 x i64> %__W) nou
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpor %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6842,7 +6842,7 @@ define i64 @test_mm512_mask_reduce_or_epi64(i8 zeroext %__M, <8 x i64> %__W) nou
; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vporq %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6901,7 +6901,7 @@ define i32 @test_mm512_reduce_or_epi32(<8 x i64> %__W) nounwind {
; CHECK-LABEL: test_mm512_reduce_or_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpor %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -6921,7 +6921,7 @@ define i32 @test_mm512_reduce_and_epi32(<8 x i64> %__W) nounwind {
; CHECK-LABEL: test_mm512_reduce_and_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: vpand %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7029,7 +7029,7 @@ define i32 @test_mm512_mask_reduce_and_epi32(i16 zeroext %__M, <8 x i64> %__W) n
; X86-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X86-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X86-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X86-NEXT: vpandd %zmm0, %zmm1, %zmm0
+; X86-NEXT: vpand %ymm0, %ymm1, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7046,7 +7046,7 @@ define i32 @test_mm512_mask_reduce_and_epi32(i16 zeroext %__M, <8 x i64> %__W) n
; X64-NEXT: vpternlogd {{.*#+}} zmm1 = -1
; X64-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
; X64-NEXT: vextracti64x4 $1, %zmm1, %ymm0
-; X64-NEXT: vpandd %zmm0, %zmm1, %zmm0
+; X64-NEXT: vpand %ymm0, %ymm1, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7071,7 +7071,7 @@ define i32 @test_mm512_mask_reduce_or_epi32(i16 zeroext %__M, <8 x i64> %__W) no
; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
; X86-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X86-NEXT: vpord %zmm1, %zmm0, %zmm0
+; X86-NEXT: vpor %ymm1, %ymm0, %ymm0
; X86-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
@@ -7087,7 +7087,7 @@ define i32 @test_mm512_mask_reduce_or_epi32(i16 zeroext %__M, <8 x i64> %__W) no
; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vmovdqa32 %zmm0, %zmm0 {%k1} {z}
; X64-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; X64-NEXT: vpord %zmm1, %zmm0, %zmm0
+; X64-NEXT: vpor %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
diff --git a/llvm/test/CodeGen/X86/pr53419.ll b/llvm/test/CodeGen/X86/pr53419.ll
index 750751d404f38..b4c01676d73b4 100644
--- a/llvm/test/CodeGen/X86/pr53419.ll
+++ b/llvm/test/CodeGen/X86/pr53419.ll
@@ -15,8 +15,8 @@ declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
define i1 @intrinsic_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X64-LABEL: intrinsic_v2i8:
; X64: # %bb.0: # %bb
-; X64-NEXT: movzwl (%rsi), %eax
-; X64-NEXT: cmpw (%rdi), %ax
+; X64-NEXT: movzwl (%rdi), %eax
+; X64-NEXT: cmpw %ax, (%rsi)
; X64-NEXT: sete %al
; X64-NEXT: retq
;
@@ -24,8 +24,8 @@ define i1 @intrinsic_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X86: # %bb.0: # %bb
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movzwl (%ecx), %ecx
-; X86-NEXT: cmpw (%eax), %cx
+; X86-NEXT: movzwl (%eax), %eax
+; X86-NEXT: cmpw %ax, (%ecx)
; X86-NEXT: sete %al
; X86-NEXT: retl
bb:
@@ -39,8 +39,8 @@ bb:
define i1 @intrinsic_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X64-LABEL: intrinsic_v4i8:
; X64: # %bb.0: # %bb
-; X64-NEXT: movl (%rsi), %eax
-; X64-NEXT: cmpl (%rdi), %eax
+; X64-NEXT: movl (%rdi), %eax
+; X64-NEXT: cmpl %eax, (%rsi)
; X64-NEXT: sete %al
; X64-NEXT: retq
;
@@ -48,8 +48,8 @@ define i1 @intrinsic_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X86: # %bb.0: # %bb
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl (%ecx), %ecx
-; X86-NEXT: cmpl (%eax), %ecx
+; X86-NEXT: movl (%eax), %eax
+; X86-NEXT: cmpl %eax, (%ecx)
; X86-NEXT: sete %al
; X86-NEXT: retl
bb:
@@ -63,8 +63,8 @@ bb:
define i1 @intrinsic_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X64-LABEL: intrinsic_v8i8:
; X64: # %bb.0: # %bb
-; X64-NEXT: movq (%rsi), %rax
-; X64-NEXT: cmpq (%rdi), %rax
+; X64-NEXT: movq (%rdi), %rax
+; X64-NEXT: cmpq %rax, (%rsi)
; X64-NEXT: sete %al
; X64-NEXT: retq
;
@@ -72,11 +72,11 @@ define i1 @intrinsic_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {
; X86: # %bb.0: # %bb
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl (%ecx), %edx
-; X86-NEXT: movl 4(%ecx), %ecx
-; X86-NEXT: xorl 4(%eax), %ecx
-; X86-NEXT: xorl (%eax), %edx
-; X86-NEXT: orl %ecx, %edx
+; X86-NEXT: movl (%eax), %edx
+; X86-NEXT: movl 4(%eax), %eax
+; X86-NEXT: xorl 4(%ecx), %eax
+; X86-NEXT: xorl (%ecx), %edx
+; X86-NEXT: orl %eax, %edx
; X86-NEXT: sete %al
; X86-NEXT: retl
bb:
diff --git a/llvm/test/CodeGen/X86/vector-extract-last-active.ll b/llvm/test/CodeGen/X86/vector-extract-last-active.ll
index 3f0a0c587415e..d3469d561184f 100644
--- a/llvm/test/CodeGen/X86/vector-extract-last-active.ll
+++ b/llvm/test/CodeGen/X86/vector-extract-last-active.ll
@@ -8,35 +8,30 @@
define i32 @extract_last_active_v4i32(<4 x i32> %a, <4 x i1> %c) {
; CHECK-LABEL: extract_last_active_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
-; CHECK-NEXT: por %xmm1, %xmm2
; CHECK-NEXT: pslld $31, %xmm1
+; CHECK-NEXT: movmskps %xmm1, %ecx
; CHECK-NEXT: psrad $31, %xmm1
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648,2147483648,2147483648]
-; CHECK-NEXT: movdqa %xmm1, %xmm3
-; CHECK-NEXT: por %xmm0, %xmm3
-; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
-; CHECK-NEXT: por %xmm4, %xmm0
-; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
-; CHECK-NEXT: pand %xmm3, %xmm1
-; CHECK-NEXT: pandn %xmm4, %xmm3
-; CHECK-NEXT: por %xmm1, %xmm3
-; CHECK-NEXT: movd %xmm3, %eax
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1]
-; CHECK-NEXT: movd %xmm0, %ecx
-; CHECK-NEXT: cmpl %ecx, %eax
-; CHECK-NEXT: cmoval %eax, %ecx
-; CHECK-NEXT: andl $3, %ecx
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: por %xmm0, %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; CHECK-NEXT: por %xmm3, %xmm0
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
+; CHECK-NEXT: pand %xmm2, %xmm1
+; CHECK-NEXT: pandn %xmm3, %xmm2
+; CHECK-NEXT: por %xmm1, %xmm2
+; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; CHECK-NEXT: por %xmm2, %xmm0
; CHECK-NEXT: movd %xmm0, %edx
-; CHECK-NEXT: andb $1, %dl
+; CHECK-NEXT: cmpl %edx, %eax
+; CHECK-NEXT: cmoval %eax, %edx
+; CHECK-NEXT: andl $3, %edx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb $1, %dl
+; CHECK-NEXT: cmpl $1, %ecx
; CHECK-NEXT: sbbl %eax, %eax
-; CHECK-NEXT: orl -24(%rsp,%rcx,4), %eax
+; CHECK-NEXT: orl -24(%rsp,%rdx,4), %eax
; CHECK-NEXT: retq
%res = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> %a, <4 x i1> %c, i32 -1)
ret i32 %res
@@ -74,14 +69,11 @@ define i32 @extract_last_active_v4i32_no_default(<4 x i32> %a, <4 x i1> %c) {
define i32 @extract_last_active_v2i32(<2 x i32> %a, <2 x i1> %c) {
; CHECK-LABEL: extract_last_active_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
-; CHECK-NEXT: por %xmm1, %xmm2
-; CHECK-NEXT: psllq $63, %xmm1
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT: movq %xmm2, %rcx
-; CHECK-NEXT: andb $1, %cl
+; CHECK-NEXT: psllq $63, %xmm1
+; CHECK-NEXT: movmskpd %xmm1, %ecx
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb $1, %cl
+; CHECK-NEXT: cmpl $1, %ecx
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3]
; CHECK-NEXT: psrld $31, %xmm0
@@ -141,34 +133,28 @@ define i32 @extract_last_active_v3i32(<3 x i32> %a, <3 x i1> %c) {
define i32 @extract_last_active_v8i32(<8 x i32> %a, <8 x i...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/199544
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