[llvm] [SDAG] Add basic type legalization for experimental.vector.match (PR #213344)

[Benjamin Maxwell via llvm-commits]

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@@ -1023,16 +1157,47 @@ define <4 x i1> @match_v4xi32_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %ma
 }
 
 define <2 x i1> @match_v2xi64_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) {
-; CHECK-LABEL: match_v2xi64_v2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT:    vrgather.vi v10, v9, 1
-; CHECK-NEXT:    vrgather.vi v11, v9, 0
-; CHECK-NEXT:    vmseq.vv v9, v8, v10
-; CHECK-NEXT:    vmseq.vv v8, v8, v11
-; CHECK-NEXT:    vmor.mm v8, v8, v9
-; CHECK-NEXT:    vmand.mm v0, v8, v0
-; CHECK-NEXT:    ret
+; RV32-LABEL: match_v2xi64_v2i64:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    li a0, 32
+; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; RV32-NEXT:    vmv.x.s a1, v9
+; RV32-NEXT:    vsrl.vx v10, v9, a0
+; RV32-NEXT:    vmv.x.s a2, v10
+; RV32-NEXT:    vslidedown.vi v9, v9, 1
+; RV32-NEXT:    vmv.x.s a3, v9
+; RV32-NEXT:    vsrl.vx v9, v9, a0
+; RV32-NEXT:    vmv.x.s a0, v9
+; RV32-NEXT:    sw a1, 8(sp)
+; RV32-NEXT:    sw a2, 12(sp)
+; RV32-NEXT:    sw a3, 0(sp)
+; RV32-NEXT:    sw a0, 4(sp)
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT:    vlse64.v v9, (a0), zero
+; RV32-NEXT:    mv a0, sp
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MacDue wrote:

I don't know too much about the RISC-V lowering, but it seem like the expansion occurs too late for the splat to be pattern matched into something that avoids the spills. 

https://github.com/llvm/llvm-project/pull/213344