[llvm] 07a53be - [GlobalISel] Combine merge-unmerge with mixed scalar and vector types (#213086)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 06:26:25 PDT 2026
Author: Madhur Kumar
Date: 2026-08-04T15:26:20+02:00
New Revision: 07a53be7d3cd68b7b4c397eb3ec5b30bc84acbf9
URL: https://github.com/llvm/llvm-project/commit/07a53be7d3cd68b7b4c397eb3ec5b30bc84acbf9
DIFF: https://github.com/llvm/llvm-project/commit/07a53be7d3cd68b7b4c397eb3ec5b30bc84acbf9.diff
LOG: [GlobalISel] Combine merge-unmerge with mixed scalar and vector types (#213086)
fixes: https://github.com/llvm/llvm-project/issues/177416
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 08e567f2e640a..f5a8f2d83a6c2 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -1023,7 +1023,8 @@ class LegalizationArtifactCombiner {
}
// Recognize UnmergeSrc that can be unmerged to DstTy directly.
- // Types have to be either both vector or both non-vector types.
+ // Types can be either both vector or both non-vector types, or one
+ // is a vector type and the other is a scalar type.
// In case of vector types, the scalar elements need to match.
// Merge-like opcodes are combined one at the time. First one creates new
// unmerge, following should use the same unmerge (builder performs CSE).
@@ -1033,15 +1034,23 @@ class LegalizationArtifactCombiner {
// %AnotherDst:_(DstTy) = G_merge_like_opcode %2:_(EltTy), %3
//
// %Dst:_(DstTy), %AnotherDst = G_UNMERGE_VALUES %UnmergeSrc
+ bool MixedVectorScalar = DstTy.isVector() != UnmergeSrcTy.isVector();
if ((DstSize < UnmergeSrcSize) &&
- ((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
- (DstTy.isVector() && UnmergeSrcTy.isVector() &&
- DstTy.getScalarType() == UnmergeSrcTy.getScalarType())) &&
+ (!DstTy.isVector() || !UnmergeSrcTy.isVector() ||
+ DstTy.getScalarType() == UnmergeSrcTy.getScalarType()) &&
(Elt0UnmergeIdx % NumMIElts == 0) &&
- getCoverTy(UnmergeSrcTy, DstTy) == UnmergeSrcTy) {
+ (MixedVectorScalar
+ ? UnmergeSrcSize % DstSize == 0
+ : getCoverTy(UnmergeSrcTy, DstTy) == UnmergeSrcTy)) {
if (!isSequenceFromUnmerge(MI, 0, Unmerge, Elt0UnmergeIdx, NumMIElts,
EltSize, false))
return false;
+ if (MixedVectorScalar) {
+ LegalizeActionStep ActionStep = LI.getAction(
+ {TargetOpcode::G_UNMERGE_VALUES, {DstTy, UnmergeSrcTy}});
+ if (ActionStep.Action != LegalizeAction::Legal)
+ return false;
+ }
MIB.setInstrAndDebugLoc(MI);
auto NewUnmerge = MIB.buildUnmerge(DstTy, Unmerge->getSourceReg());
unsigned DstIdx = (Elt0UnmergeIdx * EltSize) / DstTy.getSizeInBits();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
index d553f16d49013..239dfa9698192 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
@@ -750,8 +750,6 @@ define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_andn2_v3i16:
@@ -824,8 +822,6 @@ define amdgpu_ps i48 @s_andn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inr
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_andn2_v3i16_commute:
@@ -913,10 +909,7 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s4, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s4, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -953,20 +946,16 @@ define <3 x i16> @v_andn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v3
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
index 9f0ef53b922a0..efc4b1038b2fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
@@ -1611,3 +1611,180 @@ body: |
$vgpr0 = COPY %4
$vgpr1 = COPY %5
...
+
+# Vector to integer unmerge + merge combine tests.
+# G_UNMERGE_VALUES of a vector feeding G_MERGE_VALUES into an integer
+# should fold to direct G_UNMERGE_VALUES of the source vector.
+
+---
+name: vector_to_integer_merge_values
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: vector_to_integer_merge_values
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
+ ; CHECK-NEXT: $vgpr1 = COPY [[UV3]](i32)
+ %0:_(<4 x i16>) = COPY $vgpr0_vgpr1
+ %1:_(i16), %2:_(i16), %3:_(i16), %4:_(i16) = G_UNMERGE_VALUES %0:_(<4 x i16>)
+ %5:_(i32) = G_MERGE_VALUES %1:_(i16), %2:_(i16)
+ %6:_(i32) = G_MERGE_VALUES %3:_(i16), %4:_(i16)
+ $vgpr0 = COPY %5:_(i32)
+ $vgpr1 = COPY %6:_(i32)
+...
+---
+name: vector_to_integer_build_vector
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: vector_to_integer_build_vector
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i16>), [[UV1:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x i16>), [[UV3:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x i16>)
+ ; CHECK-NEXT: $vgpr1 = COPY [[UV3]](<2 x i16>)
+ %0:_(<4 x i16>) = COPY $vgpr0_vgpr1
+ %1:_(i16), %2:_(i16), %3:_(i16), %4:_(i16) = G_UNMERGE_VALUES %0:_(<4 x i16>)
+ %5:_(<2 x i16>) = G_BUILD_VECTOR %1:_(i16), %2:_(i16)
+ %6:_(<2 x i16>) = G_BUILD_VECTOR %3:_(i16), %4:_(i16)
+ $vgpr0 = COPY %5:_(<2 x i16>)
+ $vgpr1 = COPY %6:_(<2 x i16>)
+...
+---
+name: integer_to_vector_no_fold
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: integer_to_vector_no_fold
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](i64)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[UV1]](i32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x i32>)
+ %0:_(i64) = COPY $vgpr0_vgpr1
+ %1:_(i32), %2:_(i32) = G_UNMERGE_VALUES %0:_(i64)
+ %3:_(<2 x i32>) = G_BUILD_VECTOR %1:_(i32), %2:_(i32)
+ $vgpr0_vgpr1 = COPY %3:_(<2 x i32>)
+...
+---
+name: equal_size_no_fold
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: equal_size_no_fold
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x i32>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<2 x i32>)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[UV]](i32), [[UV1]](i32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](i64)
+ %0:_(<2 x i32>) = COPY $vgpr0_vgpr1
+ %1:_(i32), %2:_(i32) = G_UNMERGE_VALUES %0:_(<2 x i32>)
+ %3:_(i64) = G_MERGE_VALUES %1:_(i32), %2:_(i32)
+ $vgpr0_vgpr1 = COPY %3:_(i64)
+...
+---
+name: vector_to_integer_eight_i16
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: vector_to_integer_eight_i16
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x i16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<8 x i16>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32), [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<8 x i16>)
+ ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32), [[UV10:%[0-9]+]]:_(i32), [[UV11:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<8 x i16>)
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32), [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<8 x i16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](i32)
+ ; CHECK-NEXT: $vgpr1 = COPY [[UV5]](i32)
+ ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](i32)
+ ; CHECK-NEXT: $vgpr3 = COPY [[UV15]](i32)
+ %0:_(<8 x i16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(i16), %2:_(i16), %3:_(i16), %4:_(i16), %5:_(i16), %6:_(i16), %7:_(i16), %8:_(i16) = G_UNMERGE_VALUES %0:_(<8 x i16>)
+ %9:_(i32) = G_MERGE_VALUES %1:_(i16), %2:_(i16)
+ %10:_(i32) = G_MERGE_VALUES %3:_(i16), %4:_(i16)
+ %11:_(i32) = G_MERGE_VALUES %5:_(i16), %6:_(i16)
+ %12:_(i32) = G_MERGE_VALUES %7:_(i16), %8:_(i16)
+ $vgpr0 = COPY %9:_(i32)
+ $vgpr1 = COPY %10:_(i32)
+ $vgpr2 = COPY %11:_(i32)
+ $vgpr3 = COPY %12:_(i32)
+...
+---
+name: non_zero_start_index
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: non_zero_start_index
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x i16>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](<4 x i16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](i32)
+ %0:_(<4 x i16>) = COPY $vgpr0_vgpr1
+ %1:_(i16), %2:_(i16), %3:_(i16), %4:_(i16) = G_UNMERGE_VALUES %0:_(<4 x i16>)
+ %5:_(i32) = G_MERGE_VALUES %3:_(i16), %4:_(i16)
+ $vgpr0 = COPY %5:_(i32)
+...
+
+# Integer to vector unmerge + build_vector combine tests.
+# G_UNMERGE_VALUES of an integer feeding G_BUILD_VECTOR into a vector should
+# fold to direct G_UNMERGE_VALUES of the source integer.
+
+---
+name: integer_to_vector_build_vector
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: integer_to_vector_build_vector
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i32>), [[UV1:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY]](i128)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x i32>), [[UV3:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[COPY]](i128)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](<2 x i32>)
+ ; CHECK-NEXT: $vgpr2_vgpr3 = COPY [[UV3]](<2 x i32>)
+ %0:_(i128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(i32), %2:_(i32), %3:_(i32), %4:_(i32) = G_UNMERGE_VALUES %0:_(i128)
+ %5:_(<2 x i32>) = G_BUILD_VECTOR %1:_(i32), %2:_(i32)
+ %6:_(<2 x i32>) = G_BUILD_VECTOR %3:_(i32), %4:_(i32)
+ $vgpr0_vgpr1 = COPY %5:_(<2 x i32>)
+ $vgpr2_vgpr3 = COPY %6:_(<2 x i32>)
+...
+---
+name: integer_to_vector_non_divisible
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: integer_to_vector_non_divisible
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](i128)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[UV]](i32), [[UV1]](i32), [[UV2]](i32)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[UV3]](i32), [[UV]](i32), [[UV1]](i32)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x i32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR1]](<3 x i32>)
+ %0:_(i128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(i32), %2:_(i32), %3:_(i32), %4:_(i32) = G_UNMERGE_VALUES %0:_(i128)
+ %9:_(<3 x i32>) = G_BUILD_VECTOR %1:_(i32), %2:_(i32), %3:_(i32)
+ %10:_(<3 x i32>) = G_BUILD_VECTOR %4:_(i32), %1:_(i32), %2:_(i32)
+ $vgpr0_vgpr1_vgpr2 = COPY %9:_(<3 x i32>)
+ $vgpr0_vgpr1_vgpr2 = COPY %10:_(<3 x i32>)
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index ef6699139ca7d..f4b3947616e0e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -414,9 +414,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](s64)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 0
$vgpr0_vgpr1 = COPY %1
@@ -450,9 +449,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV1]](s64)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 64
$vgpr0_vgpr1 = COPY %1
@@ -467,9 +465,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](p0)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = G_EXTRACT %0, 0
$vgpr0_vgpr1 = COPY %1
@@ -503,9 +500,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV1]](p0)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = G_EXTRACT %0, 64
$vgpr0_vgpr1 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index ee93f413566e5..2c35d2c8e94d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -53,14 +53,11 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_flat(i32 %node_ptr, float
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) {
; GFX10-LABEL: image_bvh_intersect_ray_a16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v7
+; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v7
; GFX10-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX10-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; GFX10-NEXT: v_and_or_b32 v5, 0xffff, v5, v9
-; GFX10-NEXT: v_and_or_b32 v6, 0xffff, v6, v10
+; GFX10-NEXT: v_and_or_b32 v6, 0xffff, v6, v9
; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -128,14 +125,11 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_flat(<2 x i32> %node_ptr
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) {
; GFX10-LABEL: image_bvh64_intersect_ray_a16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff, v8
+; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v8
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX10-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; GFX10-NEXT: v_and_or_b32 v6, 0xffff, v6, v10
-; GFX10-NEXT: v_and_or_b32 v7, 0xffff, v7, v11
+; GFX10-NEXT: v_and_or_b32 v7, 0xffff, v7, v10
; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -281,19 +275,17 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0:
; GFX1030-NEXT: v_mov_b32_e32 v13, v0
+; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v7
; GFX1030-NEXT: v_mov_b32_e32 v14, v1
-; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v15, v2
-; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v16, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_mov_b32_e32 v17, v4
-; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16
+; GFX1030-NEXT: v_mov_b32_e32 v18, v5
+; GFX1030-NEXT: v_alignbit_b32 v20, v1, v7, 16
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
-; GFX1030-NEXT: v_and_or_b32 v18, 0xffff, v5, v0
-; GFX1030-NEXT: v_and_or_b32 v19, 0xffff, v6, v1
+; GFX1030-NEXT: v_and_or_b32 v19, 0xffff, v6, v0
; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v9
; GFX1030-NEXT: v_readfirstlane_b32 s5, v10
@@ -323,15 +315,12 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0:
-; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v7
+; GFX1013-NEXT: v_and_b32_e32 v13, 0xffff, v7
; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; GFX1013-NEXT: v_and_or_b32 v5, 0xffff, v5, v13
-; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v14
+; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v13
; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v9
; GFX1013-NEXT: v_readfirstlane_b32 s5, v10
@@ -548,19 +537,17 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
; GFX1030-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0:
; GFX1030-NEXT: v_mov_b32_e32 v14, v0
+; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v15, v1
-; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v9
; GFX1030-NEXT: v_mov_b32_e32 v16, v2
-; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v9
; GFX1030-NEXT: v_mov_b32_e32 v17, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_mov_b32_e32 v18, v4
; GFX1030-NEXT: v_mov_b32_e32 v19, v5
-; GFX1030-NEXT: v_alignbit_b32 v22, v2, v8, 16
-; GFX1030-NEXT: v_and_or_b32 v20, 0xffff, v6, v0
-; GFX1030-NEXT: v_and_or_b32 v21, 0xffff, v7, v1
+; GFX1030-NEXT: v_mov_b32_e32 v20, v6
+; GFX1030-NEXT: v_alignbit_b32 v22, v1, v8, 16
+; GFX1030-NEXT: v_and_or_b32 v21, 0xffff, v7, v0
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v10
@@ -592,15 +579,12 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
;
; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0:
-; GFX1013-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX1013-NEXT: v_and_b32_e32 v15, 0xffff, v8
+; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v8
; GFX1013-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX1013-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX1013-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v14
-; GFX1013-NEXT: v_and_or_b32 v7, 0xffff, v7, v15
+; GFX1013-NEXT: v_and_or_b32 v7, 0xffff, v7, v14
; GFX1013-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v10
; GFX1013-NEXT: v_readfirstlane_b32 s5, v11
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
index c226f7f9289ee..f5bf57222710c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
@@ -749,8 +749,6 @@ define amdgpu_ps i48 @s_orn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1)
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_orn2_v3i16:
@@ -823,8 +821,6 @@ define amdgpu_ps i48 @s_orn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inre
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_orn2_v3i16_commute:
@@ -912,10 +908,7 @@ define amdgpu_ps { i48, i48 } @s_orn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s4, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s4, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -952,19 +945,15 @@ define <3 x i16> @v_orn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
index 43351a8217879..3f98ce371f3fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
@@ -9,9 +9,6 @@ define amdgpu_ps i48 @test_merge_values_sgpr(<3 x i16> inreg %src0, <3 x i16> in
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: test_merge_values_sgpr:
@@ -20,9 +17,6 @@ define amdgpu_ps i48 @test_merge_values_sgpr(<3 x i16> inreg %src0, <3 x i16> in
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX12-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX12-NEXT: ; return to shader part epilog
%not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>
%and = and <3 x i16> %src0, %not.src1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index 173739fa8f35f..6c1e55e364325 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -231,17 +231,14 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
; GFX1013-GISEL-LABEL: image_bvh_intersect_ray_a16:
; GFX1013-GISEL: ; %bb.0: ; %main_body
; GFX1013-GISEL-NEXT: s_and_b32 s8, s8, 0xffff
-; GFX1013-GISEL-NEXT: s_mov_b32 s16, s9
+; GFX1013-GISEL-NEXT: s_and_b32 s6, s6, 0xffff
; GFX1013-GISEL-NEXT: v_alignbit_b32 v0, s8, s7, 16
-; GFX1013-GISEL-NEXT: s_lshr_b32 s9, s5, 16
-; GFX1013-GISEL-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX1013-GISEL-NEXT: s_lshl_b32 s8, s9, 16
-; GFX1013-GISEL-NEXT: s_and_b32 s9, s7, 0xffff
+; GFX1013-GISEL-NEXT: s_and_b32 s8, s7, 0xffff
+; GFX1013-GISEL-NEXT: s_mov_b32 s16, s9
+; GFX1013-GISEL-NEXT: s_lshl_b32 s8, s8, 16
+; GFX1013-GISEL-NEXT: s_mov_b32 s17, s10
; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s7, v0
-; GFX1013-GISEL-NEXT: s_and_b32 s6, s6, 0xffff
-; GFX1013-GISEL-NEXT: s_lshl_b32 s9, s9, 16
-; GFX1013-GISEL-NEXT: s_or_b32 s5, s5, s8
-; GFX1013-GISEL-NEXT: s_or_b32 s6, s6, s9
+; GFX1013-GISEL-NEXT: s_or_b32 s6, s6, s8
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2
@@ -250,7 +247,6 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, s5
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, s6
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, s7
-; GFX1013-GISEL-NEXT: s_mov_b32 s17, s10
; GFX1013-GISEL-NEXT: s_mov_b32 s18, s11
; GFX1013-GISEL-NEXT: s_mov_b32 s19, s12
; GFX1013-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[16:19] a16
@@ -268,16 +264,12 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
; GFX1030-GISEL-LABEL: image_bvh_intersect_ray_a16:
; GFX1030-GISEL: ; %bb.0: ; %main_body
; GFX1030-GISEL-NEXT: s_mov_b32 s16, s9
-; GFX1030-GISEL-NEXT: s_lshr_b32 s9, s5, 16
-; GFX1030-GISEL-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX1030-GISEL-NEXT: s_lshl_b32 s9, s9, 16
-; GFX1030-GISEL-NEXT: s_and_b32 s6, s6, 0xffff
-; GFX1030-GISEL-NEXT: s_or_b32 s5, s5, s9
; GFX1030-GISEL-NEXT: s_and_b32 s9, s7, 0xffff
-; GFX1030-GISEL-NEXT: s_and_b32 s8, s8, 0xffff
+; GFX1030-GISEL-NEXT: s_and_b32 s6, s6, 0xffff
; GFX1030-GISEL-NEXT: s_lshl_b32 s9, s9, 16
-; GFX1030-GISEL-NEXT: v_alignbit_b32 v7, s8, s7, 16
+; GFX1030-GISEL-NEXT: s_and_b32 s8, s8, 0xffff
; GFX1030-GISEL-NEXT: s_or_b32 s6, s6, s9
+; GFX1030-GISEL-NEXT: v_alignbit_b32 v7, s8, s7, 16
; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2
@@ -533,17 +525,14 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
; GFX1013-GISEL-LABEL: image_bvh64_intersect_ray_a16:
; GFX1013-GISEL: ; %bb.0: ; %main_body
; GFX1013-GISEL-NEXT: s_and_b32 s9, s9, 0xffff
-; GFX1013-GISEL-NEXT: s_mov_b32 s16, s10
+; GFX1013-GISEL-NEXT: s_and_b32 s7, s7, 0xffff
; GFX1013-GISEL-NEXT: v_alignbit_b32 v0, s9, s8, 16
-; GFX1013-GISEL-NEXT: s_lshr_b32 s10, s6, 16
-; GFX1013-GISEL-NEXT: s_and_b32 s6, s6, 0xffff
-; GFX1013-GISEL-NEXT: s_lshl_b32 s9, s10, 16
-; GFX1013-GISEL-NEXT: s_and_b32 s10, s8, 0xffff
+; GFX1013-GISEL-NEXT: s_and_b32 s9, s8, 0xffff
+; GFX1013-GISEL-NEXT: s_mov_b32 s16, s10
+; GFX1013-GISEL-NEXT: s_lshl_b32 s9, s9, 16
+; GFX1013-GISEL-NEXT: s_mov_b32 s17, s11
; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s8, v0
-; GFX1013-GISEL-NEXT: s_and_b32 s7, s7, 0xffff
-; GFX1013-GISEL-NEXT: s_lshl_b32 s10, s10, 16
-; GFX1013-GISEL-NEXT: s_or_b32 s6, s6, s9
-; GFX1013-GISEL-NEXT: s_or_b32 s7, s7, s10
+; GFX1013-GISEL-NEXT: s_or_b32 s7, s7, s9
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2
@@ -553,7 +542,6 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, s6
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, s7
; GFX1013-GISEL-NEXT: v_mov_b32_e32 v8, s8
-; GFX1013-GISEL-NEXT: s_mov_b32 s17, s11
; GFX1013-GISEL-NEXT: s_mov_b32 s18, s12
; GFX1013-GISEL-NEXT: s_mov_b32 s19, s13
; GFX1013-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[16:19] a16
@@ -571,16 +559,12 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
; GFX1030-GISEL-LABEL: image_bvh64_intersect_ray_a16:
; GFX1030-GISEL: ; %bb.0: ; %main_body
; GFX1030-GISEL-NEXT: s_mov_b32 s16, s10
-; GFX1030-GISEL-NEXT: s_lshr_b32 s10, s6, 16
-; GFX1030-GISEL-NEXT: s_and_b32 s6, s6, 0xffff
-; GFX1030-GISEL-NEXT: s_lshl_b32 s10, s10, 16
-; GFX1030-GISEL-NEXT: s_and_b32 s7, s7, 0xffff
-; GFX1030-GISEL-NEXT: s_or_b32 s6, s6, s10
; GFX1030-GISEL-NEXT: s_and_b32 s10, s8, 0xffff
-; GFX1030-GISEL-NEXT: s_and_b32 s9, s9, 0xffff
+; GFX1030-GISEL-NEXT: s_and_b32 s7, s7, 0xffff
; GFX1030-GISEL-NEXT: s_lshl_b32 s10, s10, 16
-; GFX1030-GISEL-NEXT: v_alignbit_b32 v8, s9, s8, 16
+; GFX1030-GISEL-NEXT: s_and_b32 s9, s9, 0xffff
; GFX1030-GISEL-NEXT: s_or_b32 s7, s7, s10
+; GFX1030-GISEL-NEXT: v_alignbit_b32 v8, s9, s8, 16
; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2
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