[llvm] [SDAG] Add basic type legalization for experimental.vector.match (PR #213344)

[Benjamin Maxwell via llvm-commits]

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@@ -6482,23 +6494,32 @@ SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
                       DAG.getTargetConstant(ImmAddend, DL, MVT::i32)});
 }
 
-SDValue LowerVectorMatch(SDValue Op, SelectionDAG &DAG) {
+SDValue LowerVectorMatch(SDValue Op, SelectionDAG &DAG,
+                         const AArch64Subtarget *Subtarget) {
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MacDue wrote:

no, removed :+1: 

https://github.com/llvm/llvm-project/pull/213344