[llvm] AMDGPU/GlobalISel: Legalize G_SCMP and G_UCMP (PR #213896)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 03:13:35 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/213896
None
>From 2f568f4a01af5aa7bc5d9dee879b385b129910fe Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Tue, 4 Aug 2026 12:12:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Legalize G_SCMP and G_UCMP
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +
llvm/test/CodeGen/AMDGPU/scmp-ucmp.ll | 606 ++++++++++++++++++
2 files changed, 608 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/scmp-ucmp.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index f71d88bb68783..7931c9f7f9e02 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1335,6 +1335,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0)
.legalIf(all(typeInSet(0, {S1, S32}), isPointer(1)));
+ getActionDefinitionsBuilder({G_SCMP, G_UCMP}).lower();
+
auto &FCmpBuilder =
getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct(
{S1}, ST.has16BitInsts() ? FPTypes16 : FPTypesBase);
diff --git a/llvm/test/CodeGen/AMDGPU/scmp-ucmp.ll b/llvm/test/CodeGen/AMDGPU/scmp-ucmp.ll
new file mode 100644
index 0000000000000..816644a6502eb
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/scmp-ucmp.ll
@@ -0,0 +1,606 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+
+define i32 @scmp_i64(i64 %a, i64 %b) {
+; GFX12-SDAG-LABEL: scmp_i64:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: scmp_i64:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v4, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.scmp.i32.i64(i64 %a, i64 %b)
+ ret i32 %r
+}
+
+define i32 @scmp_i32(i32 %a, i32 %b) {
+; GFX12-SDAG-LABEL: scmp_i32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: scmp_i32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.scmp.i32.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i32 @scmp_i16(i16 %a, i16 %b) {
+; GFX12-SDAG-LABEL: scmp_i16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: scmp_i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.scmp.i32.i16(i16 %a, i16 %b)
+ ret i32 %r
+}
+
+define i32 @scmp_i8(i8 %a, i8 %b) {
+; GFX12-SDAG-LABEL: scmp_i8:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: scmp_i8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.scmp.i32.i8(i8 %a, i8 %b)
+ ret i32 %r
+}
+
+define <2 x i32> @scmp_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; GFX12-SDAG-LABEL: scmp_v2i16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v1, -1, v5, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: scmp_v2i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.h, v1.h
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i16_e32 vcc_lo, v0.h, v1.h
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v1, v3, v1
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call <2 x i32> @llvm.scmp.v2i32.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i32> %r
+}
+
+define <4 x i32> @scmp_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; GFX12-SDAG-LABEL: scmp_v4i8:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-NEXT: v_bfe_i32 v8, v3, 0, 8
+; GFX12-SDAG-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v3.l, v4.l
+; GFX12-SDAG-NEXT: v_bfe_i32 v4, v6, 0, 8
+; GFX12-SDAG-NEXT: v_bfe_i32 v9, v2, 0, 8
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v2.l, v5.l
+; GFX12-SDAG-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v3.l
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v5.l, v8.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.l, v3.l
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v3.l, v9.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v6, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v1.l, v2.l
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v6.l, v7.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v3.l, v4.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v5.l, v6.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v1.l, v2.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v1, -1, v7, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v3.l, v4.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v2, -1, v8, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v5.l, v6.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v3, -1, v9, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: scmp_v4i8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v6, v6, 0, 8
+; GFX12-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v4
+; GFX12-GISEL-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX12-GISEL-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, v1, v5
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, v2, v6
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, v3, v7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, v1, v5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v8, v0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, v2, v6
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v1, v9, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, v3, v7
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v2, v10, v2
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v3, v11, v3
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call <4 x i32> @llvm.scmp.v4i32.v4i8(<4 x i8> %a, <4 x i8> %b)
+ ret <4 x i32> %r
+}
+
+define i32 @ucmp_i64(i64 %a, i64 %b) {
+; GFX12-SDAG-LABEL: ucmp_i64:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: ucmp_i64:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v4, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.ucmp.i32.i64(i64 %a, i64 %b)
+ ret i32 %r
+}
+
+define i32 @ucmp_i32(i32 %a, i32 %b) {
+; GFX12-SDAG-LABEL: ucmp_i32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: ucmp_i32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.ucmp.i32.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i32 @ucmp_i16(i16 %a, i16 %b) {
+; GFX12-SDAG-LABEL: ucmp_i16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: ucmp_i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.ucmp.i32.i16(i16 %a, i16 %b)
+ ret i32 %r
+}
+
+define i32 @ucmp_i8(i8 %a, i8 %b) {
+; GFX12-SDAG-LABEL: ucmp_i8:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX12-SDAG-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v0.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.l, v0.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v1, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: ucmp_i8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.ucmp.i32.i8(i8 %a, i8 %b)
+ ret i32 %r
+}
+
+define <2 x i32> @ucmp_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; GFX12-SDAG-LABEL: ucmp_v2i16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v1, -1, v5, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: ucmp_v2i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.h, v1.h
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u16_e32 vcc_lo, v0.l, v1.l
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u16_e32 vcc_lo, v0.h, v1.h
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v2, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v1, v3, v1
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call <2 x i32> @llvm.ucmp.v2i32.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i32> %r
+}
+
+define <4 x i32> @ucmp_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; GFX12-SDAG-LABEL: ucmp_v4i8:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_and_b16 v0.h, 0xff, v4.l
+; GFX12-SDAG-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-NEXT: v_and_b16 v1.h, 0xff, v5.l
+; GFX12-SDAG-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-NEXT: v_and_b16 v2.h, 0xff, v6.l
+; GFX12-SDAG-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v0.h
+; GFX12-SDAG-NEXT: v_and_b16 v3.h, 0xff, v7.l
+; GFX12-SDAG-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.l, v0.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v1.l, v1.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v2.l, v2.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v3.l, v3.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v1.l, v1.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v1, -1, v4, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v2.l, v2.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v2, -1, v5, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v3.l, v3.h
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc_lo
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: ucmp_v4i8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-GISEL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX12-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-GISEL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX12-GISEL-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v4
+; GFX12-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX12-GISEL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_u32_e32 vcc_lo, v1, v5
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v6
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_gt_u32_e32 vcc_lo, v3, v7
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, v1, v5
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v8, v0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v6
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v1, v9, v1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, v3, v7
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v2, v10, v2
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v3, v11, v3
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %r = call <4 x i32> @llvm.ucmp.v4i32.v4i8(<4 x i8> %a, <4 x i8> %b)
+ ret <4 x i32> %r
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12: {{.*}}
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