[llvm] [SDAG] Add basic type legalization for experimental.vector.match (PR #213344)

[Luke Lau via llvm-commits]

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@@ -1038,6 +1038,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       if (!isTypeLegal(VT))
         continue;
 
+      setOperationAction(ISD::VECTOR_MATCH, VT, Expand);
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lukel97 wrote:

Can we just make expand the default in `initActions`

https://github.com/llvm/llvm-project/pull/213344