[llvm] [AArch64] Add ReadAdvance for AESE/AESMC and AESD/AESIMC pairs (PR #213652)

[Andrew Savonichev via llvm-commits]

asavonic wrote:

> My understanding is that there is a difference between "fusion" and "forwarding", and aes instruction fuse together. It means that (I believe) the instruction need to be back-to-back in the instruction stream so the frontend of the CPU can fuse them. It does mean that if there is an instruction between the two then they will not fuse (I believe), and it can be dependant on the regs used, but if they do fuse there is a single uOp.

Right, that matches my understanding as well.
I originally made an MCA-specific fix that handled "back-to-back" fusion, but then I found that V1 schedule model [uses ReadAdvance](https://github.com/llvm/llvm-project/blob/a44620dad09537ba10d22e241c6f2ba011c65bea/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td#L1400).

> We control this in the compiler with MacroFusion and FeatureFuseAES. It doesn't say what it fuses into, but is there a way to either marry the two or get the scheduling model info more correct?

Thank you! I'll look at how to make this more accurate.


https://github.com/llvm/llvm-project/pull/213652