[llvm] 24d2a96 - GlobalISel: Fix floating point unmerge lowering (#213703)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 01:49:40 PDT 2026
Author: Petar Avramovic
Date: 2026-08-04T10:49:35+02:00
New Revision: 24d2a96518ced6d86219d0aa2b9ad7326271fd8e
URL: https://github.com/llvm/llvm-project/commit/24d2a96518ced6d86219d0aa2b9ad7326271fd8e
DIFF: https://github.com/llvm/llvm-project/commit/24d2a96518ced6d86219d0aa2b9ad7326271fd8e.diff
LOG: GlobalISel: Fix floating point unmerge lowering (#213703)
Bitcast to integer and use integer type for bit twiddling.
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 65d71a481dbdc..87a3ea5bdea59 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2141,11 +2141,15 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Register LegalizerHelper::coerceToInteger(Register Val) {
LLT Ty = MRI.getType(Val);
- if (Ty.isScalar())
+ if (Ty.isScalar() && !Ty.isFloat())
return Val;
const DataLayout &DL = MIRBuilder.getDataLayout();
LLT NewTy = LLT::integer(Ty.getSizeInBits());
+
+ if (Ty.isFloat())
+ return MIRBuilder.buildBitcast(NewTy, Val).getReg(0);
+
if (Ty.isPointer()) {
if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
return Register();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index 6eebf814f4fd0..bff28f14bbfa5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define float @dyn_extract_v8f32_const_s_v(i32 %sel) {
; GCN-LABEL: dyn_extract_v8f32_const_s_v:
@@ -4672,24 +4672,352 @@ define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) {
define amdgpu_gs void @extract_v32i1_bitcast_f32(float %x, ptr addrspace(1) %out) {
; GPRIDX-LABEL: extract_v32i1_bitcast_f32:
; GPRIDX: ; %bb.0:
+; GPRIDX-NEXT: v_bfe_u32 v4, v0, 1, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v4, 1, v4
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 2, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 3, 1
+; GPRIDX-NEXT: v_and_or_b32 v4, v0, 1, v4
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 2, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 3, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 4, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 5, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 4, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 5, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 6, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 7, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 6, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 7, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 8, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 9, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 9, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 10, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 11, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 10, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 11, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 12, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 13, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 12, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 13, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 14, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 15, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 14, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 15, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 17, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 17, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 18, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 19, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 18, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 19, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 20, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 21, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 20, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 21, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 22, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 23, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 22, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 23, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 24, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 25, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 25, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 26, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 27, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 26, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 27, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 28, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 29, 1
+; GPRIDX-NEXT: v_lshrrev_b32_e32 v3, 31, v0
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 28, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 29, v6
+; GPRIDX-NEXT: v_bfe_u32 v0, v0, 30, 1
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v0, 30, v0
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v3, 31, v3
+; GPRIDX-NEXT: v_or3_b32 v0, v4, v0, v3
; GPRIDX-NEXT: v_and_b32_e32 v0, 1, v0
; GPRIDX-NEXT: global_store_dword v[1:2], v0, off
; GPRIDX-NEXT: s_endpgm
;
; MOVREL-LABEL: extract_v32i1_bitcast_f32:
; MOVREL: ; %bb.0:
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 1, 1
+; MOVREL-NEXT: v_and_b32_e32 v4, 1, v0
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 1, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 2, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 2, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 3, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 4, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 4, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 5, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 6, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 6, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 7, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 7, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 8, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 9, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 9, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 10, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 10, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 11, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 11, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 12, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 12, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 13, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 13, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 14, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 14, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 15, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 15, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 16, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 17, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 17, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 18, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 18, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 19, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 19, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 20, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 20, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 21, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 21, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 22, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 22, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 23, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 23, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 24, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 25, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 25, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 26, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 26, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 27, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 27, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 28, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 28, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 29, 1
+; MOVREL-NEXT: v_lshrrev_b32_e32 v3, 31, v0
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 29, v5
+; MOVREL-NEXT: v_bfe_u32 v0, v0, 30, 1
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_lshlrev_b32_e32 v0, 30, v0
+; MOVREL-NEXT: v_or_b32_e32 v0, v4, v0
+; MOVREL-NEXT: v_lshlrev_b32_e32 v3, 31, v3
+; MOVREL-NEXT: v_or_b32_e32 v0, v0, v3
; MOVREL-NEXT: v_and_b32_e32 v0, 1, v0
; MOVREL-NEXT: flat_store_dword v[1:2], v0
; MOVREL-NEXT: s_endpgm
;
; GFX10-LABEL: extract_v32i1_bitcast_f32:
; GFX10: ; %bb.0:
+; GFX10-NEXT: v_bfe_u32 v3, v0, 1, 1
+; GFX10-NEXT: v_bfe_u32 v4, v0, 2, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 3, 1
+; GFX10-NEXT: v_bfe_u32 v6, v0, 4, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 5, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 2, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; GFX10-NEXT: v_bfe_u32 v8, v0, 6, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 7, 1
+; GFX10-NEXT: v_and_or_b32 v3, v0, 1, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 4, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 5, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 6, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 7, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 9, 1
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 10, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 11, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 9, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 12, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 13, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 10, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 11, v7
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 14, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 15, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 12, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 13, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 17, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 14, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 15, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 18, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 19, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 17, v7
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 20, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 21, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 18, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 19, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 22, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 23, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 20, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 21, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 24, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 25, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 22, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 23, v7
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 26, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 27, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 25, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 28, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 29, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 26, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 27, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 30, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 28, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 29, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 30, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v0
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_or3_b32 v0, v3, v4, v0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: global_store_dword v[1:2], v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: extract_v32i1_bitcast_f32:
; GFX11: ; %bb.0:
+; GFX11-NEXT: v_bfe_u32 v3, v0, 1, 1
+; GFX11-NEXT: v_bfe_u32 v4, v0, 2, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 3, 1
+; GFX11-NEXT: v_bfe_u32 v6, v0, 4, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 5, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 2, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; GFX11-NEXT: v_bfe_u32 v8, v0, 6, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 7, 1
+; GFX11-NEXT: v_and_or_b32 v3, v0, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 4, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 5, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 6, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 7, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 8, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 9, 1
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 10, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 11, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 9, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 12, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 13, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 10, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 11, v7
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 14, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 15, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 12, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 13, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 17, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 14, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 15, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 18, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 19, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 17, v7
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 20, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 21, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 18, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 19, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 22, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 23, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 20, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 21, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 24, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 25, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 22, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 23, v7
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 26, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 27, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 25, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 28, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 29, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 26, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 27, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 30, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 28, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 29, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 31, v0
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 30, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 31, v0
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_or3_b32 v0, v3, v4, v0
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: global_store_b32 v[1:2], v0, off
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index bba06a67d305f..ea6d7739874bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -1443,227 +1443,165 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C]](f32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C1]](f32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C2]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C3]](f32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C4]](f32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C5]](f32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C6]](f32)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C7]](f32)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(f32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C8]](f32)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(f32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C9]](f32)
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(f32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C10]](f32)
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(f32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C11]](f32)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(f32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C12]](f32)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(f32) = G_CONSTANT i32 14
- ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C13]](f32)
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(f32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[LSHR14:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C14]](f32)
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(f32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[LSHR15:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C15]](f32)
- ; CHECK-NEXT: [[C16:%[0-9]+]]:_(f32) = G_CONSTANT i32 17
- ; CHECK-NEXT: [[LSHR16:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C16]](f32)
- ; CHECK-NEXT: [[C17:%[0-9]+]]:_(f32) = G_CONSTANT i32 18
- ; CHECK-NEXT: [[LSHR17:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C17]](f32)
- ; CHECK-NEXT: [[C18:%[0-9]+]]:_(f32) = G_CONSTANT i32 19
- ; CHECK-NEXT: [[LSHR18:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C18]](f32)
- ; CHECK-NEXT: [[C19:%[0-9]+]]:_(f32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[LSHR19:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C19]](f32)
- ; CHECK-NEXT: [[C20:%[0-9]+]]:_(f32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[LSHR20:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C20]](f32)
- ; CHECK-NEXT: [[C21:%[0-9]+]]:_(f32) = G_CONSTANT i32 22
- ; CHECK-NEXT: [[LSHR21:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C21]](f32)
- ; CHECK-NEXT: [[C22:%[0-9]+]]:_(f32) = G_CONSTANT i32 23
- ; CHECK-NEXT: [[LSHR22:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C22]](f32)
- ; CHECK-NEXT: [[C23:%[0-9]+]]:_(f32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[LSHR23:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C23]](f32)
- ; CHECK-NEXT: [[C24:%[0-9]+]]:_(f32) = G_CONSTANT i32 25
- ; CHECK-NEXT: [[LSHR24:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C24]](f32)
- ; CHECK-NEXT: [[C25:%[0-9]+]]:_(f32) = G_CONSTANT i32 26
- ; CHECK-NEXT: [[LSHR25:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C25]](f32)
- ; CHECK-NEXT: [[C26:%[0-9]+]]:_(f32) = G_CONSTANT i32 27
- ; CHECK-NEXT: [[LSHR26:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C26]](f32)
- ; CHECK-NEXT: [[C27:%[0-9]+]]:_(f32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[LSHR27:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C27]](f32)
- ; CHECK-NEXT: [[C28:%[0-9]+]]:_(f32) = G_CONSTANT i32 29
- ; CHECK-NEXT: [[LSHR28:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C28]](f32)
- ; CHECK-NEXT: [[C29:%[0-9]+]]:_(f32) = G_CONSTANT i32 30
- ; CHECK-NEXT: [[LSHR29:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C29]](f32)
- ; CHECK-NEXT: [[C30:%[0-9]+]]:_(f32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[LSHR30:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C30]](f32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C2]](i32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C3]](i32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C4]](i32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C5]](i32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C6]](i32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C7]](i32)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C8]](i32)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C9]](i32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C10]](i32)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C11]](i32)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C12]](i32)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 14
+ ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C13]](i32)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[LSHR14:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C14]](i32)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[LSHR15:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C15]](i32)
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 17
+ ; CHECK-NEXT: [[LSHR16:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C16]](i32)
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 18
+ ; CHECK-NEXT: [[LSHR17:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C17]](i32)
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 19
+ ; CHECK-NEXT: [[LSHR18:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C18]](i32)
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[LSHR19:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C19]](i32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[LSHR20:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C20]](i32)
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 22
+ ; CHECK-NEXT: [[LSHR21:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C21]](i32)
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(i32) = G_CONSTANT i32 23
+ ; CHECK-NEXT: [[LSHR22:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C22]](i32)
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[LSHR23:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C23]](i32)
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(i32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[LSHR24:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C24]](i32)
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(i32) = G_CONSTANT i32 26
+ ; CHECK-NEXT: [[LSHR25:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C25]](i32)
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(i32) = G_CONSTANT i32 27
+ ; CHECK-NEXT: [[LSHR26:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C26]](i32)
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[LSHR27:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C27]](i32)
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(i32) = G_CONSTANT i32 29
+ ; CHECK-NEXT: [[LSHR28:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C28]](i32)
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+ ; CHECK-NEXT: [[LSHR29:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C29]](i32)
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(i32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[LSHR30:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C30]](i32)
; CHECK-NEXT: [[C31:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](f32)
- ; CHECK-NEXT: [[C32:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C32]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[LSHR]](f32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY2]], [[C32]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C32]](i32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[LSHR1]](f32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY3]], [[C32]]
- ; CHECK-NEXT: [[C33:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C33]](i32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C1]](i32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY [[LSHR2]](f32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[COPY4]], [[C32]]
- ; CHECK-NEXT: [[C34:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C34]](i32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[LSHR2]], [[C]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C2]](i32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY [[LSHR3]](f32)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[COPY5]], [[C32]]
- ; CHECK-NEXT: [[C35:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C35]](i32)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR3]], [[C]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C3]](i32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY [[LSHR4]](f32)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[COPY6]], [[C32]]
- ; CHECK-NEXT: [[C36:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C36]](i32)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C4]](i32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY [[LSHR5]](f32)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[COPY7]], [[C32]]
- ; CHECK-NEXT: [[C37:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C37]](i32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[LSHR5]], [[C]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C5]](i32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY [[LSHR6]](f32)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[COPY8]], [[C32]]
- ; CHECK-NEXT: [[C38:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C38]](i32)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[LSHR6]], [[C]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C6]](i32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY [[LSHR7]](f32)
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[COPY9]], [[C32]]
- ; CHECK-NEXT: [[C39:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND8]], [[C39]](i32)
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[LSHR7]], [[C]]
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND8]], [[C7]](i32)
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY [[LSHR8]](f32)
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[COPY10]], [[C32]]
- ; CHECK-NEXT: [[C40:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[AND9]], [[C40]](i32)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[LSHR8]], [[C]]
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[AND9]], [[C8]](i32)
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(i32) = G_OR [[OR7]], [[SHL8]]
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY [[LSHR9]](f32)
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[COPY11]], [[C32]]
- ; CHECK-NEXT: [[C41:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[AND10]], [[C41]](i32)
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[LSHR9]], [[C]]
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[AND10]], [[C9]](i32)
; CHECK-NEXT: [[OR9:%[0-9]+]]:_(i32) = G_OR [[OR8]], [[SHL9]]
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY [[LSHR10]](f32)
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(i32) = G_AND [[COPY12]], [[C32]]
- ; CHECK-NEXT: [[C42:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C42]](i32)
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(i32) = G_AND [[LSHR10]], [[C]]
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C10]](i32)
; CHECK-NEXT: [[OR10:%[0-9]+]]:_(i32) = G_OR [[OR9]], [[SHL10]]
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY [[LSHR11]](f32)
- ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(i32) = G_AND [[COPY13]], [[C32]]
- ; CHECK-NEXT: [[C43:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(i32) = G_SHL [[AND12]], [[C43]](i32)
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(i32) = G_AND [[LSHR11]], [[C]]
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(i32) = G_SHL [[AND12]], [[C11]](i32)
; CHECK-NEXT: [[OR11:%[0-9]+]]:_(i32) = G_OR [[OR10]], [[SHL11]]
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY [[LSHR12]](f32)
- ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(i32) = G_AND [[COPY14]], [[C32]]
- ; CHECK-NEXT: [[C44:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(i32) = G_SHL [[AND13]], [[C44]](i32)
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(i32) = G_AND [[LSHR12]], [[C]]
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(i32) = G_SHL [[AND13]], [[C12]](i32)
; CHECK-NEXT: [[OR12:%[0-9]+]]:_(i32) = G_OR [[OR11]], [[SHL12]]
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[LSHR13]](f32)
- ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(i32) = G_AND [[COPY15]], [[C32]]
- ; CHECK-NEXT: [[C45:%[0-9]+]]:_(i32) = G_CONSTANT i32 14
- ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(i32) = G_SHL [[AND14]], [[C45]](i32)
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(i32) = G_AND [[LSHR13]], [[C]]
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(i32) = G_SHL [[AND14]], [[C13]](i32)
; CHECK-NEXT: [[OR13:%[0-9]+]]:_(i32) = G_OR [[OR12]], [[SHL13]]
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[LSHR14]](f32)
- ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(i32) = G_AND [[COPY16]], [[C32]]
- ; CHECK-NEXT: [[C46:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(i32) = G_SHL [[AND15]], [[C46]](i32)
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(i32) = G_AND [[LSHR14]], [[C]]
+ ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(i32) = G_SHL [[AND15]], [[C14]](i32)
; CHECK-NEXT: [[OR14:%[0-9]+]]:_(i32) = G_OR [[OR13]], [[SHL14]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[LSHR15]](f32)
- ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(i32) = G_AND [[COPY17]], [[C32]]
- ; CHECK-NEXT: [[C47:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(i32) = G_SHL [[AND16]], [[C47]](i32)
+ ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(i32) = G_AND [[LSHR15]], [[C]]
+ ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(i32) = G_SHL [[AND16]], [[C15]](i32)
; CHECK-NEXT: [[OR15:%[0-9]+]]:_(i32) = G_OR [[OR14]], [[SHL15]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[LSHR16]](f32)
- ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(i32) = G_AND [[COPY18]], [[C32]]
- ; CHECK-NEXT: [[C48:%[0-9]+]]:_(i32) = G_CONSTANT i32 17
- ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(i32) = G_SHL [[AND17]], [[C48]](i32)
+ ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(i32) = G_AND [[LSHR16]], [[C]]
+ ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(i32) = G_SHL [[AND17]], [[C16]](i32)
; CHECK-NEXT: [[OR16:%[0-9]+]]:_(i32) = G_OR [[OR15]], [[SHL16]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[LSHR17]](f32)
- ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(i32) = G_AND [[COPY19]], [[C32]]
- ; CHECK-NEXT: [[C49:%[0-9]+]]:_(i32) = G_CONSTANT i32 18
- ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(i32) = G_SHL [[AND18]], [[C49]](i32)
+ ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(i32) = G_AND [[LSHR17]], [[C]]
+ ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(i32) = G_SHL [[AND18]], [[C17]](i32)
; CHECK-NEXT: [[OR17:%[0-9]+]]:_(i32) = G_OR [[OR16]], [[SHL17]]
- ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY [[LSHR18]](f32)
- ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(i32) = G_AND [[COPY20]], [[C32]]
- ; CHECK-NEXT: [[C50:%[0-9]+]]:_(i32) = G_CONSTANT i32 19
- ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(i32) = G_SHL [[AND19]], [[C50]](i32)
+ ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(i32) = G_AND [[LSHR18]], [[C]]
+ ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(i32) = G_SHL [[AND19]], [[C18]](i32)
; CHECK-NEXT: [[OR18:%[0-9]+]]:_(i32) = G_OR [[OR17]], [[SHL18]]
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY [[LSHR19]](f32)
- ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(i32) = G_AND [[COPY21]], [[C32]]
- ; CHECK-NEXT: [[C51:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(i32) = G_SHL [[AND20]], [[C51]](i32)
+ ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(i32) = G_AND [[LSHR19]], [[C]]
+ ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(i32) = G_SHL [[AND20]], [[C19]](i32)
; CHECK-NEXT: [[OR19:%[0-9]+]]:_(i32) = G_OR [[OR18]], [[SHL19]]
- ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY [[LSHR20]](f32)
- ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(i32) = G_AND [[COPY22]], [[C32]]
- ; CHECK-NEXT: [[C52:%[0-9]+]]:_(i32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(i32) = G_SHL [[AND21]], [[C52]](i32)
+ ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(i32) = G_AND [[LSHR20]], [[C]]
+ ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(i32) = G_SHL [[AND21]], [[C20]](i32)
; CHECK-NEXT: [[OR20:%[0-9]+]]:_(i32) = G_OR [[OR19]], [[SHL20]]
- ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(i32) = COPY [[LSHR21]](f32)
- ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(i32) = G_AND [[COPY23]], [[C32]]
- ; CHECK-NEXT: [[C53:%[0-9]+]]:_(i32) = G_CONSTANT i32 22
- ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(i32) = G_SHL [[AND22]], [[C53]](i32)
+ ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(i32) = G_AND [[LSHR21]], [[C]]
+ ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(i32) = G_SHL [[AND22]], [[C21]](i32)
; CHECK-NEXT: [[OR21:%[0-9]+]]:_(i32) = G_OR [[OR20]], [[SHL21]]
- ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(i32) = COPY [[LSHR22]](f32)
- ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(i32) = G_AND [[COPY24]], [[C32]]
- ; CHECK-NEXT: [[C54:%[0-9]+]]:_(i32) = G_CONSTANT i32 23
- ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(i32) = G_SHL [[AND23]], [[C54]](i32)
+ ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(i32) = G_AND [[LSHR22]], [[C]]
+ ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(i32) = G_SHL [[AND23]], [[C22]](i32)
; CHECK-NEXT: [[OR22:%[0-9]+]]:_(i32) = G_OR [[OR21]], [[SHL22]]
- ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(i32) = COPY [[LSHR23]](f32)
- ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(i32) = G_AND [[COPY25]], [[C32]]
- ; CHECK-NEXT: [[C55:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(i32) = G_SHL [[AND24]], [[C55]](i32)
+ ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(i32) = G_AND [[LSHR23]], [[C]]
+ ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(i32) = G_SHL [[AND24]], [[C23]](i32)
; CHECK-NEXT: [[OR23:%[0-9]+]]:_(i32) = G_OR [[OR22]], [[SHL23]]
- ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(i32) = COPY [[LSHR24]](f32)
- ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(i32) = G_AND [[COPY26]], [[C32]]
- ; CHECK-NEXT: [[C56:%[0-9]+]]:_(i32) = G_CONSTANT i32 25
- ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(i32) = G_SHL [[AND25]], [[C56]](i32)
+ ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(i32) = G_AND [[LSHR24]], [[C]]
+ ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(i32) = G_SHL [[AND25]], [[C24]](i32)
; CHECK-NEXT: [[OR24:%[0-9]+]]:_(i32) = G_OR [[OR23]], [[SHL24]]
- ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(i32) = COPY [[LSHR25]](f32)
- ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(i32) = G_AND [[COPY27]], [[C32]]
- ; CHECK-NEXT: [[C57:%[0-9]+]]:_(i32) = G_CONSTANT i32 26
- ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(i32) = G_SHL [[AND26]], [[C57]](i32)
+ ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(i32) = G_AND [[LSHR25]], [[C]]
+ ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(i32) = G_SHL [[AND26]], [[C25]](i32)
; CHECK-NEXT: [[OR25:%[0-9]+]]:_(i32) = G_OR [[OR24]], [[SHL25]]
- ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(i32) = COPY [[LSHR26]](f32)
- ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(i32) = G_AND [[COPY28]], [[C32]]
- ; CHECK-NEXT: [[C58:%[0-9]+]]:_(i32) = G_CONSTANT i32 27
- ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(i32) = G_SHL [[AND27]], [[C58]](i32)
+ ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(i32) = G_AND [[LSHR26]], [[C]]
+ ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(i32) = G_SHL [[AND27]], [[C26]](i32)
; CHECK-NEXT: [[OR26:%[0-9]+]]:_(i32) = G_OR [[OR25]], [[SHL26]]
- ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(i32) = COPY [[LSHR27]](f32)
- ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(i32) = G_AND [[COPY29]], [[C32]]
- ; CHECK-NEXT: [[C59:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(i32) = G_SHL [[AND28]], [[C59]](i32)
+ ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(i32) = G_AND [[LSHR27]], [[C]]
+ ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(i32) = G_SHL [[AND28]], [[C27]](i32)
; CHECK-NEXT: [[OR27:%[0-9]+]]:_(i32) = G_OR [[OR26]], [[SHL27]]
- ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(i32) = COPY [[LSHR28]](f32)
- ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(i32) = G_AND [[COPY30]], [[C32]]
- ; CHECK-NEXT: [[C60:%[0-9]+]]:_(i32) = G_CONSTANT i32 29
- ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(i32) = G_SHL [[AND29]], [[C60]](i32)
+ ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(i32) = G_AND [[LSHR28]], [[C]]
+ ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(i32) = G_SHL [[AND29]], [[C28]](i32)
; CHECK-NEXT: [[OR28:%[0-9]+]]:_(i32) = G_OR [[OR27]], [[SHL28]]
- ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(i32) = COPY [[LSHR29]](f32)
- ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(i32) = G_AND [[COPY31]], [[C32]]
- ; CHECK-NEXT: [[C61:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
- ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(i32) = G_SHL [[AND30]], [[C61]](i32)
+ ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(i32) = G_AND [[LSHR29]], [[C]]
+ ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(i32) = G_SHL [[AND30]], [[C29]](i32)
; CHECK-NEXT: [[OR29:%[0-9]+]]:_(i32) = G_OR [[OR28]], [[SHL29]]
- ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(i32) = COPY [[LSHR30]](f32)
- ; CHECK-NEXT: [[C62:%[0-9]+]]:_(i32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(i32) = G_SHL [[COPY32]], [[C62]](i32)
+ ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(i32) = G_SHL [[LSHR30]], [[C30]](i32)
; CHECK-NEXT: [[OR30:%[0-9]+]]:_(i32) = G_OR [[OR29]], [[SHL30]]
; CHECK-NEXT: [[LSHR31:%[0-9]+]]:_(i32) = G_LSHR [[OR30]], [[C31]](i32)
- ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(i32) = G_AND [[LSHR31]], [[C32]]
+ ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(i32) = G_AND [[LSHR31]], [[C]]
; CHECK-NEXT: $vgpr0 = COPY [[AND31]](i32)
%0:_(f32) = COPY $vgpr0
%1:_(<32 x i1>) = G_BITCAST %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
index 80806ed66c097..a9cc6d4329eff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
@@ -1115,10 +1115,11 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](f32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C]](f32)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](f32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](f32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32)
; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](i16)
; CHECK-NEXT: $vgpr1 = COPY [[TRUNC1]](i16)
%0:_(f32) = COPY $vgpr0
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