[llvm] 27e6d83 - AMDGPU/GlobalISel: Precommit tests for upcoming bug fix (#213701)

[via llvm-commits]

Author: Petar Avramovic
Date: 2026-08-04T10:35:30+02:00
New Revision: 27e6d832069729d75a76e7776737bf4477dde5a8

URL: https://github.com/llvm/llvm-project/commit/27e6d832069729d75a76e7776737bf4477dde5a8
DIFF: https://github.com/llvm/llvm-project/commit/27e6d832069729d75a76e7776737bf4477dde5a8.diff

LOG: AMDGPU/GlobalISel: Precommit tests for upcoming bug fix (#213701)

Here we have:
artifact combiner creating one element unmerge and
unmerge lowering of FP source using FP type for bit twiddling.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index 0c6853fe4ae66..bfe447daf8560 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -1433,3 +1433,26 @@ body: |
     %5:_(s32) = G_ANYEXT %4
     $vgpr0 = COPY %5
 ...
+
+---
+name: extract_vector_elt_v32i1_bitcast_f32
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: extract_vector_elt_v32i1_bitcast_f32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](f32)
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[UV]], [[C]](i32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[AND]](i32)
+    %0:_(f32) = COPY $vgpr0
+    %1:_(<32 x i1>) = G_BITCAST %0
+    %2:_(i32) = G_CONSTANT i32 0
+    %3:_(i1) = G_EXTRACT_VECTOR_ELT %1, %2
+    %4:_(i32) = G_ZEXT %3
+    $vgpr0 = COPY %4
+...

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
index 5a1d715b98f43..80806ed66c097 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
@@ -1105,3 +1105,24 @@ body: |
     %6:_(s32) = G_ZEXT %4:_(s8)
     $vgpr0 = COPY %6:_(s32)
 ...
+
+---
+name: test_unmerge_f32_to_s16
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: test_unmerge_f32_to_s16
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY]](f32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_CONSTANT i32 16
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C]](f32)
+    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](f32)
+    ; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](i16)
+    ; CHECK-NEXT: $vgpr1 = COPY [[TRUNC1]](i16)
+    %0:_(f32) = COPY $vgpr0
+    %1:_(i16), %2:_(i16) = G_UNMERGE_VALUES %0
+    $vgpr0 = COPY %1
+    $vgpr1 = COPY %2
+...