[llvm] [NFC][AMDGPU] Rename some variable names to follow convention better (PR #213827)

[Shilei Tian via llvm-commits]

https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/213827

This is a follow-up of #213491.


>From 136b116b12a24efcb0d374660050fb187b9129b8 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 4 Aug 2026 00:09:39 -0400
Subject: [PATCH] [NFC][AMDGPU] Rename some variable names to follow convention
 better

This is a follow-up of #213491.
---
 llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp |  4 ++--
 llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp    |  9 ++++-----
 llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h  | 10 +++++-----
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp       |  8 ++++----
 4 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
index 94830ba998f27..dc4d7eb5bdc9c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
@@ -104,8 +104,8 @@ bool AMDGPUReserveWWMRegs::run(MachineFunction &MF) {
       MO.setIsRenamable(false);
   }
 
-  // Now clear the NonWWMRegMask earlier set during wwm-regalloc.
-  MFI->clearNonWWMRegAllocMask();
+  // Now clear the PerlaneVGPRMask earlier set during wwm-regalloc.
+  MFI->clearPerlaneVGPRAllocMask();
 
   return Changed;
 }
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 5bf34ddcb2816..9734222c99691 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -427,12 +427,11 @@ void SILowerSGPRSpills::assignWWMRegs(MachineFunction &MF,
         "cannot find enough VGPRs for wwm-regalloc");
   }
 
-  BitVector NonWwmRegMask(WwmRegMask);
-  NonWwmRegMask.flip().clearBitsNotInMask(TRI->getAllVGPRRegMask());
+  BitVector PerlaneVGPRMask(WwmRegMask);
+  PerlaneVGPRMask.flip().clearBitsNotInMask(TRI->getAllVGPRRegMask());
 
-  // The complement set will be the registers for non-wwm (per-thread) vgpr
-  // allocation.
-  FuncInfo->updateNonWWMRegMask(NonWwmRegMask);
+  // The complement set will be the registers for per-lane VGPR allocation.
+  FuncInfo->updatePerlaneVGPRMask(PerlaneVGPRMask);
 }
 
 bool SILowerSGPRSpillsLegacy::runOnMachineFunction(MachineFunction &MF) {
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 2d1b77fc4fb8f..fa68ef8687575 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -580,9 +580,9 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunctionInfo,
   WWMSpillsMap WWMSpills;
 
   // Before allocation, the VGPR registers are partitioned into two distinct
-  // sets, the first one for WWM-values and the second set for non-WWM values.
+  // sets, the first one for WWM values and the second set for per-lane values.
   // The latter set should be reserved during WWM-regalloc.
-  BitVector NonWWMRegMask;
+  BitVector PerlaneVGPRMask;
 
   using ReservedRegSet = SmallSetVector<Register, 8>;
   // To track the VGPRs reserved for WWM instructions. They get stack slots
@@ -679,9 +679,9 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunctionInfo,
                            : WWMReservedRegs.contains(Reg);
   }
 
-  void updateNonWWMRegMask(BitVector &RegMask) { NonWWMRegMask = RegMask; }
-  BitVector getNonWWMRegMask() const { return NonWWMRegMask; }
-  void clearNonWWMRegAllocMask() { NonWWMRegMask.clear(); }
+  void updatePerlaneVGPRMask(BitVector &RegMask) { PerlaneVGPRMask = RegMask; }
+  BitVector getPerlaneVGPRMask() const { return PerlaneVGPRMask; }
+  void clearPerlaneVGPRAllocMask() { PerlaneVGPRMask.clear(); }
 
   SIModeRegisterDefaults getMode() const { return Mode; }
 
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 01220a701a453..40db08dfc4778 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -753,13 +753,13 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   }
 
   // During wwm-regalloc, reserve the registers for perlane VGPR allocation. The
-  // MFI->getNonWWMRegMask() field will have a valid bitmask only during
+  // MFI->getPerlaneVGPRMask() field will have a valid bitmask only during
   // wwm-regalloc and it would be empty otherwise.
-  BitVector NonWWMRegMask = MFI->getNonWWMRegMask();
-  if (!NonWWMRegMask.empty()) {
+  BitVector PerlaneVGPRMask = MFI->getPerlaneVGPRMask();
+  if (!PerlaneVGPRMask.empty()) {
     for (unsigned RegI = AMDGPU::VGPR0, RegE = AMDGPU::VGPR0 + MaxNumVGPRs;
          RegI < RegE; ++RegI) {
-      if (NonWWMRegMask.test(RegI))
+      if (PerlaneVGPRMask.test(RegI))
         reserveRegisterTuples(Reserved, RegI);
     }
   }