[llvm] [PowerPC] Fix tlbie one-operand InstAlias for ISA 3.0+ (PR #213816)

via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 3 18:23:07 PDT 2026


llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-powerpc

Author: Chris Copeland (chrisnc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/213816.diff


2 Files Affected:

- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.td (+1-1) 
- (modified) llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s (+8) 


``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a67da9b85aa94..d09fc965ec6a2 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5003,7 +5003,7 @@ def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
 
 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>,  Requires<[IsNotISA3_0]>;
 let Predicates = [IsISA3_0] in {
-  def : InstAlias<"tlbie $RB", (TLBIEP9 R0, gprc:$RB, 0, 0, 0)>;
+  def : InstAlias<"tlbie $RB", (TLBIEP9 gprc:$RB, R0, 0, 0, 0)>;
   def : InstAlias<"tlbie $RB, $RS", (TLBIEP9 gprc:$RB, gprc:$RS, 0, 0, 0)>;
 }
 
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s b/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
index e08434058f28a..f3a2c86f24ab2 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s
@@ -170,6 +170,14 @@
 # CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
             tlbie %r4
 
+# CHECK-BE: tlbie 4                         # encoding: [0x7c,0x00,0x22,0x64]
+# CHECK-LE: tlbie 4                         # encoding: [0x64,0x22,0x00,0x7c]
+            tlbie 4, 0, 0, 0, 0
+
+# CHECK-BE: tlbie 4, 5                      # encoding: [0x7c,0xa0,0x22,0x64]
+# CHECK-LE: tlbie 4, 5                      # encoding: [0x64,0x22,0xa0,0x7c]
+            tlbie 4, 5, 0, 0, 0
+
 # CHECK-BE: tlbilx 1, 4, 5                  # encoding: [0x7c,0x24,0x28,0x24]
 # CHECK-LE: tlbilx 1, 4, 5                  # encoding: [0x24,0x28,0x24,0x7c]
             tlbilx 1, %r4, %r5

``````````

</details>


https://github.com/llvm/llvm-project/pull/213816


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