[llvm] [AArch64] Lower fixed-length interleaved stores with SVE (PR #213692)

[David Sherwood via llvm-commits]

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@@ -27805,8 +27803,12 @@ performInterleavedStoreCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     return DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, DL,
                                    DAG.getVTList(MVT::Other), Ops,
                                    MemN->getMemoryVT(), MemN->getMemOperand());
-  } else {
+  }
 
+  const AArch64Subtarget &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
+  // Fixed length vector using NEON
+  if (!IsMasked && (SubBits == 64 || SubBits == 128) &&
+      Subtarget.isNeonAvailable()) {
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david-arm wrote:

Does this mean we also need streaming SVE VLA tests?

https://github.com/llvm/llvm-project/pull/213692