[llvm] [AArch64][GlobalISel] Legalize <8 x i1> and <16 x i1> loads and stores (PR #210514)

[Nathan Corbyn via llvm-commits]

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@@ -1604,16 +1616,100 @@ bool AArch64LegalizerInfo::legalizeCustom(
   llvm_unreachable("expected switch to return");
 }
 
+bool AArch64LegalizerInfo::legalizeI1VecStore(MachineInstr &MI,
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cofibrant wrote:

I don't think this achieves what you set out to achieve: you're only improving the lowering in two very specific cases (1) the store is fed by a bit cast, (2) the store is fed by a load.

https://github.com/llvm/llvm-project/pull/210514