[llvm] [VPlan] Constant-fold ActiveLaneMask intrinsics (PR #208852)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 3 06:24:04 PDT 2026
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/208852
>From 48704d87ebbf71e89161993757c4a5dc82c15305 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Sun, 2 Aug 2026 11:53:43 +0100
Subject: [PATCH 1/2] [LV] Pre-commit ALM tests
---
.../vplan-scalable-active-lane-mask.ll | 29 +++++++++++++++++++
.../VPlan/vplan-foldable-active-lane-mask.ll | 26 +++++++++++++++++
2 files changed, 55 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-scalable-active-lane-mask.ll
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/vplan-foldable-active-lane-mask.ll
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-scalable-active-lane-mask.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-scalable-active-lane-mask.ll
new file mode 100644
index 0000000000000..10a952683119b
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-scalable-active-lane-mask.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "active.lane.mask" --version 6
+; RUN: opt -mtriple=aarch64 -mcpu=neoverse-v1 -passes=loop-vectorize -force-vector-width="vscale x 4" -force-vector-interleave=1 -tail-folding-policy=prefer-fold-tail -disable-output -vplan-print-after=printOptimizedVPlan %s 2>&1 | FileCheck %s
+
+; We never emit a scalable active.lane.mask that can be folded to a constant.
+define i32 @scalable_alm_liveins(ptr %A, ptr noalias %B) {
+; CHECK-LABEL: VPlan for loop in 'scalable_alm_liveins'
+; CHECK: EMIT vp<%active.lane.mask.entry> = active lane mask vp<%index.part.next>, ir<1002>, ir<1>
+; CHECK: ACTIVE-LANE-MASK-PHI vp<[[VP5:%[0-9]+]]> = phi vp<%active.lane.mask.entry>, vp<%active.lane.mask.next>
+; CHECK: EMIT vp<%active.lane.mask.next> = active lane mask vp<[[VP8:%[0-9]+]]>, ir<1002>, ir<1>
+; CHECK: EMIT vp<[[VP9:%[0-9]+]]> = not vp<%active.lane.mask.next>
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %for = phi i16 [ 0, %entry ], [ %for.next, %loop ]
+ %sext = sext i16 %for to i32
+ %iv.next = add i64 %iv, 1
+ %gep.A = getelementptr i32, ptr %A, i64 %iv.next
+ %for.next = load i16, ptr %gep.A, align 2
+ %gep.B = getelementptr i32, ptr %B, i64 %iv.next
+ store i32 %sext, ptr %gep.B
+ %ec = icmp eq i64 %iv, 1001
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret i32 0
+}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-foldable-active-lane-mask.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-foldable-active-lane-mask.ll
new file mode 100644
index 0000000000000..b2fdc9e79cad7
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-foldable-active-lane-mask.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "active.lane.mask" --version 6
+; RUN: opt -passes=loop-vectorize -tail-folding-policy=must-fold-tail -force-tail-folding-style=data -force-vector-width=4 -disable-output -vplan-print-after=printOptimizedVPlan %s 2>&1 | FileCheck %s --check-prefix=FIXED
+; RUN: opt -passes=loop-vectorize -tail-folding-policy=must-fold-tail -force-tail-folding-style=data -force-vector-width="vscale x 4" -disable-output -vplan-print-after=printOptimizedVPlan %s 2>&1 | FileCheck %s --check-prefix=SCALABLE
+
+; We never emit fixed-vector active.lane.masks foldable to false.
+define i16 @foldable_fixed_alm(i32 %x) {
+; FIXED-LABEL: VPlan for loop in 'foldable_fixed_alm'
+; SCALABLE-LABEL: VPlan for loop in 'foldable_fixed_alm'
+; SCALABLE: EMIT vp<%active.lane.mask> = active lane mask vp<[[VP5:%[0-9]+]]>, ir<4>, ir<1>
+; SCALABLE: EMIT vp<[[VP7:%[0-9]+]]> = last-active-lane vp<%active.lane.mask>
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %red = phi i32 [ 0, %entry ], [ %add, %loop ]
+ %t = trunc i32 %red to i16
+ %add = add i32 %red, %x
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv, 3
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret i16 %t
+}
>From 210d50d29e8e1e5921849f94bde7d2874c72bd41 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Mon, 22 Jun 2026 18:18:42 +0100
Subject: [PATCH 2/2] [VPlan] Constant-fold ActiveLaneMask intrinsics
Constant-fold fixed-vector types via llvm::simplifyIntrinsic, making it
accessible from InstSimplifyFolder, and use it for folding
get.active.lane.mask in VPlan.
---
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 17 +++++++++++++++++
.../AArch64/first-order-recurrence-fold-tail.ll | 3 +--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 93b18b31e9e7d..b658e57a0e597 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -1115,6 +1115,23 @@ VPIRValue *vputils::tryToFoldLiveIns(VPSingleDefRecipe &R,
case Instruction::ExtractElement:
assert(!Ops[0]->getType()->isVectorTy() && "Live-ins should be scalar");
return Ops[0];
+ case VPInstruction::ActiveLaneMask: {
+ uint64_t Multiplier = cast<ConstantInt>(Ops[2])->getZExtValue();
+ Type *I1Ty = IntegerType::getInt1Ty(Plan.getContext());
+ if (Plan.hasScalableVF())
+ // We do not produce foldable scalable ALMs at the moment.
+ return nullptr;
+
+ // We do not produce ALMs foldable to false at the moment.
+ unsigned MaxVF = Multiplier * max_element(Plan.vectorFactors(),
+ ElementCount::isKnownLT)
+ ->getFixedValue();
+ if (auto *C = dyn_cast_if_present<Constant>(Folder.FoldIntrinsic(
+ Intrinsic::get_active_lane_mask, drop_end(Ops),
+ FixedVectorType::get(I1Ty, MaxVF))))
+ if (C->isOneValue())
+ return ConstantInt::getTrue(I1Ty);
+ }
}
return nullptr;
};
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence-fold-tail.ll b/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence-fold-tail.ll
index 380554dd22b64..ed4fcb31f9dda 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence-fold-tail.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence-fold-tail.ll
@@ -9,11 +9,10 @@ define i32 @test_phi_iterator_invalidation(ptr %A, ptr noalias %B) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
-; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 1002)
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE6:%.*]] ]
-; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ splat (i1 true), [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_LOAD_CONTINUE6]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_LOAD_CONTINUE6]] ]
; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i16> [ <i16 poison, i16 poison, i16 poison, i16 0>, [[VECTOR_PH]] ], [ [[TMP24:%.*]], [[PRED_LOAD_CONTINUE6]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 1)
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