[llvm] [LV] Avoid adding stray predicates in isConsecutivePtr (PR #213662)
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llvm-commits at lists.llvm.org
Mon Aug 3 06:04:13 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-vectorizers
Author: Ramkumar Ramachandra (artagnon)
<details>
<summary>Changes</summary>
If the absolute value of Stride is not unit, avoid adding stray SCEV predicates.
---
Patch is 53.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213662.diff
10 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp (+7-5)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll (+15-26)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll (+48-18)
- (modified) llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll (+12-77)
- (modified) llvm/test/Transforms/LoopVectorize/bounded-load.ll (+58-18)
- (modified) llvm/test/Transforms/LoopVectorize/pr34681.ll (+2-26)
- (modified) llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll (+3-7)
- (modified) llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll (+8-19)
- (modified) llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll (+1-13)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll (+15-73)
``````````diff
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 9086880599231..cb93bece62a54 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -461,12 +461,14 @@ int LoopVectorizationLegality::isConsecutivePtr(Type *AccessTy,
const auto &Strides = LAI && AllowRuntimeSCEVChecks
? LAI->getSymbolicStrides()
: DenseMap<Value *, const SCEV *>();
- int Stride = getPtrStride(PSE, AccessTy, Ptr, TheLoop, *DT, Strides,
- AllowRuntimeSCEVChecks, false)
+ SmallVector<const SCEVPredicate *> Predicates;
+ int Stride = getPtrStride(PSE, AccessTy, Ptr, TheLoop, *DT, Strides, false,
+ AllowRuntimeSCEVChecks ? &Predicates : nullptr)
.value_or(0);
- if (Stride == 1 || Stride == -1)
- return Stride;
- return 0;
+ if (std::abs(Stride) != 1)
+ return 0;
+ for_each(Predicates, [&](const SCEVPredicate *P) { PSE.addPredicate(*P); });
+ return Stride;
}
bool LoopVectorizationLegality::isInvariant(Value *V) const {
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
index dbee392ed67e9..2fc0073c06b67 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
@@ -14,43 +14,32 @@ define void @stride_exceeds_i32_max(ptr noalias readonly %src, ptr noalias %dst,
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 1
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP5:%.*]] = icmp slt i16 -1, [[START]]
-; CHECK-NEXT: br i1 [[TMP5]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[TMP12:%.*]] = sext i16 [[START]] to i64
-; CHECK-NEXT: [[TMP13:%.*]] = mul nsw i64 [[TMP12]], 3000000000
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP13]]
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x ptr> poison, ptr [[DST]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 16 x ptr> poison, <vscale x 16 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 16 x i16> @llvm.stepvector.nxv16i16()
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 16 x i16> poison, i16 [[START]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 16 x i16> [[BROADCAST_SPLATINSERT1]], <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
+; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 16 x i16> [[BROADCAST_SPLAT2]], [[TMP8]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP4]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 16 x i16> [ [[INDUCTION]], %[[VECTOR_SCEVCHECK]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP4]], %[[VECTOR_SCEVCHECK]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 16, i1 true)
-; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[INDEX]] to i64
-; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP7]], 3000000000
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP11]]
-; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP8]], i64 3000000000, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
+; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP6]] to i16
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 16 x i16> poison, i16 [[TMP5]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 16 x i16> [[BROADCAST_SPLATINSERT3]], <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP11:%.*]] = sext <vscale x 16 x i16> [[VEC_IND]] to <vscale x 16 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = mul nsw <vscale x 16 x i64> [[TMP11]], splat (i64 3000000000)
+; CHECK-NEXT: [[WIDE_GEP:%.*]] = getelementptr i8, ptr [[SRC]], <vscale x 16 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 16 x i8> @llvm.vp.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> align 1 [[WIDE_GEP]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
; CHECK-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
-; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP6]], [[INDEX]]
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP6]]
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i16> [[VEC_IND]], [[BROADCAST_SPLAT4]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
-; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i16 [ [[START]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[IV_EXT:%.*]] = sext i16 [[IV]] to i64
-; CHECK-NEXT: [[OFFSET:%.*]] = mul nsw i64 [[IV_EXT]], 3000000000
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET]]
-; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[GEP]], align 1
-; CHECK-NEXT: store i8 [[VAL]], ptr [[DST]], align 1
-; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[IV_NEXT]], 0
-; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
index 3f85bbc5b8100..708f488b93eef 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
@@ -282,34 +282,64 @@ exit:
define void @narrow_iv_i8_sext_i64_wrapping(ptr noalias %arr, ptr noalias %out) {
; RV64-LABEL: define void @narrow_iv_i8_sext_i64_wrapping(
; RV64-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
-; RV64-NEXT: [[ENTRY:.*]]:
+; RV64-NEXT: [[ENTRY:.*:]]
; RV64-NEXT: br label %[[LOOP:.*]]
; RV64: [[LOOP]]:
-; RV64-NEXT: [[I:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
-; RV64-NEXT: [[IDX:%.*]] = sext i8 [[I]] to i64
-; RV64-NEXT: [[PTR:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], i64 [[IDX]]
-; RV64-NEXT: [[VAL:%.*]] = load i8, ptr [[PTR]], align 1
-; RV64-NEXT: store i8 [[VAL]], ptr [[OUT]], align 1
-; RV64-NEXT: [[I_NEXT]] = add i8 [[I]], 4
-; RV64-NEXT: [[CMP:%.*]] = icmp ne i8 [[I_NEXT]], 0
-; RV64-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]]
+; RV64-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x ptr> poison, ptr [[OUT]], i64 0
+; RV64-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 16 x ptr> poison, <vscale x 16 x i32> zeroinitializer
+; RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()
+; RV64-NEXT: [[TMP1:%.*]] = mul <vscale x 16 x i8> [[TMP0]], splat (i8 4)
+; RV64-NEXT: br label %[[EXIT:.*]]
; RV64: [[EXIT]]:
+; RV64-NEXT: [[VEC_IND:%.*]] = phi <vscale x 16 x i8> [ [[TMP1]], %[[LOOP]] ], [ [[VEC_IND_NEXT:%.*]], %[[EXIT]] ]
+; RV64-NEXT: [[AVL:%.*]] = phi i32 [ 64, %[[LOOP]] ], [ [[AVL_NEXT:%.*]], %[[EXIT]] ]
+; RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 16, i1 true)
+; RV64-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
+; RV64-NEXT: [[TMP4:%.*]] = shl i8 [[TMP3]], 2
+; RV64-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[TMP4]], i64 0
+; RV64-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 16 x i8> [[BROADCAST_SPLATINSERT1]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+; RV64-NEXT: [[TMP5:%.*]] = sext <vscale x 16 x i8> [[VEC_IND]] to <vscale x 16 x i64>
+; RV64-NEXT: [[WIDE_GEP:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], <vscale x 16 x i64> [[TMP5]]
+; RV64-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.vp.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> align 1 [[WIDE_GEP]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV64-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> [[WIDE_MASKED_GATHER]], <vscale x 16 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV64-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]]
+; RV64-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i8> [[VEC_IND]], [[BROADCAST_SPLAT2]]
+; RV64-NEXT: [[TMP6:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
+; RV64-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[EXIT]], !llvm.loop [[LOOP6:![0-9]+]]
+; RV64: [[MIDDLE_BLOCK]]:
+; RV64-NEXT: br label %[[EXIT1:.*]]
+; RV64: [[EXIT1]]:
; RV64-NEXT: ret void
;
; RV32-LABEL: define void @narrow_iv_i8_sext_i64_wrapping(
; RV32-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
-; RV32-NEXT: [[ENTRY:.*]]:
+; RV32-NEXT: [[ENTRY:.*:]]
; RV32-NEXT: br label %[[LOOP:.*]]
; RV32: [[LOOP]]:
-; RV32-NEXT: [[I:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
-; RV32-NEXT: [[IDX:%.*]] = sext i8 [[I]] to i64
-; RV32-NEXT: [[PTR:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], i64 [[IDX]]
-; RV32-NEXT: [[VAL:%.*]] = load i8, ptr [[PTR]], align 1
-; RV32-NEXT: store i8 [[VAL]], ptr [[OUT]], align 1
-; RV32-NEXT: [[I_NEXT]] = add i8 [[I]], 4
-; RV32-NEXT: [[CMP:%.*]] = icmp ne i8 [[I_NEXT]], 0
-; RV32-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]]
+; RV32-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x ptr> poison, ptr [[OUT]], i64 0
+; RV32-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 16 x ptr> poison, <vscale x 16 x i32> zeroinitializer
+; RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()
+; RV32-NEXT: [[TMP1:%.*]] = mul <vscale x 16 x i8> [[TMP0]], splat (i8 4)
+; RV32-NEXT: br label %[[EXIT:.*]]
; RV32: [[EXIT]]:
+; RV32-NEXT: [[VEC_IND:%.*]] = phi <vscale x 16 x i8> [ [[TMP1]], %[[LOOP]] ], [ [[VEC_IND_NEXT:%.*]], %[[EXIT]] ]
+; RV32-NEXT: [[AVL:%.*]] = phi i32 [ 64, %[[LOOP]] ], [ [[AVL_NEXT:%.*]], %[[EXIT]] ]
+; RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 16, i1 true)
+; RV32-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
+; RV32-NEXT: [[TMP4:%.*]] = shl i8 [[TMP3]], 2
+; RV32-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[TMP4]], i64 0
+; RV32-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 16 x i8> [[BROADCAST_SPLATINSERT1]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
+; RV32-NEXT: [[TMP5:%.*]] = sext <vscale x 16 x i8> [[VEC_IND]] to <vscale x 16 x i64>
+; RV32-NEXT: [[WIDE_GEP:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], <vscale x 16 x i64> [[TMP5]]
+; RV32-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.vp.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> align 1 [[WIDE_GEP]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV32-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> [[WIDE_MASKED_GATHER]], <vscale x 16 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP2]])
+; RV32-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]]
+; RV32-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i8> [[VEC_IND]], [[BROADCAST_SPLAT2]]
+; RV32-NEXT: [[TMP6:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
+; RV32-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[EXIT]], !llvm.loop [[LOOP6:![0-9]+]]
+; RV32: [[MIDDLE_BLOCK]]:
+; RV32-NEXT: br label %[[EXIT1:.*]]
+; RV32: [[EXIT1]]:
; RV32-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
index d9c0cea9d6f67..0480f8b31404d 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
@@ -1020,88 +1020,23 @@ exit:
define void @replicated_load_wide_store_derived_iv_zext_and(ptr noalias %src, ptr %dst, i32 %step) {
; I64-LABEL: define void @replicated_load_wide_store_derived_iv_zext_and(
; I64-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i32 [[STEP:%.*]]) {
-; I64-NEXT: [[ENTRY:.*:]]
-; I64-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
-; I64: [[VECTOR_SCEVCHECK]]:
-; I64-NEXT: [[TMP0:%.*]] = trunc i32 [[STEP]] to i1
-; I64-NEXT: [[TMP4:%.*]] = sext i1 [[TMP0]] to i32
-; I64-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP4]]
-; I64-NEXT: [[TMP5:%.*]] = sub i32 0, [[STEP]]
-; I64-NEXT: [[TMP6:%.*]] = icmp slt i32 [[STEP]], 0
-; I64-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 [[STEP]]
-; I64-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP7]], i32 128)
-; I64-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
-; I64-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
-; I64-NEXT: [[TMP8:%.*]] = sub i32 0, [[MUL_RESULT2]]
-; I64-NEXT: [[TMP9:%.*]] = icmp ugt i32 [[TMP8]], 0
-; I64-NEXT: [[TMP10:%.*]] = select i1 [[TMP6]], i1 [[TMP9]], i1 false
-; I64-NEXT: [[TMP11:%.*]] = or i1 [[TMP10]], [[MUL_OVERFLOW3]]
-; I64-NEXT: [[TMP12:%.*]] = or i1 [[TMP0]], [[IDENT_CHECK]]
-; I64-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[TMP11]]
-; I64-NEXT: br i1 [[TMP13]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; I64: [[VECTOR_PH]]:
-; I64-NEXT: [[TMP14:%.*]] = shl i32 [[STEP]], 7
+; I64-NEXT: [[VECTOR_PH:.*]]:
; I64-NEXT: br label %[[VECTOR_BODY:.*]]
; I64: [[VECTOR_BODY]]:
-; I64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; I64-NEXT: [[TMP15:%.*]] = trunc i64 [[INDEX]] to i32
-; I64-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[STEP]]
-; I64-NEXT: [[TMP17:%.*]] = mul i32 1, [[STEP]]
-; I64-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], [[TMP17]]
-; I64-NEXT: [[TMP19:%.*]] = mul i32 2, [[STEP]]
-; I64-NEXT: [[TMP20:%.*]] = add i32 [[TMP16]], [[TMP19]]
-; I64-NEXT: [[TMP21:%.*]] = mul i32 3, [[STEP]]
-; I64-NEXT: [[TMP22:%.*]] = add i32 [[TMP16]], [[TMP21]]
-; I64-NEXT: [[TMP23:%.*]] = mul i32 4, [[STEP]]
-; I64-NEXT: [[TMP24:%.*]] = add i32 [[TMP16]], [[TMP23]]
-; I64-NEXT: [[TMP25:%.*]] = mul i32 5, [[STEP]]
-; I64-NEXT: [[TMP26:%.*]] = add i32 [[TMP16]], [[TMP25]]
-; I64-NEXT: [[TMP27:%.*]] = mul i32 6, [[STEP]]
-; I64-NEXT: [[TMP28:%.*]] = add i32 [[TMP16]], [[TMP27]]
-; I64-NEXT: [[TMP29:%.*]] = mul i32 7, [[STEP]]
-; I64-NEXT: [[TMP30:%.*]] = add i32 [[TMP16]], [[TMP29]]
-; I64-NEXT: [[TMP31:%.*]] = zext i32 [[TMP16]] to i64
-; I64-NEXT: [[TMP32:%.*]] = zext i32 [[TMP18]] to i64
-; I64-NEXT: [[TMP33:%.*]] = zext i32 [[TMP20]] to i64
-; I64-NEXT: [[TMP34:%.*]] = zext i32 [[TMP22]] to i64
-; I64-NEXT: [[TMP35:%.*]] = zext i32 [[TMP24]] to i64
-; I64-NEXT: [[TMP36:%.*]] = zext i32 [[TMP26]] to i64
-; I64-NEXT: [[TMP37:%.*]] = zext i32 [[TMP28]] to i64
+; I64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_0_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; I64-NEXT: [[TMP30:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[VECTOR_BODY]] ]
; I64-NEXT: [[TMP38:%.*]] = zext i32 [[TMP30]] to i64
-; I64-NEXT: [[TMP39:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP31]]
-; I64-NEXT: [[TMP40:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP32]]
-; I64-NEXT: [[TMP41:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP33]]
-; I64-NEXT: [[TMP42:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP34]]
-; I64-NEXT: [[TMP43:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP35]]
-; I64-NEXT: [[TMP44:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP36]]
-; I64-NEXT: [[TMP45:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP37]]
; I64-NEXT: [[TMP46:%.*]] = getelementptr float, ptr [[SRC]], i64 [[TMP38]]
-; I64-NEXT: [[TMP47:%.*]] = load float, ptr [[TMP39]], align 4
-; I64-NEXT: [[TMP48:%.*]] = load float, ptr [[TMP40]], align 4
-; I64-NEXT: [[TMP49:%.*]] = load float, ptr [[TMP41]], align 4
-; I64-NEXT: [[TMP50:%.*]] = load float, ptr [[TMP42]], align 4
-; I64-NEXT: [[TMP51:%.*]] = insertelement <4 x float> poison, float [[TMP47]], i32 0
-; I64-NEXT: [[TMP52:%.*]] = insertelement <4 x float> [[TMP51]], float [[TMP48]], i32 1
-; I64-NEXT: [[TMP53:%.*]] = insertelement <4 x float> [[TMP52]], float [[TMP49]], i32 2
-; I64-NEXT: [[TMP54:%.*]] = insertelement <4 x float> [[TMP53]], float [[TMP50]], i32 3
-; I64-NEXT: [[TMP55:%.*]] = load float, ptr [[TMP43]], align 4
-; I64-NEXT: [[TMP56:%.*]] = load float, ptr [[TMP44]], align 4
-; I64-NEXT: [[TMP57:%.*]] = load float, ptr [[TMP45]], align 4
; I64-NEXT: [[TMP58:%.*]] = load float, ptr [[TMP46]], align 4
-; I64-NEXT: [[TMP59:%.*]] = insertelement <4 x float> poison, float [[TMP55]], i32 0
-; I64-NEXT: [[TMP60:%.*]] = insertelement <4 x float> [[TMP59]], float [[TMP56]], i32 1
-; I64-NEXT: [[TMP61:%.*]] = insertelement <4 x float> [[TMP60]], float [[TMP57]], i32 2
-; I64-NEXT: [[TMP62:%.*]] = insertelement <4 x float> [[TMP61]], float [[TMP58]], i32 3
; I64-NEXT: [[TMP63:%.*]] = getelementptr float, ptr [[DST]], i64 [[INDEX]]
-; I64-NEXT: [[TMP64:%.*]] = getelementptr float, ptr [[TMP63]], i64 4
-; I64-NEXT: store <4 x float> [[TMP54]], ptr [[TMP63]], align 4
-; I64-NEXT: store <4 x float> [[TMP62]], ptr [[TMP64]], align 4
-; I64-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; I64-NEXT: [[TMP65:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; I64-NEXT: br i1 [[TMP65]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
-; I64: [[MIDDLE_BLOCK]]:
-; I64-NEXT: br label %[[SCALAR_PH]]
+; I64-NEXT: store float [[TMP58]], ptr [[TMP63]], align 4
+; I64-NEXT: [[IV_1_ADD:%.*]] = and i32 [[TMP30]], 1
+; I64-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1_ADD]], [[STEP]]
+; I64-NEXT: [[IV_0_NEXT]] = add i64 [[INDEX]], 1
+; I64-NEXT: [[EC:%.*]] = icmp eq i64 [[INDEX]], 128
+; I64-NEXT: br i1 [[EC]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]]
; I64: [[SCALAR_PH]]:
+; I64-NEXT: ret void
;
; I32-LABEL: define void @replicated_load_wide_store_derived_iv_zext_and(
; I32-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i32 [[STEP:%.*]]) {
@@ -1214,7 +1149,7 @@ define void @replicated_load_wide_store_derived_iv_zext_and2(ptr noalias %dst, p
; I64-NEXT: store <4 x float> [[TMP54]], ptr [[TMP56]], align 4
; I64-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; I64-NEXT: [[TMP57:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
-; I64-NEXT: br i1 [[TMP57]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
+; I64-NEXT: br i1 [[TMP57]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; I64: [[MIDDLE_BLOCK]]:
; I64-NEXT: br label %[[SCALAR_PH]]
; I64: [[SCALAR_PH]]:
@@ -1283,7 +1218,7 @@ define void @invariant_pred_store_sunk_out_of_loop(ptr noalias %dst, ptr noalias
; I64-NEXT: [[TMP5]] = add <2 x ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213662
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