[llvm] [VPlan] Extend cse to eliminate redundant widened loads (PR #212543)

[Ashutosh Nema via llvm-commits]

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@@ -2304,7 +2330,26 @@ struct VPCSEDenseMapInfo : public DenseMapInfo<VPSingleDefRecipe *> {
 };
 } // end anonymous namespace
 
-/// Perform a common-subexpression-elimination of VPSingleDefRecipes on the \p
+/// Return true if no memory-writing recipe between \p From and \p To may alias
+/// \p MemLoc. \p From and \p To must be in the same block.
+static bool noAliasingWriteBetween(const MemoryLocation &MemLoc,
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nema-ashutosh wrote:

I looked into reusing canHoistOrSinkWithNoAliasCheck for load CSE. The tricky part is that the hoist/sink check scans whole blocks anchored on the FirstBB/LastBB blocks (and descends into nested regions), while CSE just needs the range between two load recipes in the same block.

I tried making the recipe pair (VPRecipeBase *From, VPRecipeBase *To) the main signature and adding a small wrapper that takes the FirstBB/LastBB basic blocks. That didn't work out though. The entry basic block of the vector loop region can be empty, so &FirstBB->front() crashes when trying to get the From recipe. 
I also tried skipping the empty end blocks with getSingleSuccessor(), but that lands on a nested replicate region instead of a basic block, so From and To end up in different regions and trip the "different regions" assert. To get it right I'd basically need to walk the chain again in a region-aware way, which defeats the point.

So as an alternative, could we keep a single canHoistOrSinkWithNoAliasCheck on the FirstBB/LastBB basic blocks and add optional From/To recipe bounds? The existing hoist/sink callers don't change (they just pass the blocks), CSE passes the two loads to limit the scan, and noAliasingWriteBetween goes away.  Does this seem reasonable, or would you rather do it differently ?

https://github.com/llvm/llvm-project/pull/212543