[llvm] 0e87f69 - [AArch64][GlobalISel] Select narrow GPR constants (#204322)

[via llvm-commits]

Author: Cullen Rhodes
Date: 2026-08-03T11:59:15+01:00
New Revision: 0e87f69d0c327612590f73b715c657c5096383c2

URL: https://github.com/llvm/llvm-project/commit/0e87f69d0c327612590f73b715c657c5096383c2
DIFF: https://github.com/llvm/llvm-project/commit/0e87f69d0c327612590f73b715c657c5096383c2.diff

LOG: [AArch64][GlobalISel] Select narrow GPR constants (#204322)

Select non-zero s8/s16 GPR constants as 32-bit MOV immediates during
instruction selection.

RegBankSelect already does this, but this gives instruction selection a
direct path instead of falling back which will help enable a simple fast
pure type-based RBS alternative.

Assisted-by: codex

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 0c2f3f97ec07d..7e9135b15144a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2143,8 +2143,25 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
   case TargetOpcode::G_CONSTANT: {
     Register DefReg = I.getOperand(0).getReg();
     const LLT DefTy = MRI.getType(DefReg);
-    if (!DefTy.isPointer())
-      return false;
+    if (!DefTy.isPointer()) {
+      if (DefTy.getSizeInBits() >= 32 ||
+          RBI.getRegBank(DefReg, MRI, TRI)->getID() != AArch64::GPRRegBankID)
+        return false;
+      // Widen narrow GPR constants to s32 so imported patterns can match.
+      APInt Val = I.getOperand(1).getCImm()->getValue().zext(32);
+      I.getOperand(1).setCImm(
+          ConstantInt::get(MF.getFunction().getContext(), Val));
+
+      Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
+      MRI.setRegBank(WideReg, RBI.getRegBank(AArch64::GPRRegBankID));
+      I.getOperand(0).setReg(WideReg);
+
+      MIB.setInsertPt(MBB, std::next(I.getIterator()));
+      auto Copy = MIB.buildCopy(DefReg, WideReg);
+      selectCopy(*Copy, TII, MRI, TRI, RBI);
+      MIB.setInstr(I);
+      return true;
+    }
     const unsigned PtrSize = DefTy.getSizeInBits();
     if (PtrSize != 32 && PtrSize != 64)
       return false;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index 95f860bafb2b9..c067696035126 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"