[llvm] [DAG] Change `isExtractSubvectorCheap` into `getExtractSubvectorCost` (PR #213614)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 3 03:29:37 PDT 2026
https://github.com/Shoreshen updated https://github.com/llvm/llvm-project/pull/213614
>From 213488383ba6b3ec5b62ac5c95565c2828547df4 Mon Sep 17 00:00:00 2001
From: shore <shorshen at amd.com>
Date: Mon, 3 Aug 2026 15:28:38 +0800
Subject: [PATCH 1/2] change isExtractSubvectorCheap into
getExtractSubvectorCost
---
llvm/include/llvm/CodeGen/TargetLowering.h | 23 +++++++++++-----
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 18 ++++++-------
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +-
.../Target/AArch64/AArch64ISelLowering.cpp | 10 ++++---
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 +--
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 ++++---
llvm/lib/Target/AMDGPU/SIISelLowering.h | 4 +--
llvm/lib/Target/ARM/ARMISelLowering.cpp | 10 ++++---
llvm/lib/Target/ARM/ARMISelLowering.h | 4 +--
.../Target/Hexagon/HexagonISelLowering.cpp | 12 +++++----
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 4 +--
.../LoongArch/LoongArchISelLowering.cpp | 11 +++++---
.../Target/LoongArch/LoongArchISelLowering.h | 4 +--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 27 +++++++++++--------
llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 +--
llvm/lib/Target/X86/X86ISelLowering.cpp | 20 ++++++++------
llvm/lib/Target/X86/X86ISelLowering.h | 4 +--
17 files changed, 100 insertions(+), 71 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index c663bb8ea65b7..80a7f7b770f64 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3540,13 +3540,22 @@ class LLVM_ABI TargetLoweringBase {
return false;
}
- /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
- /// from this source type with this index. This is needed because
- /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
- /// the first element, and only the target knows which lowering is cheap.
- virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
- return false;
+ /// Return the cost of extracting a subvector of type \p ResVT from a vector
+ /// of type \p SrcVT, starting at element \p Index:
+ ///
+ /// 0 - Free: lowers to no instruction at all, e.g. a subregister copy.
+ /// 1 - Cheap: lowers to at most one instruction, and may still be free if
+ /// the target can fold the extract into the instruction consuming it
+ /// (e.g. a widening op that reads the high half of a register).
+ /// 2 - Expensive: needs a shuffle sequence that cannot be folded away.
+ ///
+ /// Most callers only create a new EXTRACT_SUBVECTOR when the cost is below
+ /// 2. This hook exists because EXTRACT_SUBVECTOR usually has custom lowering
+ /// that depends on the index of the first element, so only the target knows
+ /// which lowering is cheap.
+ virtual unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
+ return 2;
}
/// Try to convert an extract element of a vector binary operation into an
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ae9af86196c86..d15598da732ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -21843,7 +21843,7 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
InterVT.getVectorNumElements() - LDMemType.getVectorNumElements();
}
- if (!TLI.isExtractSubvectorCheap(LDMemType, InterVT, ExtIdx))
+ if (!(TLI.getExtractSubvectorCost(LDMemType, InterVT, ExtIdx) < 2))
break;
Val = DAG.getExtractSubvector(SDLoc(LD), LDMemType,
DAG.getBitcast(InterVT, Val), ExtIdx);
@@ -26262,7 +26262,7 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
VecIn2 = SDValue();
} else if (InVT1Size == VTSize * 2) {
- if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems))
+ if (!(TLI.getExtractSubvectorCost(VT, InVT1, NumElems) < 2))
return SDValue();
if (!VecIn2.getNode()) {
@@ -26301,7 +26301,7 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
ConcatOps[0] = VecIn2;
VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
} else if (InVT1Size / VTSize > 1 && InVT1Size % VTSize == 0) {
- if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems) ||
+ if (!(TLI.getExtractSubvectorCost(VT, InVT1, NumElems) < 2) ||
!TLI.isTypeLegal(InVT1) || !TLI.isTypeLegal(InVT2))
return SDValue();
// If dest vector has less than two elements, then use shuffle and extract
@@ -27777,7 +27777,7 @@ static SDValue narrowExtractedVectorBinOp(EVT VT, SDValue Src, unsigned Index,
// bitcasted.
unsigned ConcatOpNum = Index / VT.getVectorNumElements();
unsigned ExtBOIdx = ConcatOpNum * NarrowBVT.getVectorNumElements();
- if (TLI.isExtractSubvectorCheap(NarrowBVT, WideBVT, ExtBOIdx) &&
+ if ((TLI.getExtractSubvectorCost(NarrowBVT, WideBVT, ExtBOIdx) < 2) &&
BinOp.hasOneUse() && Src->hasOneUse()) {
// extract (binop B0, B1), N --> binop (extract B0, N), (extract B1, N)
SDValue NewExtIndex = DAG.getVectorIdxConstant(ExtBOIdx, DL);
@@ -27988,7 +27988,7 @@ static SDValue foldExtractSubvectorFromShuffleVector(EVT NarrowVT, SDValue Src,
// How many elements into the WideVT does this subvector start?
int Index = NumEltsExtracted * OpSubvecIdx;
// Bail out if the extraction isn't going to be cheap.
- if (!TLI.isExtractSubvectorCheap(NarrowVT, WideVT, Index))
+ if (!(TLI.getExtractSubvectorCost(NarrowVT, WideVT, Index) < 2))
return SDValue();
}
@@ -28111,8 +28111,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
uint64_t NewExtIdx = InnerExtIdx + ExtIdx;
if (V.getValueType().isScalableVector() == NVT.isScalableVector() &&
NewExtIdx % NVT.getVectorMinNumElements() == 0 &&
- TLI.isExtractSubvectorCheap(NVT, V.getOperand(0).getValueType(),
- NewExtIdx) &&
+ (TLI.getExtractSubvectorCost(NVT, V.getOperand(0).getValueType(),
+ NewExtIdx) < 2) &&
TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT))
return DAG.getExtractSubvector(DL, NVT, V.getOperand(0), NewExtIdx);
}
@@ -28121,7 +28121,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
if (V.getOpcode() == ISD::SPLAT_VECTOR)
if ((DAG.isConstantValueOfAnyType(V.getOperand(0)) &&
!(NVT.isScalableVector() &&
- TLI.isExtractSubvectorCheap(NVT, V.getValueType(), ExtIdx))) ||
+ (TLI.getExtractSubvectorCost(NVT, V.getValueType(), ExtIdx) < 2))) ||
V.hasOneUse())
if (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, NVT))
return DAG.getSplatVector(NVT, DL, V.getOperand(0));
@@ -28145,7 +28145,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
unsigned InsIdx = V.getConstantOperandVal(2);
unsigned NumSubElts = NVT.getVectorMinNumElements();
if (InsIdx <= ExtIdx && (ExtIdx + NumSubElts) <= (InsIdx + NumInsElts) &&
- TLI.isExtractSubvectorCheap(NVT, InsSubVT, ExtIdx - InsIdx) &&
+ (TLI.getExtractSubvectorCost(NVT, InsSubVT, ExtIdx - InsIdx) < 2) &&
InsSubVT.isFixedLengthVector() && NVT.isFixedLengthVector() &&
V.getValueType().isFixedLengthVector())
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, InsSub,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 683cf2517b2f5..c58917c7807b5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -14217,7 +14217,7 @@ SelectionDAG::matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp,
EVT OpVT = Op.getValueType();
EVT OpSVT = OpVT.getScalarType();
EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts);
- if (!TLI->isExtractSubvectorCheap(SubVT, OpVT, 0))
+ if (!(TLI->getExtractSubvectorCost(SubVT, OpVT, 0) < 2))
return SDValue();
BinOp = (ISD::NodeType)CandidateBinOp;
return getExtractSubvector(SDLoc(Op), SubVT, Op, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 51be0e66b19b0..cf11773e7c10f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20290,12 +20290,14 @@ bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
return Shift < 3;
}
-bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned AArch64TargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return false;
+ return 2;
- return (Index == 0 || Index == ResVT.getVectorMinNumElements());
+ if (Index == 0 || Index == ResVT.getVectorMinNumElements())
+ return 0;
+ return 2;
}
bool AArch64TargetLowering::shouldOptimizeMulOverflowWithZeroHighBits(
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 35f7ef0e2151e..84eca294dbed7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -331,8 +331,8 @@ class AArch64TargetLowering : public TargetLowering {
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
/// with this index.
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 612342b159583..f854b0dcf1c76 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2404,13 +2404,15 @@ bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
return true;
}
-bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned SITargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return false;
+ return 2;
// TODO: Add more cases that are cheap.
- return Index == 0;
+ if (Index == 0)
+ return 0;
+ return 2;
}
bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 14f63325edde7..454e6a27ca1f7 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -404,8 +404,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index e2b39726c7c0d..97f1db8e2680e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -21496,12 +21496,14 @@ bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
return true;
}
-bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned ARMTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return false;
+ return 2;
- return (Index == 0 || Index == ResVT.getVectorNumElements());
+ if (Index == 0 || Index == ResVT.getVectorNumElements())
+ return 0;
+ return 2;
}
Instruction *ARMTargetLowering::makeDMB(IRBuilderBase &Builder,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 10f5442d7429b..c3179d513dee9 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -330,8 +330,8 @@ class VectorType;
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
/// with this index.
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 0e1b4d72eb03f..7458b4651f8ae 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2141,18 +2141,20 @@ bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
return false;
}
-bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned HexagonTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType());
if (!ResVT.isSimple() || !SrcVT.isSimple())
- return false;
+ return 2;
MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT();
if (ResTy.getVectorElementType() != MVT::i1)
- return true;
+ return 0;
// Non-HVX bool vectors are relatively cheap.
- return SrcTy.getVectorNumElements() <= 8;
+ if (SrcTy.getVectorNumElements() <= 8)
+ return 0;
+ return 2;
}
bool HexagonTargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index cf2263fdc2ad8..872edbcc8db8a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -78,8 +78,8 @@ class HexagonTargetLowering : public TargetLowering {
// Should we expand the build vector with shuffles?
bool shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const override;
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isTargetCanonicalConstantNode(SDValue Op) const override;
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 38f46a9fc9855..36f8b881439e3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -11787,13 +11787,16 @@ bool LoongArchTargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
}
-bool LoongArchTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned
+LoongArchTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return false;
+ return 2;
// Extract a 128-bit subvector from index 0 of a 256-bit vector is free.
- return Index == 0;
+ if (Index == 0)
+ return 0;
+ return 2;
}
bool LoongArchTargetLowering::isExtractVecEltCheap(EVT VT,
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 32e32ab9148af..486277100a4f5 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -169,8 +169,8 @@ class LoongArchTargetLowering : public TargetLowering {
unsigned Depth) const override;
bool shouldScalarizeBinop(SDValue VecOp) const override;
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
/// Check if a constant splat can be generated using [x]vldi, where imm[12]
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e23427482c1e4..2e74f4755aee3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2865,32 +2865,35 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
}
// TODO: This is very conservative.
-bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned RISCVTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (Subtarget.hasStdExtP() && !Subtarget.is64Bit() &&
- (ResVT == MVT::v4i8 || ResVT == MVT::v2i16))
- return (Index % ResVT.getVectorNumElements()) == 0;
+ (ResVT == MVT::v4i8 || ResVT == MVT::v2i16)) {
+ if ((Index % ResVT.getVectorNumElements()) == 0)
+ return 0;
+ return 2;
+ }
if (!Subtarget.hasVInstructions())
- return false;
+ return 2;
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return false;
+ return 2;
// Extracts from index 0 are just subreg extracts.
if (Index == 0)
- return true;
+ return 0;
// Only support extracting a fixed from a fixed vector for now.
if (ResVT.isScalableVector() || SrcVT.isScalableVector())
- return false;
+ return 2;
EVT EltVT = ResVT.getVectorElementType();
assert(EltVT == SrcVT.getVectorElementType() && "Should hold for node");
// The smallest type we can slide is i8.
if (EltVT == MVT::i1)
- return false;
+ return 2;
unsigned ResElts = ResVT.getVectorNumElements();
unsigned SrcElts = SrcVT.getVectorNumElements();
@@ -2903,7 +2906,7 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
// Index ensures we can use a vslidedown.vi.
// TODO: We can generalize this when the exact VLEN is known.
if (Index + ResElts <= MinVLMAX && Index < 31)
- return true;
+ return 0;
// Convervatively only handle extracting half of a vector.
// TODO: We can do arbitrary slidedowns, but for now only support extracting
@@ -2911,7 +2914,9 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
// TODO: For sizes which aren't multiples of VLEN sizes, this may not be
// a cheap extract. However, this case is important in practice for
// shuffled extracts of longer vectors. How resolve?
- return (ResElts * 2) == SrcElts && Index == ResElts;
+ if ((ResElts * 2) == SrcElts && Index == ResElts)
+ return 0;
+ return 2;
}
MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 2ca7c392639f7..09c1d88bcd780 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -64,8 +64,8 @@ class RISCVTargetLowering : public TargetLowering {
int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 44c847565cb69..5a993dfc0b43c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3604,19 +3604,23 @@ bool X86TargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
(1 - MulC).isPowerOf2() || (-(MulC + 1)).isPowerOf2();
}
-bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+unsigned X86TargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return false;
+ return 2;
// Mask vectors support all subregister combinations and operations that
// extract half of vector.
- if (ResVT.getVectorElementType() == MVT::i1)
- return Index == 0 ||
- ((ResVT.getSizeInBits() * 2 == SrcVT.getSizeInBits()) &&
- (Index == ResVT.getVectorNumElements()));
+ if (ResVT.getVectorElementType() == MVT::i1) {
+ if (Index == 0 || ((ResVT.getSizeInBits() * 2 == SrcVT.getSizeInBits()) &&
+ (Index == ResVT.getVectorNumElements())))
+ return 0;
+ return 2;
+ }
- return (Index % ResVT.getVectorNumElements()) == 0;
+ if ((Index % ResVT.getVectorNumElements()) == 0)
+ return 0;
+ return 2;
}
bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 798050028c15a..af82869c8681e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -578,8 +578,8 @@ namespace llvm {
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
/// with this index.
- bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
/// Scalar ops always have equal or better analysis/performance/power than
/// the vector equivalent, so this always makes sense if the scalar op is
>From f2e2b1cec37f6e2d1fceafa1c4d9cb39a170f18c Mon Sep 17 00:00:00 2001
From: shore <shorshen at amd.com>
Date: Mon, 3 Aug 2026 18:29:17 +0800
Subject: [PATCH 2/2] use enum
---
llvm/include/llvm/CodeGen/TargetLowering.h | 32 +++++++++++--------
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 26 +++++++++------
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +-
.../Target/AArch64/AArch64ISelLowering.cpp | 11 ++++---
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 8 ++---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 11 ++++---
llvm/lib/Target/AMDGPU/SIISelLowering.h | 4 +--
llvm/lib/Target/ARM/ARMISelLowering.cpp | 11 ++++---
llvm/lib/Target/ARM/ARMISelLowering.h | 8 ++---
.../Target/Hexagon/HexagonISelLowering.cpp | 13 ++++----
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 4 +--
.../LoongArch/LoongArchISelLowering.cpp | 8 ++---
.../Target/LoongArch/LoongArchISelLowering.h | 4 +--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 25 ++++++++-------
llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 +--
llvm/lib/Target/X86/X86ISelLowering.cpp | 15 +++++----
llvm/lib/Target/X86/X86ISelLowering.h | 8 ++---
17 files changed, 107 insertions(+), 88 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 80a7f7b770f64..54ecf9142d94e 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -307,6 +307,16 @@ class LLVM_ABI TargetLoweringBase {
Expensive = 2 // Negated expression is more expensive.
};
+ /// Enum that specifies how expensive lowering an EXTRACT_SUBVECTOR is.
+ enum class ExtractSubvectorCost {
+ Free = 0, // Lowers to no instruction at all, e.g. a subregister copy.
+ Cheap = 1, // Lowers to at most one instruction, and may still be free if
+ // the target can fold the extract into the instruction
+ // consuming it (e.g. a widening op that reads the high half of
+ // a register).
+ Expensive = 2 // Needs a shuffle sequence that cannot be folded away.
+ };
+
/// Enum of different potentially desirable ways to fold (and/or (setcc ...),
/// (setcc ...)).
enum AndOrSETCCFoldKind : uint8_t {
@@ -3541,21 +3551,15 @@ class LLVM_ABI TargetLoweringBase {
}
/// Return the cost of extracting a subvector of type \p ResVT from a vector
- /// of type \p SrcVT, starting at element \p Index:
- ///
- /// 0 - Free: lowers to no instruction at all, e.g. a subregister copy.
- /// 1 - Cheap: lowers to at most one instruction, and may still be free if
- /// the target can fold the extract into the instruction consuming it
- /// (e.g. a widening op that reads the high half of a register).
- /// 2 - Expensive: needs a shuffle sequence that cannot be folded away.
+ /// of type \p SrcVT, starting at element \p Index.
///
- /// Most callers only create a new EXTRACT_SUBVECTOR when the cost is below
- /// 2. This hook exists because EXTRACT_SUBVECTOR usually has custom lowering
- /// that depends on the index of the first element, so only the target knows
- /// which lowering is cheap.
- virtual unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
- return 2;
+ /// Most callers only create a new EXTRACT_SUBVECTOR when the cost is at most
+ /// ExtractSubvectorCost::Cheap. This hook exists because EXTRACT_SUBVECTOR
+ /// usually has custom lowering that depends on the index of the first
+ /// element, so only the target knows which lowering is cheap.
+ virtual ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
+ return ExtractSubvectorCost::Expensive;
}
/// Try to convert an extract element of a vector binary operation into an
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d15598da732ef..4ef90964d4c1e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -21843,7 +21843,8 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
InterVT.getVectorNumElements() - LDMemType.getVectorNumElements();
}
- if (!(TLI.getExtractSubvectorCost(LDMemType, InterVT, ExtIdx) < 2))
+ if (TLI.getExtractSubvectorCost(LDMemType, InterVT, ExtIdx) >
+ TargetLowering::ExtractSubvectorCost::Cheap)
break;
Val = DAG.getExtractSubvector(SDLoc(LD), LDMemType,
DAG.getBitcast(InterVT, Val), ExtIdx);
@@ -26262,7 +26263,8 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
VecIn2 = SDValue();
} else if (InVT1Size == VTSize * 2) {
- if (!(TLI.getExtractSubvectorCost(VT, InVT1, NumElems) < 2))
+ if (TLI.getExtractSubvectorCost(VT, InVT1, NumElems) >
+ TargetLowering::ExtractSubvectorCost::Cheap)
return SDValue();
if (!VecIn2.getNode()) {
@@ -26301,7 +26303,8 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N,
ConcatOps[0] = VecIn2;
VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
} else if (InVT1Size / VTSize > 1 && InVT1Size % VTSize == 0) {
- if (!(TLI.getExtractSubvectorCost(VT, InVT1, NumElems) < 2) ||
+ if (TLI.getExtractSubvectorCost(VT, InVT1, NumElems) >
+ TargetLowering::ExtractSubvectorCost::Cheap ||
!TLI.isTypeLegal(InVT1) || !TLI.isTypeLegal(InVT2))
return SDValue();
// If dest vector has less than two elements, then use shuffle and extract
@@ -27777,7 +27780,8 @@ static SDValue narrowExtractedVectorBinOp(EVT VT, SDValue Src, unsigned Index,
// bitcasted.
unsigned ConcatOpNum = Index / VT.getVectorNumElements();
unsigned ExtBOIdx = ConcatOpNum * NarrowBVT.getVectorNumElements();
- if ((TLI.getExtractSubvectorCost(NarrowBVT, WideBVT, ExtBOIdx) < 2) &&
+ if (TLI.getExtractSubvectorCost(NarrowBVT, WideBVT, ExtBOIdx) <=
+ TargetLowering::ExtractSubvectorCost::Cheap &&
BinOp.hasOneUse() && Src->hasOneUse()) {
// extract (binop B0, B1), N --> binop (extract B0, N), (extract B1, N)
SDValue NewExtIndex = DAG.getVectorIdxConstant(ExtBOIdx, DL);
@@ -27988,7 +27992,8 @@ static SDValue foldExtractSubvectorFromShuffleVector(EVT NarrowVT, SDValue Src,
// How many elements into the WideVT does this subvector start?
int Index = NumEltsExtracted * OpSubvecIdx;
// Bail out if the extraction isn't going to be cheap.
- if (!(TLI.getExtractSubvectorCost(NarrowVT, WideVT, Index) < 2))
+ if (TLI.getExtractSubvectorCost(NarrowVT, WideVT, Index) >
+ TargetLowering::ExtractSubvectorCost::Cheap)
return SDValue();
}
@@ -28111,8 +28116,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
uint64_t NewExtIdx = InnerExtIdx + ExtIdx;
if (V.getValueType().isScalableVector() == NVT.isScalableVector() &&
NewExtIdx % NVT.getVectorMinNumElements() == 0 &&
- (TLI.getExtractSubvectorCost(NVT, V.getOperand(0).getValueType(),
- NewExtIdx) < 2) &&
+ TLI.getExtractSubvectorCost(NVT, V.getOperand(0).getValueType(),
+ NewExtIdx) <=
+ TargetLowering::ExtractSubvectorCost::Cheap &&
TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT))
return DAG.getExtractSubvector(DL, NVT, V.getOperand(0), NewExtIdx);
}
@@ -28121,7 +28127,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
if (V.getOpcode() == ISD::SPLAT_VECTOR)
if ((DAG.isConstantValueOfAnyType(V.getOperand(0)) &&
!(NVT.isScalableVector() &&
- (TLI.getExtractSubvectorCost(NVT, V.getValueType(), ExtIdx) < 2))) ||
+ TLI.getExtractSubvectorCost(NVT, V.getValueType(), ExtIdx) <=
+ TargetLowering::ExtractSubvectorCost::Cheap)) ||
V.hasOneUse())
if (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, NVT))
return DAG.getSplatVector(NVT, DL, V.getOperand(0));
@@ -28145,7 +28152,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
unsigned InsIdx = V.getConstantOperandVal(2);
unsigned NumSubElts = NVT.getVectorMinNumElements();
if (InsIdx <= ExtIdx && (ExtIdx + NumSubElts) <= (InsIdx + NumInsElts) &&
- (TLI.getExtractSubvectorCost(NVT, InsSubVT, ExtIdx - InsIdx) < 2) &&
+ TLI.getExtractSubvectorCost(NVT, InsSubVT, ExtIdx - InsIdx) <=
+ TargetLowering::ExtractSubvectorCost::Cheap &&
InsSubVT.isFixedLengthVector() && NVT.isFixedLengthVector() &&
V.getValueType().isFixedLengthVector())
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, InsSub,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c58917c7807b5..630df49259092 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -14217,7 +14217,8 @@ SelectionDAG::matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp,
EVT OpVT = Op.getValueType();
EVT OpSVT = OpVT.getScalarType();
EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts);
- if (!(TLI->getExtractSubvectorCost(SubVT, OpVT, 0) < 2))
+ if (TLI->getExtractSubvectorCost(SubVT, OpVT, 0) >
+ TargetLowering::ExtractSubvectorCost::Cheap)
return SDValue();
BinOp = (ISD::NodeType)CandidateBinOp;
return getExtractSubvector(SDLoc(Op), SubVT, Op, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index cf11773e7c10f..718eaa5fe97af 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20290,14 +20290,15 @@ bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
return Shift < 3;
}
-unsigned AArch64TargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+AArch64TargetLowering::ExtractSubvectorCost
+AArch64TargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return 2;
+ return ExtractSubvectorCost::Expensive;
if (Index == 0 || Index == ResVT.getVectorMinNumElements())
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
bool AArch64TargetLowering::shouldOptimizeMulOverflowWithZeroHighBits(
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 84eca294dbed7..66a6261d2a991 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -329,10 +329,10 @@ class AArch64TargetLowering : public TargetLowering {
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
- /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
- /// with this index.
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ /// Return the cost of EXTRACT_SUBVECTOR for this result type with this
+ /// index.
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f854b0dcf1c76..72f3338f107d1 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2404,15 +2404,16 @@ bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
return true;
}
-unsigned SITargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+SITargetLowering::ExtractSubvectorCost
+SITargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return 2;
+ return ExtractSubvectorCost::Expensive;
// TODO: Add more cases that are cheap.
if (Index == 0)
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 454e6a27ca1f7..7037cf1410f63 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -404,8 +404,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 97f1db8e2680e..f013bc76e428e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -21496,14 +21496,15 @@ bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
return true;
}
-unsigned ARMTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+ARMTargetLowering::ExtractSubvectorCost
+ARMTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return 2;
+ return ExtractSubvectorCost::Expensive;
if (Index == 0 || Index == ResVT.getVectorNumElements())
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
Instruction *ARMTargetLowering::makeDMB(IRBuilderBase &Builder,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index c3179d513dee9..2bbb91a8758e2 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -328,10 +328,10 @@ class VectorType;
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
- /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
- /// with this index.
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ /// Return the cost of EXTRACT_SUBVECTOR for this result type with this
+ /// index.
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 7458b4651f8ae..5b6127040c5e8 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2141,20 +2141,21 @@ bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
return false;
}
-unsigned HexagonTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+HexagonTargetLowering::ExtractSubvectorCost
+HexagonTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType());
if (!ResVT.isSimple() || !SrcVT.isSimple())
- return 2;
+ return ExtractSubvectorCost::Expensive;
MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT();
if (ResTy.getVectorElementType() != MVT::i1)
- return 0;
+ return ExtractSubvectorCost::Free;
// Non-HVX bool vectors are relatively cheap.
if (SrcTy.getVectorNumElements() <= 8)
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
bool HexagonTargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 872edbcc8db8a..8e7d31b20a892 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -78,8 +78,8 @@ class HexagonTargetLowering : public TargetLowering {
// Should we expand the build vector with shuffles?
bool shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const override;
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isTargetCanonicalConstantNode(SDValue Op) const override;
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 36f8b881439e3..7d43635348914 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -11787,16 +11787,16 @@ bool LoongArchTargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
return isOperationLegalOrCustomOrPromote(Opc, ScalarVT);
}
-unsigned
+LoongArchTargetLowering::ExtractSubvectorCost
LoongArchTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return 2;
+ return ExtractSubvectorCost::Expensive;
// Extract a 128-bit subvector from index 0 of a 256-bit vector is free.
if (Index == 0)
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
bool LoongArchTargetLowering::isExtractVecEltCheap(EVT VT,
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 486277100a4f5..b30bdeef1812c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -169,8 +169,8 @@ class LoongArchTargetLowering : public TargetLowering {
unsigned Depth) const override;
bool shouldScalarizeBinop(SDValue VecOp) const override;
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
/// Check if a constant splat can be generated using [x]vldi, where imm[12]
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2e74f4755aee3..7db68caac2de4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2865,35 +2865,36 @@ bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
}
// TODO: This is very conservative.
-unsigned RISCVTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+RISCVTargetLowering::ExtractSubvectorCost
+RISCVTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (Subtarget.hasStdExtP() && !Subtarget.is64Bit() &&
(ResVT == MVT::v4i8 || ResVT == MVT::v2i16)) {
if ((Index % ResVT.getVectorNumElements()) == 0)
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
if (!Subtarget.hasVInstructions())
- return 2;
+ return ExtractSubvectorCost::Expensive;
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return 2;
+ return ExtractSubvectorCost::Expensive;
// Extracts from index 0 are just subreg extracts.
if (Index == 0)
- return 0;
+ return ExtractSubvectorCost::Free;
// Only support extracting a fixed from a fixed vector for now.
if (ResVT.isScalableVector() || SrcVT.isScalableVector())
- return 2;
+ return ExtractSubvectorCost::Expensive;
EVT EltVT = ResVT.getVectorElementType();
assert(EltVT == SrcVT.getVectorElementType() && "Should hold for node");
// The smallest type we can slide is i8.
if (EltVT == MVT::i1)
- return 2;
+ return ExtractSubvectorCost::Expensive;
unsigned ResElts = ResVT.getVectorNumElements();
unsigned SrcElts = SrcVT.getVectorNumElements();
@@ -2906,7 +2907,7 @@ unsigned RISCVTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
// Index ensures we can use a vslidedown.vi.
// TODO: We can generalize this when the exact VLEN is known.
if (Index + ResElts <= MinVLMAX && Index < 31)
- return 0;
+ return ExtractSubvectorCost::Free;
// Convervatively only handle extracting half of a vector.
// TODO: We can do arbitrary slidedowns, but for now only support extracting
@@ -2915,8 +2916,8 @@ unsigned RISCVTargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
// a cheap extract. However, this case is important in practice for
// shuffled extracts of longer vectors. How resolve?
if ((ResElts * 2) == SrcElts && Index == ResElts)
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 09c1d88bcd780..972cc256a3386 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -64,8 +64,8 @@ class RISCVTargetLowering : public TargetLowering {
int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5a993dfc0b43c..4047877b0ece1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3604,23 +3604,24 @@ bool X86TargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
(1 - MulC).isPowerOf2() || (-(MulC + 1)).isPowerOf2();
}
-unsigned X86TargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
+X86TargetLowering::ExtractSubvectorCost
+X86TargetLowering::getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
- return 2;
+ return ExtractSubvectorCost::Expensive;
// Mask vectors support all subregister combinations and operations that
// extract half of vector.
if (ResVT.getVectorElementType() == MVT::i1) {
if (Index == 0 || ((ResVT.getSizeInBits() * 2 == SrcVT.getSizeInBits()) &&
(Index == ResVT.getVectorNumElements())))
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
if ((Index % ResVT.getVectorNumElements()) == 0)
- return 0;
- return 2;
+ return ExtractSubvectorCost::Free;
+ return ExtractSubvectorCost::Expensive;
}
bool X86TargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index af82869c8681e..a4b4e6f32591b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -576,10 +576,10 @@ namespace llvm {
bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
SDValue C) const override;
- /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
- /// with this index.
- unsigned getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
- unsigned Index) const override;
+ /// Return the cost of EXTRACT_SUBVECTOR for this result type with this
+ /// index.
+ ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
/// Scalar ops always have equal or better analysis/performance/power than
/// the vector equivalent, so this always makes sense if the scalar op is
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