[llvm] [X86] Add PSEUDO_FMIN/PSEUDO_FMAX to canCombineAsMaskOperation (PR #213475)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 3 02:19:54 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/213475
>From 95fd23253f1e689acd613edf2242466a9e87d61d Mon Sep 17 00:00:00 2001
From: Timur Golubovich <timur.golubovich at intel.com>
Date: Sat, 1 Aug 2026 20:14:20 +0200
Subject: [PATCH] [X86] Add PSEUDO_FMIN/PSEUDO_FMAX to
canCombineAsMaskOperation
Add FP min/max opcodes to the list of operations that can be folded
into write-masked instructions. This allows commuteSelect to
recognize these operations and invert the setcc condition to enable
ISel to match fused vminps/vmaxps {%k} patterns.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +
.../X86/avx512-maxnum-minnum-masked-store.ll | 16 +--
llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll | 35 +++---
llvm/test/CodeGen/X86/avx512fp16-fminnum.ll | 35 +++---
.../CodeGen/X86/expand-vp-fp-intrinsics.ll | 28 ++---
llvm/test/CodeGen/X86/fmaxnum.ll | 109 ++++++++++++------
llvm/test/CodeGen/X86/fminnum.ll | 109 ++++++++++++------
llvm/test/CodeGen/X86/vector-reduce-fmax.ll | 45 ++++----
llvm/test/CodeGen/X86/vector-reduce-fmin.ll | 45 ++++----
9 files changed, 238 insertions(+), 186 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 44c847565cb69..4bb22b89068c2 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18457,6 +18457,8 @@ static bool canCombineAsMaskOperation(SDValue V,
case ISD::SRL:
case ISD::SRA:
case ISD::MUL:
+ case ISD::PSEUDO_FMIN:
+ case ISD::PSEUDO_FMAX:
break;
}
if (!V->hasOneUse())
diff --git a/llvm/test/CodeGen/X86/avx512-maxnum-minnum-masked-store.ll b/llvm/test/CodeGen/X86/avx512-maxnum-minnum-masked-store.ll
index f6ca1490b558c..c190ec1bc719d 100644
--- a/llvm/test/CodeGen/X86/avx512-maxnum-minnum-masked-store.ll
+++ b/llvm/test/CodeGen/X86/avx512-maxnum-minnum-masked-store.ll
@@ -27,8 +27,8 @@ define void @maxnum_v4f32_masked_store(<4 x float> %a, ptr %ptr) {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovups (%rdi), %xmm1
; AVX512F-NEXT: vmaxps %xmm0, %xmm1, %xmm1
-; AVX512F-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
-; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0
+; AVX512F-NEXT: vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovups %zmm1, (%rdi) {%k1}
@@ -61,8 +61,8 @@ define void @maxnum_v2f64_masked_store(<2 x double> %a, ptr %ptr) {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovupd (%rdi), %xmm1
; AVX512F-NEXT: vmaxpd %xmm0, %xmm1, %xmm1
-; AVX512F-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
-; AVX512F-NEXT: vptestnmq %zmm0, %zmm0, %k0
+; AVX512F-NEXT: vcmpordpd %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k0
; AVX512F-NEXT: kshiftrw $14, %k0, %k1
; AVX512F-NEXT: vmovupd %zmm1, (%rdi) {%k1}
@@ -95,8 +95,8 @@ define void @minnum_v4f32_masked_store(<4 x float> %a, ptr %ptr) {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovups (%rdi), %xmm1
; AVX512F-NEXT: vminps %xmm0, %xmm1, %xmm1
-; AVX512F-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
-; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0
+; AVX512F-NEXT: vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovups %zmm1, (%rdi) {%k1}
@@ -129,8 +129,8 @@ define void @minnum_v2f64_masked_store(<2 x double> %a, ptr %ptr) {
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovupd (%rdi), %xmm1
; AVX512F-NEXT: vminpd %xmm0, %xmm1, %xmm1
-; AVX512F-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
-; AVX512F-NEXT: vptestnmq %zmm0, %zmm0, %k0
+; AVX512F-NEXT: vcmpordpd %xmm0, %xmm0, %xmm0
+; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k0
; AVX512F-NEXT: kshiftrw $14, %k0, %k1
; AVX512F-NEXT: vmovupd %zmm1, (%rdi) {%k1}
diff --git a/llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll b/llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll
index d941930e4dadf..0a9079894e220 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll
@@ -32,10 +32,9 @@ define half @test_intrinsic_fmaxh(half %x, half %y) {
define <2 x half> @test_intrinsic_fmax_v2f16(<2 x half> %x, <2 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmax_v2f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vmaxph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5f,0xd0]
-; HasVL-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x07]
+; HasVL-NEXT: vmaxph %xmm0, %xmm1, %xmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x09,0x5f,0xc8]
+; HasVL-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmax_v2f16:
@@ -110,10 +109,9 @@ define <2 x half> @test_intrinsic_fmax_v2f16(<2 x half> %x, <2 x half> %y) {
define <4 x half> @test_intrinsic_fmax_v4f16(<4 x half> %x, <4 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmax_v4f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vmaxph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5f,0xd0]
-; HasVL-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x07]
+; HasVL-NEXT: vmaxph %xmm0, %xmm1, %xmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x09,0x5f,0xc8]
+; HasVL-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmax_v4f16:
@@ -188,10 +186,9 @@ define <4 x half> @test_intrinsic_fmax_v4f16(<4 x half> %x, <4 x half> %y) {
define <8 x half> @test_intrinsic_fmax_v8f16(<8 x half> %x, <8 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmax_v8f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vmaxph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5f,0xd0]
-; HasVL-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x07]
+; HasVL-NEXT: vmaxph %xmm0, %xmm1, %xmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x09,0x5f,0xc8]
+; HasVL-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmax_v8f16:
@@ -266,10 +263,9 @@ define <8 x half> @test_intrinsic_fmax_v8f16(<8 x half> %x, <8 x half> %y) {
define <16 x half> @test_intrinsic_fmax_v16f16(<16 x half> %x, <16 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmax_v16f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vmaxph %ymm0, %ymm1, %ymm2 # encoding: [0x62,0xf5,0x74,0x28,0x5f,0xd0]
-; HasVL-NEXT: vcmpunordph %ymm0, %ymm0, %k1 # encoding: [0x62,0xf3,0x7c,0x28,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %ymm1, %ymm2 {%k1} # encoding: [0x62,0xf1,0xff,0x29,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %ymm0, %ymm0, %k1 # encoding: [0x62,0xf3,0x7c,0x28,0xc2,0xc8,0x07]
+; HasVL-NEXT: vmaxph %ymm0, %ymm1, %ymm1 {%k1} # encoding: [0x62,0xf5,0x74,0x29,0x5f,0xc8]
+; HasVL-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmax_v16f16:
@@ -408,10 +404,9 @@ define <16 x half> @test_intrinsic_fmax_v16f16(<16 x half> %x, <16 x half> %y) {
define <32 x half> @test_intrinsic_fmax_v32f16(<32 x half> %x, <32 x half> %y) {
; CHECK-LABEL: test_intrinsic_fmax_v32f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmaxph %zmm0, %zmm1, %zmm2 # encoding: [0x62,0xf5,0x74,0x48,0x5f,0xd0]
-; CHECK-NEXT: vcmpunordph %zmm0, %zmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x48,0xc2,0xc8,0x03]
-; CHECK-NEXT: vmovdqu16 %zmm1, %zmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x49,0x6f,0xd1]
-; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; CHECK-NEXT: vcmpordph %zmm0, %zmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x48,0xc2,0xc8,0x07]
+; CHECK-NEXT: vmaxph %zmm0, %zmm1, %zmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x49,0x5f,0xc8]
+; CHECK-NEXT: vmovaps %zmm1, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
; CHECK-NEXT: retq # encoding: [0xc3]
%z = call <32 x half> @llvm.maxnum.v32f16(<32 x half> %x, <32 x half> %y) readnone
ret <32 x half> %z
diff --git a/llvm/test/CodeGen/X86/avx512fp16-fminnum.ll b/llvm/test/CodeGen/X86/avx512fp16-fminnum.ll
index 3df6ee4e85f01..9cddf4b013c56 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-fminnum.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-fminnum.ll
@@ -32,10 +32,9 @@ define half @test_intrinsic_fminh(half %x, half %y) {
define <2 x half> @test_intrinsic_fmin_v2f16(<2 x half> %x, <2 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmin_v2f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vminph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5d,0xd0]
-; HasVL-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x07]
+; HasVL-NEXT: vminph %xmm0, %xmm1, %xmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x09,0x5d,0xc8]
+; HasVL-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmin_v2f16:
@@ -110,10 +109,9 @@ define <2 x half> @test_intrinsic_fmin_v2f16(<2 x half> %x, <2 x half> %y) {
define <4 x half> @test_intrinsic_fmin_v4f16(<4 x half> %x, <4 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmin_v4f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vminph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5d,0xd0]
-; HasVL-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x07]
+; HasVL-NEXT: vminph %xmm0, %xmm1, %xmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x09,0x5d,0xc8]
+; HasVL-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmin_v4f16:
@@ -188,10 +186,9 @@ define <4 x half> @test_intrinsic_fmin_v4f16(<4 x half> %x, <4 x half> %y) {
define <8 x half> @test_intrinsic_fmin_v8f16(<8 x half> %x, <8 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmin_v8f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vminph %xmm0, %xmm1, %xmm2 # encoding: [0x62,0xf5,0x74,0x08,0x5d,0xd0]
-; HasVL-NEXT: vcmpunordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x09,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %xmm0, %xmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x08,0xc2,0xc8,0x07]
+; HasVL-NEXT: vminph %xmm0, %xmm1, %xmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x09,0x5d,0xc8]
+; HasVL-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmin_v8f16:
@@ -266,10 +263,9 @@ define <8 x half> @test_intrinsic_fmin_v8f16(<8 x half> %x, <8 x half> %y) {
define <16 x half> @test_intrinsic_fmin_v16f16(<16 x half> %x, <16 x half> %y) {
; HasVL-LABEL: test_intrinsic_fmin_v16f16:
; HasVL: # %bb.0:
-; HasVL-NEXT: vminph %ymm0, %ymm1, %ymm2 # encoding: [0x62,0xf5,0x74,0x28,0x5d,0xd0]
-; HasVL-NEXT: vcmpunordph %ymm0, %ymm0, %k1 # encoding: [0x62,0xf3,0x7c,0x28,0xc2,0xc8,0x03]
-; HasVL-NEXT: vmovdqu16 %ymm1, %ymm2 {%k1} # encoding: [0x62,0xf1,0xff,0x29,0x6f,0xd1]
-; HasVL-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; HasVL-NEXT: vcmpordph %ymm0, %ymm0, %k1 # encoding: [0x62,0xf3,0x7c,0x28,0xc2,0xc8,0x07]
+; HasVL-NEXT: vminph %ymm0, %ymm1, %ymm1 {%k1} # encoding: [0x62,0xf5,0x74,0x29,0x5d,0xc8]
+; HasVL-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; HasVL-NEXT: retq # encoding: [0xc3]
;
; NOVL-LABEL: test_intrinsic_fmin_v16f16:
@@ -408,10 +404,9 @@ define <16 x half> @test_intrinsic_fmin_v16f16(<16 x half> %x, <16 x half> %y) {
define <32 x half> @test_intrinsic_fmin_v32f16(<32 x half> %x, <32 x half> %y) {
; CHECK-LABEL: test_intrinsic_fmin_v32f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vminph %zmm0, %zmm1, %zmm2 # encoding: [0x62,0xf5,0x74,0x48,0x5d,0xd0]
-; CHECK-NEXT: vcmpunordph %zmm0, %zmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x48,0xc2,0xc8,0x03]
-; CHECK-NEXT: vmovdqu16 %zmm1, %zmm2 {%k1} # encoding: [0x62,0xf1,0xff,0x49,0x6f,0xd1]
-; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; CHECK-NEXT: vcmpordph %zmm0, %zmm0, %k1 # encoding: [0x62,0xf3,0x7c,0x48,0xc2,0xc8,0x07]
+; CHECK-NEXT: vminph %zmm0, %zmm1, %zmm1 {%k1} # encoding: [0x62,0xf5,0x74,0x49,0x5d,0xc8]
+; CHECK-NEXT: vmovaps %zmm1, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
; CHECK-NEXT: retq # encoding: [0xc3]
%z = call <32 x half> @llvm.minnum.v32f16(<32 x half> %x, <32 x half> %y) readnone
ret <32 x half> %z
diff --git a/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll b/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll
index 018b6c2d20f1e..1e0eaa4526cce 100644
--- a/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll
@@ -588,10 +588,9 @@ define <4 x float> @vfmax_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m
;
; AVX512-LABEL: vfmax_vv_v4f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmaxps %xmm0, %xmm1, %xmm2
-; AVX512-NEXT: vcmpunordps %xmm0, %xmm0, %k1
-; AVX512-NEXT: vmovaps %xmm1, %xmm2 {%k1}
-; AVX512-NEXT: vmovaps %xmm2, %xmm0
+; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %k1
+; AVX512-NEXT: vmaxps %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512-NEXT: vmovaps %xmm1, %xmm0
; AVX512-NEXT: retq
%v = call <4 x float> @llvm.vp.maxnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -638,10 +637,9 @@ define <8 x float> @vfmax_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m
;
; AVX512-LABEL: vfmax_vv_v8f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmaxps %ymm0, %ymm1, %ymm2
-; AVX512-NEXT: vcmpunordps %ymm0, %ymm0, %k1
-; AVX512-NEXT: vmovaps %ymm1, %ymm2 {%k1}
-; AVX512-NEXT: vmovaps %ymm2, %ymm0
+; AVX512-NEXT: vcmpordps %ymm0, %ymm0, %k1
+; AVX512-NEXT: vmaxps %ymm0, %ymm1, %ymm1 {%k1}
+; AVX512-NEXT: vmovaps %ymm1, %ymm0
; AVX512-NEXT: retq
%v = call <8 x float> @llvm.vp.maxnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
@@ -682,10 +680,9 @@ define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m
;
; AVX512-LABEL: vfmin_vv_v4f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vminps %xmm0, %xmm1, %xmm2
-; AVX512-NEXT: vcmpunordps %xmm0, %xmm0, %k1
-; AVX512-NEXT: vmovaps %xmm1, %xmm2 {%k1}
-; AVX512-NEXT: vmovaps %xmm2, %xmm0
+; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %k1
+; AVX512-NEXT: vminps %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512-NEXT: vmovaps %xmm1, %xmm0
; AVX512-NEXT: retq
%v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -732,10 +729,9 @@ define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m
;
; AVX512-LABEL: vfmin_vv_v8f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vminps %ymm0, %ymm1, %ymm2
-; AVX512-NEXT: vcmpunordps %ymm0, %ymm0, %k1
-; AVX512-NEXT: vmovaps %ymm1, %ymm2 {%k1}
-; AVX512-NEXT: vmovaps %ymm2, %ymm0
+; AVX512-NEXT: vcmpordps %ymm0, %ymm0, %k1
+; AVX512-NEXT: vminps %ymm0, %ymm1, %ymm1 {%k1}
+; AVX512-NEXT: vmovaps %ymm1, %ymm0
; AVX512-NEXT: retq
%v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
diff --git a/llvm/test/CodeGen/X86/fmaxnum.ll b/llvm/test/CodeGen/X86/fmaxnum.ll
index 59d1b5b5232b6..7dabc74b1d40a 100644
--- a/llvm/test/CodeGen/X86/fmaxnum.ll
+++ b/llvm/test/CodeGen/X86/fmaxnum.ll
@@ -196,12 +196,19 @@ define <2 x float> @test_intrinsic_fmax_v2f32(<2 x float> %x, <2 x float> %y) {
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmax_v2f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmax_v2f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxps %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmax_v2f32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmaxps %xmm0, %xmm1, %xmm2
+; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
%z = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
ret <2 x float> %z
}
@@ -226,12 +233,19 @@ define <4 x float> @test_intrinsic_fmax_v4f32(<4 x float> %x, <4 x float> %y) {
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmax_v4f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmax_v4f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxps %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmax_v4f32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmaxps %xmm0, %xmm1, %xmm2
+; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
%z = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
ret <4 x float> %z
}
@@ -268,12 +282,19 @@ define <8 x float> @test_intrinsic_fmax_v8f32(<8 x float> %x, <8 x float> %y) {
; SSE4-NEXT: movaps %xmm4, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmax_v8f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxps %ymm0, %ymm1, %ymm2
-; AVX-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
-; AVX-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmax_v8f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxps %ymm0, %ymm1, %ymm2
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
+; AVX1-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmax_v8f32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmaxps %ymm0, %ymm1, %ymm2
+; AVX512-NEXT: vcmpordps %ymm0, %ymm0, %ymm0
+; AVX512-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
+; AVX512-NEXT: retq
%z = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
ret <8 x float> %z
}
@@ -346,10 +367,9 @@ define <16 x float> @test_intrinsic_fmax_v16f32(<16 x float> %x, <16 x float> %y
;
; AVX512-LABEL: test_intrinsic_fmax_v16f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmaxps %zmm0, %zmm1, %zmm2
-; AVX512-NEXT: vcmpunordps %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovaps %zmm1, %zmm2 {%k1}
-; AVX512-NEXT: vmovaps %zmm2, %zmm0
+; AVX512-NEXT: vcmpordps %zmm0, %zmm0, %k1
+; AVX512-NEXT: vmaxps %zmm0, %zmm1, %zmm1 {%k1}
+; AVX512-NEXT: vmovaps %zmm1, %zmm0
; AVX512-NEXT: retq
%z = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %x, <16 x float> %y) readnone
ret <16 x float> %z
@@ -375,12 +395,19 @@ define <2 x double> @test_intrinsic_fmax_v2f64(<2 x double> %x, <2 x double> %y)
; SSE4-NEXT: movapd %xmm2, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmax_v2f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxpd %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmax_v2f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxpd %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmax_v2f64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmaxpd %xmm0, %xmm1, %xmm2
+; AVX512-NEXT: vcmpordpd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
%z = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double> %y) readnone
ret <2 x double> %z
}
@@ -417,12 +444,19 @@ define <4 x double> @test_intrinsic_fmax_v4f64(<4 x double> %x, <4 x double> %y)
; SSE4-NEXT: movapd %xmm4, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmax_v4f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmaxpd %ymm0, %ymm1, %ymm2
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
-; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmax_v4f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmaxpd %ymm0, %ymm1, %ymm2
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
+; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmax_v4f64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmaxpd %ymm0, %ymm1, %ymm2
+; AVX512-NEXT: vcmpordpd %ymm0, %ymm0, %ymm0
+; AVX512-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
+; AVX512-NEXT: retq
%z = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %x, <4 x double> %y) readnone
ret <4 x double> %z
}
@@ -495,10 +529,9 @@ define <8 x double> @test_intrinsic_fmax_v8f64(<8 x double> %x, <8 x double> %y)
;
; AVX512-LABEL: test_intrinsic_fmax_v8f64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmaxpd %zmm0, %zmm1, %zmm2
-; AVX512-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1}
-; AVX512-NEXT: vmovapd %zmm2, %zmm0
+; AVX512-NEXT: vcmpordpd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vmaxpd %zmm0, %zmm1, %zmm1 {%k1}
+; AVX512-NEXT: vmovapd %zmm1, %zmm0
; AVX512-NEXT: retq
%z = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
ret <8 x double> %z
diff --git a/llvm/test/CodeGen/X86/fminnum.ll b/llvm/test/CodeGen/X86/fminnum.ll
index 112d0f25cbaab..c108644eae0bf 100644
--- a/llvm/test/CodeGen/X86/fminnum.ll
+++ b/llvm/test/CodeGen/X86/fminnum.ll
@@ -196,12 +196,19 @@ define <2 x float> @test_intrinsic_fmin_v2f32(<2 x float> %x, <2 x float> %y) {
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmin_v2f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vminps %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmin_v2f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminps %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmin_v2f32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vminps %xmm0, %xmm1, %xmm2
+; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
%z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
ret <2 x float> %z
}
@@ -226,12 +233,19 @@ define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmin_v4f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vminps %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmin_v4f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminps %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmin_v4f32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vminps %xmm0, %xmm1, %xmm2
+; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
%z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
ret <4 x float> %z
}
@@ -268,12 +282,19 @@ define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
; SSE4-NEXT: movaps %xmm4, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmin_v8f32:
-; AVX: # %bb.0:
-; AVX-NEXT: vminps %ymm0, %ymm1, %ymm2
-; AVX-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
-; AVX-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmin_v8f32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminps %ymm0, %ymm1, %ymm2
+; AVX1-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
+; AVX1-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmin_v8f32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vminps %ymm0, %ymm1, %ymm2
+; AVX512-NEXT: vcmpordps %ymm0, %ymm0, %ymm0
+; AVX512-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
+; AVX512-NEXT: retq
%z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
ret <8 x float> %z
}
@@ -346,10 +367,9 @@ define <16 x float> @test_intrinsic_fmin_v16f32(<16 x float> %x, <16 x float> %y
;
; AVX512-LABEL: test_intrinsic_fmin_v16f32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vminps %zmm0, %zmm1, %zmm2
-; AVX512-NEXT: vcmpunordps %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovaps %zmm1, %zmm2 {%k1}
-; AVX512-NEXT: vmovaps %zmm2, %zmm0
+; AVX512-NEXT: vcmpordps %zmm0, %zmm0, %k1
+; AVX512-NEXT: vminps %zmm0, %zmm1, %zmm1 {%k1}
+; AVX512-NEXT: vmovaps %zmm1, %zmm0
; AVX512-NEXT: retq
%z = call <16 x float> @llvm.minnum.v16f32(<16 x float> %x, <16 x float> %y) readnone
ret <16 x float> %z
@@ -375,12 +395,19 @@ define <2 x double> @test_intrinsic_fmin_v2f64(<2 x double> %x, <2 x double> %y)
; SSE4-NEXT: movapd %xmm2, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmin_v2f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm2
-; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
-; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmin_v2f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminpd %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmin_v2f64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vminpd %xmm0, %xmm1, %xmm2
+; AVX512-NEXT: vcmpordpd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT: retq
%z = call <2 x double> @llvm.minnum.v2f64(<2 x double> %x, <2 x double> %y) readnone
ret <2 x double> %z
}
@@ -417,12 +444,19 @@ define <4 x double> @test_intrinsic_fmin_v4f64(<4 x double> %x, <4 x double> %y)
; SSE4-NEXT: movapd %xmm4, %xmm0
; SSE4-NEXT: retq
;
-; AVX-LABEL: test_intrinsic_fmin_v4f64:
-; AVX: # %bb.0:
-; AVX-NEXT: vminpd %ymm0, %ymm1, %ymm2
-; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
-; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
-; AVX-NEXT: retq
+; AVX1-LABEL: test_intrinsic_fmin_v4f64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vminpd %ymm0, %ymm1, %ymm2
+; AVX1-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
+; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX512-LABEL: test_intrinsic_fmin_v4f64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vminpd %ymm0, %ymm1, %ymm2
+; AVX512-NEXT: vcmpordpd %ymm0, %ymm0, %ymm0
+; AVX512-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
+; AVX512-NEXT: retq
%z = call <4 x double> @llvm.minnum.v4f64(<4 x double> %x, <4 x double> %y) readnone
ret <4 x double> %z
}
@@ -495,10 +529,9 @@ define <8 x double> @test_intrinsic_fmin_v8f64(<8 x double> %x, <8 x double> %y)
;
; AVX512-LABEL: test_intrinsic_fmin_v8f64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vminpd %zmm0, %zmm1, %zmm2
-; AVX512-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1}
-; AVX512-NEXT: vmovapd %zmm2, %zmm0
+; AVX512-NEXT: vcmpordpd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vminpd %zmm0, %zmm1, %zmm1 {%k1}
+; AVX512-NEXT: vmovapd %zmm1, %zmm0
; AVX512-NEXT: retq
%z = call <8 x double> @llvm.minnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
ret <8 x double> %z
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmax.ll b/llvm/test/CodeGen/X86/vector-reduce-fmax.ll
index 7048b98227620..ece1005bcee77 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fmax.ll
@@ -1039,32 +1039,31 @@ define double @test_v16f64(<16 x double> %a0) {
;
; AVX512-LABEL: test_v16f64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmaxpd %zmm0, %zmm1, %zmm2
-; AVX512-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1}
-; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
-; AVX512-NEXT: vmaxsd %xmm2, %xmm0, %xmm1
-; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512-NEXT: vextractf128 $1, %ymm2, %xmm0
-; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512-NEXT: vcmpordpd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vmaxpd %zmm0, %zmm1, %zmm1 {%k1}
+; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
+; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512-NEXT: vextractf128 $1, %ymm1, %xmm0
+; AVX512-NEXT: vmaxsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512-NEXT: vextractf32x4 $2, %zmm2, %xmm0
-; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
+; AVX512-NEXT: vmaxsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512-NEXT: vextractf32x4 $2, %zmm1, %xmm0
+; AVX512-NEXT: vmaxsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512-NEXT: vextractf32x4 $3, %zmm2, %xmm0
-; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1
+; AVX512-NEXT: vmaxsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512-NEXT: vextractf32x4 $3, %zmm1, %xmm0
+; AVX512-NEXT: vmaxsd %xmm2, %xmm0, %xmm1
; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
; AVX512-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmin.ll b/llvm/test/CodeGen/X86/vector-reduce-fmin.ll
index 727af12217c67..51fdf9fb9d47e 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fmin.ll
@@ -1043,32 +1043,31 @@ define double @test_v16f64(<16 x double> %a0) {
;
; AVX512-LABEL: test_v16f64:
; AVX512: # %bb.0:
-; AVX512-NEXT: vminpd %zmm0, %zmm1, %zmm2
-; AVX512-NEXT: vcmpunordpd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1}
-; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm2[1,0]
-; AVX512-NEXT: vminsd %xmm2, %xmm0, %xmm1
-; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512-NEXT: vextractf128 $1, %ymm2, %xmm0
-; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
+; AVX512-NEXT: vcmpordpd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vminpd %zmm0, %zmm1, %zmm1 {%k1}
+; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
+; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512-NEXT: vextractf128 $1, %ymm1, %xmm0
+; AVX512-NEXT: vminsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512-NEXT: vextractf32x4 $2, %zmm2, %xmm0
-; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
+; AVX512-NEXT: vminsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512-NEXT: vextractf32x4 $2, %zmm1, %xmm0
+; AVX512-NEXT: vminsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
-; AVX512-NEXT: vextractf32x4 $3, %zmm2, %xmm0
-; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm1
+; AVX512-NEXT: vminsd %xmm2, %xmm0, %xmm2
+; AVX512-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1}
+; AVX512-NEXT: vcmpunordsd %xmm2, %xmm2, %k1
+; AVX512-NEXT: vextractf32x4 $3, %zmm1, %xmm0
+; AVX512-NEXT: vminsd %xmm2, %xmm0, %xmm1
; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1}
; AVX512-NEXT: vcmpunordsd %xmm1, %xmm1, %k1
; AVX512-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
More information about the llvm-commits
mailing list