[llvm] [GlobalISel] Add NumSignBits for G_UNMERGE_VALUES (PR #213607)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 2 23:58:59 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-llvm-globalisel
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
The code mostly comes from computeKnownBits, with some modifications to extract the relavent bits.
---
Full diff: https://github.com/llvm/llvm-project/pull/213607.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+32)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir (+65)
- (modified) llvm/test/CodeGen/AArch64/fcmp.ll (+54-54)
- (modified) llvm/test/CodeGen/AArch64/icmp.ll (+10-13)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 7ff23d8e1bd6e..7b72e050ddd81 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -2511,6 +2511,38 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
return TyBits - 1; // Every always-zero bit is a sign bit.
break;
}
+ case TargetOpcode::G_UNMERGE_VALUES: {
+ unsigned NumOps = MI.getNumOperands();
+ Register SrcReg = MI.getOperand(NumOps - 1).getReg();
+ LLT SrcTy = MRI.getType(SrcReg);
+
+ if ((SrcTy.isVector() && SrcTy.getScalarType() != DstTy.getScalarType()) ||
+ (SrcTy.isScalar() && DstTy.isVector()))
+ break;
+
+ // Figure out the result operand index
+ unsigned DstIdx = 0;
+ for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R;
+ ++DstIdx)
+ ;
+
+ APInt SubDemandedElts = DemandedElts;
+ unsigned DstLanes = DstTy.isVector() ? DstTy.getNumElements() : 1;
+ if (SrcTy.isVector()) {
+ SubDemandedElts =
+ DemandedElts.zext(SrcTy.getNumElements()).shl(DstIdx * DstLanes);
+ }
+
+ unsigned SrcOpKnown =
+ computeNumSignBits(SrcReg, SubDemandedElts, Depth + 1);
+ if (SrcTy.isVector())
+ FirstAnswer = SrcOpKnown;
+ else if (SrcOpKnown >= (MI.getNumOperands() - DstIdx - 2) * TyBits)
+ FirstAnswer = SrcOpKnown >= (MI.getNumOperands() - DstIdx - 1) * TyBits
+ ? TyBits
+ : SrcOpKnown % TyBits;
+ break;
+ }
case TargetOpcode::G_BUILD_VECTOR: {
// Collect the known bits that are shared by every demanded vector element.
FirstAnswer = TyBits;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir
index c0fbeab3402ee..dd568ef35d8b5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-unmerge.mir
@@ -43,3 +43,68 @@ body: |
%result1:_(<2 x i8>) = COPY %x0_0
%result2:_(<2 x i8>) = COPY %x0_1
...
+---
+name: Sign_Scalar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @Sign_Scalar
+ ; CHECK-NEXT: %copy_x0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %mask4:_ KnownBits:00000000000000000000000000000100 SignBits:29
+ ; CHECK-NEXT: %and4:_ KnownBits:???????????????????????????????? SignBits:5
+ ; CHECK-NEXT: %x4_0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %x4_1:_ KnownBits:???????????????? SignBits:5
+ ; CHECK-NEXT: %mask16:_ KnownBits:00000000000000000000000000001111 SignBits:28
+ ; CHECK-NEXT: %and16:_ KnownBits:???????????????????????????????? SignBits:16
+ ; CHECK-NEXT: %x16_0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %x16_1:_ KnownBits:???????????????? SignBits:16
+ ; CHECK-NEXT: %mask24:_ KnownBits:00000000000000000000000000011000 SignBits:27
+ ; CHECK-NEXT: %and24:_ KnownBits:???????????????????????????????? SignBits:25
+ ; CHECK-NEXT: %x24_0:_ KnownBits:???????????????? SignBits:9
+ ; CHECK-NEXT: %x24_1:_ KnownBits:???????????????? SignBits:16
+ %copy_x0:_(i32) = COPY $w0
+ %mask4:_(i32) = G_CONSTANT i32 4
+ %and4:_(i32) = G_ASHR %copy_x0, %mask4
+ %x4_0:_(i16), %x4_1:_(i16) = G_UNMERGE_VALUES %and4
+ %mask16:_(i32) = G_CONSTANT i32 15
+ %and16:_(i32) = G_ASHR %copy_x0, %mask16
+ %x16_0:_(i16), %x16_1:_(i16) = G_UNMERGE_VALUES %and16
+ %mask24:_(i32) = G_CONSTANT i32 24
+ %and24:_(i32) = G_ASHR %copy_x0, %mask24
+ %x24_0:_(i16), %x24_1:_(i16) = G_UNMERGE_VALUES %and24
+...
+---
+name: Sign_Scalar_Vector
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @Sign_Scalar_Vector
+ ; CHECK-NEXT: %copy_x0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %maskf:_ KnownBits:0000000000000100 SignBits:13
+ ; CHECK-NEXT: %x0_x1:_ KnownBits:0000000000000100 SignBits:13
+ ; CHECK-NEXT: %and:_ KnownBits:???????????????? SignBits:5
+ ; CHECK-NEXT: %x0_0:_ KnownBits:???????????????? SignBits:5
+ ; CHECK-NEXT: %x0_1:_ KnownBits:???????????????? SignBits:5
+ %copy_x0:_(<2 x i16>) = COPY $w0
+ %maskf:_(i16) = G_CONSTANT i16 4
+ %x0_x1:_(<2 x i16>) = G_BUILD_VECTOR %maskf, %maskf
+ %and:_(<2 x i16>) = G_ASHR %copy_x0, %x0_x1
+ %x0_0:_(i16), %x0_1:_(i16) = G_UNMERGE_VALUES %and
+...
+---
+name: Sign_Vector
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @Sign_Vector
+ ; CHECK-NEXT: %copy_x0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %maskff:_ KnownBits:00000110 SignBits:5
+ ; CHECK-NEXT: %maskf:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %x0_x1:_ KnownBits:000001?0 SignBits:5
+ ; CHECK-NEXT: %and:_ KnownBits:???????? SignBits:5
+ ; CHECK-NEXT: %x0_0:_ KnownBits:???????? SignBits:5
+ ; CHECK-NEXT: %x0_1:_ KnownBits:???????? SignBits:7
+ %copy_x0:_(<4 x i8>) = COPY $w0
+ %maskff:_(i8) = G_CONSTANT i8 6
+ %maskf:_(i8) = G_CONSTANT i8 4
+ %x0_x1:_(<4 x i8>) = G_BUILD_VECTOR %maskf, %maskf, %maskff, %maskff
+ %and:_(<4 x i8>) = G_ASHR %copy_x0, %x0_x1
+ %x0_0:_(<2 x i8>), %x0_1:_(<2 x i8>) = G_UNMERGE_VALUES %and
+...
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index cd948f231453e..4b3ff158516ed 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -985,8 +985,6 @@ define <3 x float> @v3f32_float(<3 x float> %a, <3 x float> %b, <3 x float> %d,
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
-; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
@@ -1055,8 +1053,6 @@ define <3 x i32> @v3f32_i32(<3 x float> %a, <3 x float> %b, <3 x i32> %d, <3 x i
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
-; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
@@ -1123,34 +1119,40 @@ define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x
;
; CHECK-GI-NOFP16-LABEL: v7f16_half:
; CHECK-GI-NOFP16: // %bb.0: // %entry
-; CHECK-GI-NOFP16-NEXT: mov v4.h[0], v0.h[4]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[0], v1.h[4]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v0.h[5]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[1], v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v0.h[6]
-; CHECK-GI-NOFP16-NEXT: mov v5.h[2], v1.h[6]
-; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h
-; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v5.4h
-; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v5.4s, v4.4s
-; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NOFP16-NEXT: movi v1.2d, #0xffffffffffffffff
-; CHECK-GI-NOFP16-NEXT: shl v0.8h, v0.8h, #15
-; CHECK-GI-NOFP16-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-GI-NOFP16-NEXT: eor v1.16b, v0.16b, v1.16b
-; CHECK-GI-NOFP16-NEXT: and v0.16b, v2.16b, v0.16b
-; CHECK-GI-NOFP16-NEXT: and v1.16b, v3.16b, v1.16b
-; CHECK-GI-NOFP16-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v0.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v1.4h
+; CHECK-GI-NOFP16-NEXT: mov v6.h[0], v0.h[4]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[0], v1.h[4]
+; CHECK-GI-NOFP16-NEXT: fcmgt v4.4s, v5.4s, v4.4s
+; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v0.h[5]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[1], v1.h[5]
+; CHECK-GI-NOFP16-NEXT: mov w8, v4.s[1]
+; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v0.h[6]
+; CHECK-GI-NOFP16-NEXT: mov w9, v4.s[2]
+; CHECK-GI-NOFP16-NEXT: mov v7.h[2], v1.h[6]
+; CHECK-GI-NOFP16-NEXT: mov w10, v4.s[3]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[1], w8
+; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v6.4h
+; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v7.4h
+; CHECK-GI-NOFP16-NEXT: mov v4.h[2], w9
+; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v1.4s, v0.4s
+; CHECK-GI-NOFP16-NEXT: movi v0.2d, #0xffffffffffffffff
+; CHECK-GI-NOFP16-NEXT: mov v4.h[3], w10
+; CHECK-GI-NOFP16-NEXT: mov w8, v1.s[1]
+; CHECK-GI-NOFP16-NEXT: mov w9, v1.s[2]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[4], v1.h[0]
+; CHECK-GI-NOFP16-NEXT: mov v4.h[5], w8
+; CHECK-GI-NOFP16-NEXT: mov v4.h[6], w9
+; CHECK-GI-NOFP16-NEXT: eor v0.16b, v4.16b, v0.16b
+; CHECK-GI-NOFP16-NEXT: and v2.16b, v2.16b, v4.16b
+; CHECK-GI-NOFP16-NEXT: and v0.16b, v3.16b, v0.16b
+; CHECK-GI-NOFP16-NEXT: orr v0.16b, v2.16b, v0.16b
; CHECK-GI-NOFP16-NEXT: ret
;
; CHECK-GI-FP16-LABEL: v7f16_half:
; CHECK-GI-FP16: // %bb.0: // %entry
; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
; CHECK-GI-FP16-NEXT: movi v1.2d, #0xffffffffffffffff
-; CHECK-GI-FP16-NEXT: shl v0.8h, v0.8h, #15
-; CHECK-GI-FP16-NEXT: cmlt v0.8h, v0.8h, #0
; CHECK-GI-FP16-NEXT: eor v1.16b, v0.16b, v1.16b
; CHECK-GI-FP16-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-FP16-NEXT: and v1.16b, v3.16b, v1.16b
@@ -1386,52 +1388,50 @@ define <7 x i32> @v7f16_i32(<7 x half> %a, <7 x half> %b, <7 x i32> %d, <7 x i32
; CHECK-GI-NOFP16-NEXT: mov v2.h[0], v0.h[4]
; CHECK-GI-NOFP16-NEXT: mov v3.h[0], v1.h[4]
; CHECK-GI-NOFP16-NEXT: ldr s4, [sp]
-; CHECK-GI-NOFP16-NEXT: fmov s5, w7
-; CHECK-GI-NOFP16-NEXT: fmov s16, w4
-; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #24]
-; CHECK-GI-NOFP16-NEXT: ldr s7, [sp, #32]
-; CHECK-GI-NOFP16-NEXT: ldr s17, [sp, #16]
+; CHECK-GI-NOFP16-NEXT: fmov s5, w0
+; CHECK-GI-NOFP16-NEXT: fmov s6, w7
+; CHECK-GI-NOFP16-NEXT: ldr s7, [sp, #24]
+; CHECK-GI-NOFP16-NEXT: fmov s17, w4
+; CHECK-GI-NOFP16-NEXT: ldr s16, [sp, #32]
; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v0.h[5]
; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v1.h[5]
-; CHECK-GI-NOFP16-NEXT: mov v5.s[1], v4.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.s[1], w1
+; CHECK-GI-NOFP16-NEXT: mov v6.s[1], v4.s[0]
; CHECK-GI-NOFP16-NEXT: ldr s4, [sp, #8]
-; CHECK-GI-NOFP16-NEXT: mov v16.s[1], w5
-; CHECK-GI-NOFP16-NEXT: mov v6.s[1], v7.s[0]
-; CHECK-GI-NOFP16-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NOFP16-NEXT: mov v17.s[1], w5
+; CHECK-GI-NOFP16-NEXT: mov v7.s[1], v16.s[0]
+; CHECK-GI-NOFP16-NEXT: ldr s16, [sp, #16]
; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[6]
; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v1.h[6]
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h
-; CHECK-GI-NOFP16-NEXT: mov v5.s[2], v4.s[0]
-; CHECK-GI-NOFP16-NEXT: ldr s4, [sp, #40]
-; CHECK-GI-NOFP16-NEXT: mov v16.s[2], w6
+; CHECK-GI-NOFP16-NEXT: mov v5.s[2], w2
; CHECK-GI-NOFP16-NEXT: mov v6.s[2], v4.s[0]
+; CHECK-GI-NOFP16-NEXT: ldr s4, [sp, #40]
+; CHECK-GI-NOFP16-NEXT: mov v17.s[2], w6
; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h
; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v3.4h
+; CHECK-GI-NOFP16-NEXT: mov v7.s[2], v4.s[0]
; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov v5.s[3], v17.s[0]
+; CHECK-GI-NOFP16-NEXT: mov v5.s[3], w3
+; CHECK-GI-NOFP16-NEXT: mov v6.s[3], v16.s[0]
; CHECK-GI-NOFP16-NEXT: fcmgt v2.4s, v3.4s, v2.4s
-; CHECK-GI-NOFP16-NEXT: fmov s3, w0
-; CHECK-GI-NOFP16-NEXT: mov v3.s[1], w1
-; CHECK-GI-NOFP16-NEXT: shl v2.4s, v2.4s, #31
-; CHECK-GI-NOFP16-NEXT: mov v3.s[2], w2
-; CHECK-GI-NOFP16-NEXT: cmlt v2.4s, v2.4s, #0
-; CHECK-GI-NOFP16-NEXT: eor v1.16b, v2.16b, v7.16b
-; CHECK-GI-NOFP16-NEXT: and v2.16b, v16.16b, v2.16b
-; CHECK-GI-NOFP16-NEXT: mov v3.s[3], w3
-; CHECK-GI-NOFP16-NEXT: and v1.16b, v6.16b, v1.16b
-; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v3.16b, v5.16b
-; CHECK-GI-NOFP16-NEXT: orr v1.16b, v2.16b, v1.16b
-; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]
+; CHECK-GI-NOFP16-NEXT: movi v3.2d, #0xffffffffffffffff
+; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v5.16b, v6.16b
+; CHECK-GI-NOFP16-NEXT: eor v1.16b, v2.16b, v3.16b
+; CHECK-GI-NOFP16-NEXT: and v2.16b, v17.16b, v2.16b
; CHECK-GI-NOFP16-NEXT: mov s3, v0.s[2]
; CHECK-GI-NOFP16-NEXT: mov s4, v0.s[3]
+; CHECK-GI-NOFP16-NEXT: fmov w0, s0
+; CHECK-GI-NOFP16-NEXT: and v1.16b, v7.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: fmov w2, s3
+; CHECK-GI-NOFP16-NEXT: fmov w3, s4
+; CHECK-GI-NOFP16-NEXT: orr v1.16b, v2.16b, v1.16b
+; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]
; CHECK-GI-NOFP16-NEXT: mov s5, v1.s[1]
; CHECK-GI-NOFP16-NEXT: mov s6, v1.s[2]
-; CHECK-GI-NOFP16-NEXT: fmov w0, s0
; CHECK-GI-NOFP16-NEXT: fmov w4, s1
; CHECK-GI-NOFP16-NEXT: fmov w1, s2
-; CHECK-GI-NOFP16-NEXT: fmov w2, s3
-; CHECK-GI-NOFP16-NEXT: fmov w3, s4
; CHECK-GI-NOFP16-NEXT: fmov w5, s5
; CHECK-GI-NOFP16-NEXT: fmov w6, s6
; CHECK-GI-NOFP16-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 6830ce834ab11..914b81330ad08 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -1160,24 +1160,23 @@ define <3 x i64> @v3i64_i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %d, <3 x i64>
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3
; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4
-; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6
-; CHECK-GI-NEXT: // kill: def $d5 killed $d5 def $q5
+; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7
+; CHECK-GI-NEXT: // kill: def $d5 killed $d5 def $q5
; CHECK-GI-NEXT: ldr x8, [sp]
-; CHECK-GI-NEXT: ldr x10, [sp, #24]
+; CHECK-GI-NEXT: ldr x9, [sp, #24]
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]
-; CHECK-GI-NEXT: cmgt v2.2d, v5.2d, v2.2d
-; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]
; CHECK-GI-NEXT: mov v6.d[1], v7.d[0]
-; CHECK-GI-NEXT: fmov x9, d2
+; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]
+; CHECK-GI-NEXT: cmgt v2.2d, v5.2d, v2.2d
; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]
; CHECK-GI-NEXT: cmgt v0.2d, v3.2d, v0.2d
-; CHECK-GI-NEXT: sbfx x9, x9, #0, #1
+; CHECK-GI-NEXT: fmov x10, d2
+; CHECK-GI-NEXT: and x8, x8, x10
+; CHECK-GI-NEXT: bic x9, x9, x10
; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b
-; CHECK-GI-NEXT: and x8, x8, x9
-; CHECK-GI-NEXT: bic x9, x10, x9
; CHECK-GI-NEXT: orr x8, x8, x9
; CHECK-GI-NEXT: fmov d2, x8
; CHECK-GI-NEXT: mov d1, v0.d[1]
@@ -1232,11 +1231,9 @@ define <3 x i32> @v3i32_i32(<3 x i32> %a, <3 x i32> %b, <3 x i32> %d, <3 x i32>
;
; CHECK-GI-LABEL: v3i32_i32:
; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff
-; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
-; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: eor v1.16b, v0.16b, v4.16b
; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
``````````
</details>
https://github.com/llvm/llvm-project/pull/213607
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