[llvm] [AMDGPU][CodeGen] Incrementally update reserved regs for SIPreAllocateWWMRegs pass in RegisterClassInfo (PR #212201)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,54 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a \
+# RUN:   -passes="require<machine-register-class-info>,si-pre-allocate-wwm-regs,require<machine-register-class-info>" \
+# RUN:   -debug-pass-manager -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a \
+# RUN:   -passes=si-pre-allocate-wwm-regs -o - %s | FileCheck %s --check-prefix=MIR
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a \
+# RUN:   -passes="si-pre-allocate-wwm-regs,greedy<vgpr>,virt-reg-rewriter" \
+# RUN:   -o - %s | FileCheck %s --check-prefix=ALIAS
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a \
+# RUN:   -passes="greedy<vgpr>,virt-reg-rewriter" \
+# RUN:   -o - %s | FileCheck %s --check-prefix=NO-WWM
----------------
arsenm wrote:

```suggestion
# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa \
# RUN:   -passes="require<machine-register-class-info>,si-pre-allocate-wwm-regs,require<machine-register-class-info>" \
# RUN:   -debug-pass-manager -o /dev/null %s 2>&1 | FileCheck %s
# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa \
# RUN:   -passes=si-pre-allocate-wwm-regs -o - %s | FileCheck %s --check-prefix=MIR
# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa \
# RUN:   -passes="si-pre-allocate-wwm-regs,greedy<vgpr>,virt-reg-rewriter" \
# RUN:   -o - %s | FileCheck %s --check-prefix=ALIAS
# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa \
# RUN:   -passes="greedy<vgpr>,virt-reg-rewriter" \
# RUN:   -o - %s | FileCheck %s --check-prefix=NO-WWM
```

https://github.com/llvm/llvm-project/pull/212201