[llvm] [llvm][RISCV] Correct the ci value in batched dot product mnemonic (PR #213579)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 2 19:29:51 PDT 2026
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/213579
It's encoded by 3 bits but assembly should be scaled by 8.
>From 7473c50bbc6f1fc73b6a860aa9c146d6895cd8ed Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 3 Aug 2026 10:22:10 +0800
Subject: [PATCH] [llvm][RISCV] Correct the ci value in batched dot product
mnemonic
It's encoded by 3 bits but assembly should be scaled by 8.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 +++++
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 21 +++++++++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 21 -------------------
.../lib/Target/RISCV/RISCVInstrInfoZvbdota.td | 14 ++++++++++---
llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s | 11 ++++++----
llvm/test/MC/RISCV/rvv/zvfbdota32f.s | 8 +++----
llvm/test/MC/RISCV/rvv/zvfqwbdota8f-invalid.s | 11 ++++++----
llvm/test/MC/RISCV/rvv/zvfqwbdota8f.s | 16 +++++++-------
.../test/MC/RISCV/rvv/zvfwbdota16bf-invalid.s | 11 ++++++----
llvm/test/MC/RISCV/rvv/zvfwbdota16bf.s | 8 +++----
llvm/test/MC/RISCV/rvv/zvqwbdota-invalid.s | 11 ++++++----
llvm/test/MC/RISCV/rvv/zvqwbdota.s | 16 +++++++-------
14 files changed, 91 insertions(+), 64 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 8563f678464a6..b5886d284e486 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -916,6 +916,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isUImm6Lsb0() const { return isUImmShifted<5, 1>(); }
+ bool isUImm6Lsb000() const { return isUImmShifted<3, 3>(); }
+
bool isUImm7Lsb00() const { return isUImmShifted<5, 2>(); }
bool isUImm7Lsb000() const { return isUImmShifted<4, 3>(); }
@@ -1603,6 +1605,9 @@ std::string RISCVAsmParser::getCustomOperandDiag(unsigned MatchError) {
case Match_InvalidUImm6Lsb0:
return Range(0, (1 << 6) - 2,
"immediate must be a multiple of 2 bytes in the range");
+ case Match_InvalidUImm6Lsb000:
+ return Range(0, (1 << 6) - 8,
+ "immediate must be a multiple of 8 in the range");
case Match_InvalidUImm7Lsb00:
return Range(0, (1 << 7) - 4,
"immediate must be a multiple of 4 bytes in the range");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index e54d57d9f4451..c3620988049ef 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -47,6 +47,7 @@ enum OperandType : unsigned {
OPERAND_UIMM6,
OPERAND_UIMM6_PLUS1,
OPERAND_UIMM6_LSB0,
+ OPERAND_UIMM6_LSB000,
OPERAND_UIMM7,
OPERAND_UIMM7_LSB00,
OPERAND_UIMM7_LSB000,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index cdc1a8c07c09f..df93401d98067 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3034,6 +3034,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_UIMM_LSB_ZEROS(2, 0)
CASE_OPERAND_UIMM_LSB_ZEROS(5, 0)
CASE_OPERAND_UIMM_LSB_ZEROS(6, 0)
+ CASE_OPERAND_UIMM_LSB_ZEROS(6, 000)
CASE_OPERAND_UIMM_LSB_ZEROS(7, 00)
CASE_OPERAND_UIMM_LSB_ZEROS(7, 000)
CASE_OPERAND_UIMM_LSB_ZEROS(8, 00)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 09fa9fc0ead1b..f2fce95b35052 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -273,6 +273,27 @@ class RISCVUImmOp<int bitsNum> : RISCVOp {
class RISCVUImmLeafOp<int bitsNum> :
RISCVUImmOp<bitsNum>, ImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);">;
+// A N-bit unsigned immediate where the least significant bits are zero.
+class RISCVUImmLsbZeroOp<int width, int zeros>
+ : RISCVOp, ImmLeaf<XLenVT, [{return isShiftedUInt<}] # !sub(width, zeros) #
+ [{, }] # zeros # [{>(Imm);}]> {
+
+ // Create suffix with the appropriate number of 0s to append to all names
+ defvar Suffix = !foldl("", !range(zeros), acc, ignore, !strconcat(acc, "0"));
+
+ let ParserMatchClass = UImmAsmOperand<width, "Lsb" # Suffix>;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeUImmOperand<" # width # ">";
+ let OperandType = "OPERAND_UIMM" # width # "_LSB" # Suffix;
+
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<}] # !sub(width, zeros) # [{, }] # zeros # [{>(Imm);
+ }];
+}
+
class RISCVSImmOp<int bitsNum> : RISCVOp {
let ParserMatchClass = SImmAsmOperand<bitsNum>;
let EncoderMethod = "getImmOpValue";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index f7167a002fd9d..d64561ecd908f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -86,27 +86,6 @@ def c_lui_imm : RISCVOp,
}];
}
-// A N-bit unsigned immediate where the least significant bits are zero.
-class RISCVUImmLsbZeroOp<int width, int zeros>
- : RISCVOp, ImmLeaf<XLenVT, [{return isShiftedUInt<}] # !sub(width, zeros) #
- [{, }] # zeros # [{>(Imm);}]> {
-
- // Create suffix with the appropriate number of 0s to append to all names
- defvar Suffix = !foldl("", !range(zeros), acc, ignore, !strconcat(acc, "0"));
-
- let ParserMatchClass = UImmAsmOperand<width, "Lsb" # Suffix>;
- let EncoderMethod = "getImmOpValue";
- let DecoderMethod = "decodeUImmOperand<" # width # ">";
- let OperandType = "OPERAND_UIMM" # width # "_LSB" # Suffix;
-
- let MCOperandPredicate = [{
- int64_t Imm;
- if (!MCOp.evaluateAsConstantImm(Imm))
- return false;
- return isShiftedUInt<}] # !sub(width, zeros) # [{, }] # zeros # [{>(Imm);
- }];
-}
-
// A 7-bit unsigned immediate where the least significant two bits are zero.
def uimm7_lsb00 : RISCVUImmLsbZeroOp<7, 2>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td
index 673e0ba85161d..6a3642be0ac94 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvbdota.td
@@ -13,6 +13,14 @@
//
//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// Operand definitions
+//===----------------------------------------------------------------------===//
+
+// The ci operand is written as a multiple of 8 in the assembly syntax, but the
+// encoded field only holds the value divided by 8.
+def uimm6_lsb000 : RISCVUImmLsbZeroOp<6, 3>;
+
//===----------------------------------------------------------------------===//
// Instruction class definitions
//===----------------------------------------------------------------------===//
@@ -22,11 +30,11 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
VS1VS2Constraint = Vrgather, Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb" in
class ZvbdotaVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
- (ins VR:$vd, VRM8:$vs2, VR:$vs1, uimm3:$ci, VMaskOp:$vm),
+ (ins VR:$vd, VRM8:$vs2, VR:$vs1, uimm6_lsb000:$ci, VMaskOp:$vm),
opcodestr, "$vd, $vs2, $vs1, $ci$vm"> {
- bits<3> ci;
+ bits<6> ci;
let Inst{24-23} = vs2{4-3};
- let Inst{22-20} = ci;
+ let Inst{22-20} = ci{5-3};
let Inst{6-0} = OPC_OP_VE.Value;
}
diff --git a/llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s b/llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s
index b317d4e39e342..84c94c782ad54 100644
--- a/llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s
@@ -6,13 +6,16 @@
vsetvli a0, zero, e888, m1, ta, ma
# Invalid ci
-# CHECK-ERROR: immediate must be an integer in the range [0, 7]{{$}}
-vfbdota.vv v8, v16, v12, 8
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vfbdota.vv v8, v16, v12, 4
+
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vfbdota.vv v8, v16, v12, 64
# Invalid vs2
# CHECK-ERROR: invalid operand for instruction{{$}}
-vfbdota.vv v8, v17, v12, 1
+vfbdota.vv v8, v17, v12, 8
# Invalid vs2 and ci
# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid operand for instruction{{$}}
-vfbdota.vv v8, v17, v12, 8
+vfbdota.vv v8, v17, v12, 4
diff --git a/llvm/test/MC/RISCV/rvv/zvfbdota32f.s b/llvm/test/MC/RISCV/rvv/zvfbdota32f.s
index afa8e441c1d27..5dde3d96d3a2d 100644
--- a/llvm/test/MC/RISCV/rvv/zvfbdota32f.s
+++ b/llvm/test/MC/RISCV/rvv/zvfbdota32f.s
@@ -6,12 +6,12 @@
# RUN: | llvm-objdump -d --mattr=+experimental-zvfbdota32f --no-print-imm-hex - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# CHECK-INST: vfbdota.vv v8, v16, v12, 1
+# CHECK-INST: vfbdota.vv v8, v16, v12, 8
# CHECK-ENCODING: [0x77,0x14,0x16,0xaf]
# CHECK-ERROR: instruction requires the following: 'Zvfbdota32f' (FP32 batched dot-product extension){{$}}
-vfbdota.vv v8, v16, v12, 1
+vfbdota.vv v8, v16, v12, 8
-# CHECK-INST: vfbdota.vv v8, v16, v12, 2, v0.t
+# CHECK-INST: vfbdota.vv v8, v16, v12, 16, v0.t
# CHECK-ENCODING: [0x77,0x14,0x26,0xad]
# CHECK-ERROR: instruction requires the following: 'Zvfbdota32f' (FP32 batched dot-product extension){{$}}
-vfbdota.vv v8, v16, v12, 2, v0.t
+vfbdota.vv v8, v16, v12, 16, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwbdota8f-invalid.s b/llvm/test/MC/RISCV/rvv/zvfqwbdota8f-invalid.s
index d1288674dfd1d..91006575948ff 100644
--- a/llvm/test/MC/RISCV/rvv/zvfqwbdota8f-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvfqwbdota8f-invalid.s
@@ -6,13 +6,16 @@
vsetvli a0, zero, e888, m1, ta, ma
# Invalid ci
-# CHECK-ERROR: immediate must be an integer in the range [0, 7]{{$}}
-vfqwbdota.vv v8, v16, v12, 8
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vfqwbdota.vv v8, v16, v12, 4
+
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vfqwbdota.vv v8, v16, v12, 64
# Invalid vs2
# CHECK-ERROR: invalid operand for instruction{{$}}
-vfqwbdota.vv v8, v17, v12, 1
+vfqwbdota.vv v8, v17, v12, 8
# Invalid vs2 and ci
# CHECK-ERROR: :[[@LINE+1]]:18: error: invalid operand for instruction{{$}}
-vfqwbdota.vv v8, v17, v12, 8
+vfqwbdota.vv v8, v17, v12, 4
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwbdota8f.s b/llvm/test/MC/RISCV/rvv/zvfqwbdota8f.s
index 896a5f617b406..b379f82e6d087 100644
--- a/llvm/test/MC/RISCV/rvv/zvfqwbdota8f.s
+++ b/llvm/test/MC/RISCV/rvv/zvfqwbdota8f.s
@@ -10,22 +10,22 @@
# CHECK-ENCODING: [0x57,0x70,0x00,0x1c]
vsetvli zero, zero, e8alt, m1, ta, ma
-# CHECK-INST: vfqwbdota.vv v8, v16, v12, 1
+# CHECK-INST: vfqwbdota.vv v8, v16, v12, 8
# CHECK-ENCODING: [0x77,0x14,0x16,0xbb]
# CHECK-ERROR: instruction requires the following: 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension){{$}}
-vfqwbdota.vv v8, v16, v12, 1
+vfqwbdota.vv v8, v16, v12, 8
-# CHECK-INST: vfqwbdota.vv v8, v16, v12, 2, v0.t
+# CHECK-INST: vfqwbdota.vv v8, v16, v12, 16, v0.t
# CHECK-ENCODING: [0x77,0x14,0x26,0xb9]
# CHECK-ERROR: instruction requires the following: 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension){{$}}
-vfqwbdota.vv v8, v16, v12, 2, v0.t
+vfqwbdota.vv v8, v16, v12, 16, v0.t
-# CHECK-INST: vfqwbdota.alt.vv v8, v16, v12, 1
+# CHECK-INST: vfqwbdota.alt.vv v8, v16, v12, 8
# CHECK-ENCODING: [0x77,0x14,0x16,0xbf]
# CHECK-ERROR: instruction requires the following: 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension){{$}}
-vfqwbdota.alt.vv v8, v16, v12, 1
+vfqwbdota.alt.vv v8, v16, v12, 8
-# CHECK-INST: vfqwbdota.alt.vv v8, v16, v12, 2, v0.t
+# CHECK-INST: vfqwbdota.alt.vv v8, v16, v12, 16, v0.t
# CHECK-ENCODING: [0x77,0x14,0x26,0xbd]
# CHECK-ERROR: instruction requires the following: 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension){{$}}
-vfqwbdota.alt.vv v8, v16, v12, 2, v0.t
+vfqwbdota.alt.vv v8, v16, v12, 16, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvfwbdota16bf-invalid.s b/llvm/test/MC/RISCV/rvv/zvfwbdota16bf-invalid.s
index 2132e4eaa28f0..979e588f83dc6 100644
--- a/llvm/test/MC/RISCV/rvv/zvfwbdota16bf-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvfwbdota16bf-invalid.s
@@ -6,13 +6,16 @@
vsetvli a0, zero, e888, m1, ta, ma
# Invalid ci
-# CHECK-ERROR: immediate must be an integer in the range [0, 7]{{$}}
-vfwbdota.vv v8, v16, v12, 8
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vfwbdota.vv v8, v16, v12, 4
+
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vfwbdota.vv v8, v16, v12, 64
# Invalid vs2
# CHECK-ERROR: invalid operand for instruction{{$}}
-vfwbdota.vv v8, v17, v12, 1
+vfwbdota.vv v8, v17, v12, 8
# Invalid vs2 and ci
# CHECK-ERROR: :[[@LINE+1]]:17: error: invalid operand for instruction{{$}}
-vfwbdota.vv v8, v17, v12, 8
+vfwbdota.vv v8, v17, v12, 4
diff --git a/llvm/test/MC/RISCV/rvv/zvfwbdota16bf.s b/llvm/test/MC/RISCV/rvv/zvfwbdota16bf.s
index 1a4f5481c6fdf..66f8ac311a086 100644
--- a/llvm/test/MC/RISCV/rvv/zvfwbdota16bf.s
+++ b/llvm/test/MC/RISCV/rvv/zvfwbdota16bf.s
@@ -10,12 +10,12 @@
# CHECK-ENCODING: [0x57,0x70,0x80,0x1c]
vsetvli zero, zero, e16alt, m1, ta, ma
-# CHECK-INST: vfwbdota.vv v8, v16, v12, 1
+# CHECK-INST: vfwbdota.vv v8, v16, v12, 8
# CHECK-ENCODING: [0x77,0x14,0x16,0xb3]
# CHECK-ERROR: instruction requires the following: 'Zvfwbdota16bf' (BF16 batched dot-product extension){{$}}
-vfwbdota.vv v8, v16, v12, 1
+vfwbdota.vv v8, v16, v12, 8
-# CHECK-INST: vfwbdota.vv v8, v16, v12, 2, v0.t
+# CHECK-INST: vfwbdota.vv v8, v16, v12, 16, v0.t
# CHECK-ENCODING: [0x77,0x14,0x26,0xb1]
# CHECK-ERROR: instruction requires the following: 'Zvfwbdota16bf' (BF16 batched dot-product extension){{$}}
-vfwbdota.vv v8, v16, v12, 2, v0.t
+vfwbdota.vv v8, v16, v12, 16, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvqwbdota-invalid.s b/llvm/test/MC/RISCV/rvv/zvqwbdota-invalid.s
index f7fddad9680e7..7a983e96edd8f 100644
--- a/llvm/test/MC/RISCV/rvv/zvqwbdota-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvqwbdota-invalid.s
@@ -6,13 +6,16 @@
vsetvli a0, zero, e888, m1, ta, ma
# Invalid ci
-# CHECK-ERROR: immediate must be an integer in the range [0, 7]{{$}}
-vqwbdotau.vv v8, v16, v12, 8
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vqwbdotau.vv v8, v16, v12, 4
+
+# CHECK-ERROR: immediate must be a multiple of 8 in the range [0, 56]{{$}}
+vqwbdotau.vv v8, v16, v12, 64
# Invalid vs2
# CHECK-ERROR: invalid operand for instruction{{$}}
-vqwbdotau.vv v8, v17, v12, 1
+vqwbdotau.vv v8, v17, v12, 8
# Invalid vs2 and ci
# CHECK-ERROR: :[[@LINE+1]]:18: error: invalid operand for instruction{{$}}
-vqwbdotau.vv v8, v17, v12, 8
+vqwbdotau.vv v8, v17, v12, 4
diff --git a/llvm/test/MC/RISCV/rvv/zvqwbdota.s b/llvm/test/MC/RISCV/rvv/zvqwbdota.s
index 373eb280af75a..7a1449a35f556 100644
--- a/llvm/test/MC/RISCV/rvv/zvqwbdota.s
+++ b/llvm/test/MC/RISCV/rvv/zvqwbdota.s
@@ -17,22 +17,22 @@ vsetvli zero, zero, e8alt, m1, ta, ma
# CHECK-ENCODING: [0x57,0x70,0x80,0x1c]
vsetvli zero, zero, e16alt, m1, ta, ma
-# CHECK-INST: vqwbdotau.vv v8, v16, v12, 1
+# CHECK-INST: vqwbdotau.vv v8, v16, v12, 8
# CHECK-ENCODING: [0x77,0x04,0x16,0xbb]
# CHECK-ERROR: instruction requires the following: 'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension){{$}}
-vqwbdotau.vv v8, v16, v12, 1
+vqwbdotau.vv v8, v16, v12, 8
-# CHECK-INST: vqwbdotau.vv v8, v16, v12, 2, v0.t
+# CHECK-INST: vqwbdotau.vv v8, v16, v12, 16, v0.t
# CHECK-ENCODING: [0x77,0x04,0x26,0xb9]
# CHECK-ERROR: instruction requires the following: 'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension){{$}}
-vqwbdotau.vv v8, v16, v12, 2, v0.t
+vqwbdotau.vv v8, v16, v12, 16, v0.t
-# CHECK-INST: vqwbdotas.vv v8, v16, v12, 1
+# CHECK-INST: vqwbdotas.vv v8, v16, v12, 8
# CHECK-ENCODING: [0x77,0x04,0x16,0xbf]
# CHECK-ERROR: instruction requires the following: 'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension){{$}}
-vqwbdotas.vv v8, v16, v12, 1
+vqwbdotas.vv v8, v16, v12, 8
-# CHECK-INST: vqwbdotas.vv v8, v16, v12, 2, v0.t
+# CHECK-INST: vqwbdotas.vv v8, v16, v12, 16, v0.t
# CHECK-ENCODING: [0x77,0x04,0x26,0xbd]
# CHECK-ERROR: instruction requires the following: 'Zvqwbdota8i' or 'Zvqwbdota16i' (8-bit or 16-bit integer batched dot-product extension){{$}}
-vqwbdotas.vv v8, v16, v12, 2, v0.t
+vqwbdotas.vv v8, v16, v12, 16, v0.t
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