[llvm] [AArch64] Fold vector select with power-of-2 bit-test to CMTST+BSP (PR #209100)

[David Green via llvm-commits]

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@@ -29067,6 +29089,43 @@ static SDValue performSETCCCombine(SDNode *N,
       SplatLHSVal.isOne())
     return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, CmpVT), RHS, ISD::SETGE);
 
+  // Fold setcc(and(X, Mask), Mask/0, eq/ne) --> [not] AArch64ISD::CMTST(X,
+  // Mask) for a power of 2 splat Mask, replacing AND+CMEQ with a single CMTST.
+  // Any NOT folds away when the result feeds a BSL/BIF/BIT select.
+  if (!DCI.isBeforeLegalize() && CmpVT.isFixedLengthVector() &&
+      (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+      LHS.getOpcode() == ISD::AND) {
+    APInt SplatVal;
+    SDValue X, MaskOp;
+    if (ISD::isConstantSplatVector(LHS.getOperand(1).getNode(), SplatVal) &&
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davemgreen wrote:

I think this needn't check for specific constants. I believe it just needs RHS to be a ZeroVector, Cond to be SETEQ (SETNE will be legalized to SETEQ), and LHS is an AND. The we can generate a NOT(CMTST(X, Y)) from the And operands. That should hopefully simplify what remains.

https://github.com/llvm/llvm-project/pull/209100