[llvm] [X86] Eliminate dead SSE loads and stores after rewriting stack spills (PR #213498)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 2 10:58:48 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/213498
>From 6bafe122061cd20ad592e3c93e560089ef32930f Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 1 Aug 2026 20:08:12 -0400
Subject: [PATCH 1/9] [X86] Add pre-commit test case for x87 float return and
SSE roundtrip
---
llvm/test/CodeGen/X86/x87-inout-bounce.ll | 94 +++++++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/x87-inout-bounce.ll
diff --git a/llvm/test/CodeGen/X86/x87-inout-bounce.ll b/llvm/test/CodeGen/X86/x87-inout-bounce.ll
new file mode 100644
index 0000000000000..161ca2c1742b1
--- /dev/null
+++ b/llvm/test/CodeGen/X86/x87-inout-bounce.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=+sse2,+x87 | FileCheck %s
+
+define float @returns_float() {
+; CHECK-LABEL: returns_float:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subl $12, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: calll rand at PLT
+; CHECK-NEXT: cvtsi2ss %eax, %xmm0
+; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: addl $12, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: retl
+entry:
+ %call = call i32 @rand()
+ %conv = sitofp i32 %call to float
+ ret float %conv
+}
+
+declare i32 @rand()
+
+define float @example_float() {
+; CHECK-LABEL: example_float:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subl $28, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: calll returns_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movss %xmm0, (%esp) # 4-byte Spill
+; CHECK-NEXT: calll returns_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss (%esp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: addss {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: movss %xmm0, (%esp) # 4-byte Spill
+; CHECK-NEXT: calll returns_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss (%esp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: addss {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: movss %xmm0, (%esp) # 4-byte Spill
+; CHECK-NEXT: calll returns_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss (%esp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: addss {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: movss %xmm0, (%esp) # 4-byte Spill
+; CHECK-NEXT: calll returns_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss (%esp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: addss {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: addl $28, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: retl
+entry:
+ %call = call float @returns_float()
+ %call1 = call float @returns_float()
+ %add = fadd float %call, %call1
+ %call2 = call float @returns_float()
+ %add3 = fadd float %add, %call2
+ %call4 = call float @returns_float()
+ %add5 = fadd float %add3, %call4
+ %call6 = call float @returns_float()
+ %add7 = fadd float %add5, %call6
+ ret float %add7
+}
+
+declare x86_fp80 @returns_long_double()
+
+define x86_fp80 @testC() {
+; CHECK-LABEL: testC:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subl $12, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: calll returns_long_double at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: addl $12, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: retl
+entry:
+ %call = call x86_fp80 @returns_long_double()
+ %conv = fptrunc x86_fp80 %call to float
+ %conv1 = fpext float %conv to x86_fp80
+ ret x86_fp80 %conv1
+}
>From 8ecaeb21a47a75838e35c28ec4aa8d8cf3be4c4e Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 1 Aug 2026 21:20:34 -0400
Subject: [PATCH 2/9] [X86] Eliminate dead SSE loads and stores after rewriting
stack spills
These spills are redundant and can be removed.
---
llvm/lib/Target/X86/X86FixupInstTuning.cpp | 249 ++++++++++++++++++++
llvm/test/CodeGen/X86/fp-intrinsics.ll | 40 +---
llvm/test/CodeGen/X86/fp80-strict-scalar.ll | 12 +-
llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll | 4 +-
llvm/test/CodeGen/X86/scalar-int-to-fp.ll | 84 ++-----
llvm/test/CodeGen/X86/x87-inout-bounce.ll | 31 ++-
6 files changed, 309 insertions(+), 111 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index 621fd35a03cd5..dd0d56f27be1e 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -29,7 +29,9 @@
#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/IR/Analysis.h"
using namespace llvm;
@@ -47,6 +49,8 @@ class X86FixupInstTuningImpl {
bool processInstruction(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I);
+ bool processSpills(MachineBasicBlock &MBB, MachineFunction &MF);
+
const X86InstrInfo *TII = nullptr;
const X86Subtarget *ST = nullptr;
const MCSchedModel *SM = nullptr;
@@ -88,6 +92,250 @@ static std::optional<bool> CmpOptionals(T NewVal, T CurVal) {
return std::nullopt;
}
+bool X86FixupInstTuningImpl::processSpills(MachineBasicBlock &MBB,
+ MachineFunction &MF) {
+ bool Changed = false;
+
+ // Tracks a load->store chain: load from OrigFI into Reg, store Reg to
+ // SpillFI. We want to redirect later loads from SpillFI to OrigFI.
+ struct SpillEntry {
+ SmallVector<MachineOperand, X86::AddrNumOperands> OrigMOs;
+ MachineInstr *LoadMI = nullptr; // The original load from OrigFI.
+ MachineInstr *StoreMI = nullptr; // The store to SpillFI.
+ MCRegister LoadReg; // The register used as intermediary.
+ unsigned UseCount = 0; // Number of loads from SpillFI seen.
+ unsigned RewriteCount = 0; // Number successfully rewritten.
+ LocationSize Size = LocationSize::beforeOrAfterPointer();
+ int64_t Offset = 0;
+ int OrigFI = -1;
+ bool Invalid = false;
+ };
+
+ // Maps SpillFI -> SpillEntry (the redirect info for that slot).
+ DenseMap<int, SpillEntry> SpillMap;
+
+ // Maps physical register -> (OrigFI, address operands, LoadMI).
+ // Keyed by the canonical (largest) super-register to handle aliasing.
+ struct RegEntry {
+ SmallVector<MachineOperand, X86::AddrNumOperands> MOs;
+ MachineInstr *LoadMI = nullptr;
+ int FI = -1;
+ LocationSize Size = LocationSize::beforeOrAfterPointer();
+ };
+ DenseMap<MCRegister, RegEntry> RegToFI;
+
+ auto InvalidateReg = [&](MCRegister Reg) {
+ for (MCRegAliasIterator AI(Reg, TRI, /*IncludeSelf=*/true); AI.isValid();
+ ++AI)
+ RegToFI.erase(*AI);
+ for (auto &[FI, SE] : SpillMap) {
+ if (SE.Invalid) continue;
+ bool UsesReg = false;
+ for (const MachineOperand &MO : SE.OrigMOs) {
+ if (MO.isReg() && MO.getReg() && TRI->regsOverlap(MO.getReg(), Reg)) {
+ UsesReg = true;
+ break;
+ }
+ }
+ if (UsesReg)
+ SE.Invalid = true;
+ }
+ };
+
+ auto IsSafeToEraseLoad = [&](MachineInstr *LoadMI, MachineInstr *StoreMI,
+ MCRegister Reg) -> bool {
+ // Walk forward from LoadMI. The register must not be read by anything
+ // other than StoreMI, and must be redefined (or reach end-of-block
+ // without being live-out).
+ for (MachineBasicBlock::iterator I = std::next(LoadMI->getIterator()),
+ E = MBB.end();
+ I != E; ++I) {
+ if (&*I == StoreMI)
+ continue;
+ if (I->readsRegister(Reg, TRI))
+ return false;
+ if (I->definesRegister(Reg, TRI))
+ return true;
+ }
+ // Check if the register is live-out of the block.
+ for (MCRegAliasIterator AI(Reg, TRI, /*IncludeSelf=*/true); AI.isValid();
+ ++AI) {
+ for (MachineBasicBlock *Succ : MBB.successors()) {
+ if (Succ->isLiveIn(*AI))
+ return false;
+ }
+ }
+ return true;
+ };
+
+ for (MachineInstr &MI : MBB) {
+ if (MI.isCall()) {
+ // Calls clobber registers. Memory state (SpillMap) is preserved
+ // because local stack slots don't escape through calls.
+ RegToFI.clear();
+ continue;
+ }
+
+ int LoadedFI = -1;
+ MCRegister LoadedReg(TII->isLoadFromStackSlotPostFE(MI, LoadedFI));
+
+ if (LoadedReg) {
+ auto It = SpillMap.find(LoadedFI);
+ if (It != SpillMap.end() && !MI.memoperands_empty()) {
+ // This load reads from a SpillFI we're tracking. Rewrite it to
+ // read directly from OrigFI.
+ SpillEntry &SE = It->second;
+ const MachineMemOperand *MMO = MI.memoperands().front();
+ if (MMO->getSize() == SE.Size && MMO->getOffset() == SE.Offset) {
+ SE.UseCount++;
+ if (!SE.Invalid) {
+ int MemIdx = X86::getFirstAddrOperandIdx(MI);
+ if (MemIdx >= 0) {
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ MI.getOperand(MemIdx + i) = SE.OrigMOs[i];
+ // Drop stale MMOs — they still reference SpillFI.
+ MI.dropMemRefs(MF);
+ SE.RewriteCount++;
+ Changed = true;
+ }
+ }
+ }
+ }
+ }
+
+ // MMO-based fallback: handles x87 loads (LD_F32m, LD_F64m, etc.) that
+ // aren't recognized by isLoadFromStackSlotPostFE because they aren't
+ // in isFrameLoadOpcode, but do have valid FixedStackPseudoSourceValue
+ // MMOs. We can rewrite address operands but cannot delete the store
+ // (since we can't track all uses via this path reliably).
+ if (!LoadedReg && MI.mayLoad()) {
+ int MemIdx = X86::getFirstAddrOperandIdx(MI);
+ if (MemIdx >= 0) {
+ for (const MachineMemOperand *MMO : MI.memoperands()) {
+ if (!MMO->isLoad())
+ continue;
+ const auto *FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(
+ MMO->getPseudoValue());
+ if (!FSPV)
+ continue;
+ int FI = FSPV->getFrameIndex();
+ auto It = SpillMap.find(FI);
+ if (It != SpillMap.end()) {
+ SpillEntry &SE = It->second;
+ if (MMO->getSize() == SE.Size && MMO->getOffset() == SE.Offset) {
+ SE.UseCount++;
+ if (!SE.Invalid) {
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ MI.getOperand(MemIdx + i) = SE.OrigMOs[i];
+ MI.dropMemRefs(MF);
+ SE.RewriteCount++;
+ Changed = true;
+ }
+ }
+ break;
+ }
+ }
+ }
+ }
+
+ int StoredFI = -1;
+ MCRegister StoredReg(TII->isStoreToStackSlotPostFE(MI, StoredFI));
+
+ if (StoredReg) {
+ // If the stored register was loaded from a known FI, record the chain.
+ auto It = RegToFI.find(StoredReg);
+ if (It != RegToFI.end() && !MI.memoperands_empty()) {
+ const MachineMemOperand *MMO = MI.memoperands().front();
+ if (MMO->getSize() == It->second.Size && MMO->getSize().hasValue()) {
+ SpillEntry SE;
+ SE.OrigMOs = It->second.MOs;
+ SE.LoadMI = It->second.LoadMI;
+ SE.LoadReg = StoredReg;
+ SE.StoreMI = &MI;
+ SE.Size = MMO->getSize();
+ SE.Offset = MMO->getOffset();
+ SE.OrigFI = It->second.FI;
+ SpillMap[StoredFI] = SE;
+ } else {
+ SpillMap.erase(StoredFI);
+ }
+ } else {
+ // The store overwrites SpillFI with unknown data — invalidate.
+ SpillMap.erase(StoredFI);
+ }
+ }
+
+ // If the instruction writes to memory but we couldn't identify it as a
+ // simple stack slot store, check MMOs for stores to tracked SpillFIs.
+ // Only invalidate what we can't identify.
+ if (MI.mayStore() && !StoredReg) {
+ bool HasUnknownStore = false;
+ for (const MachineMemOperand *MMO : MI.memoperands()) {
+ if (!MMO->isStore())
+ continue;
+ const auto *FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(
+ MMO->getPseudoValue());
+ if (FSPV) {
+ // Known FI store — invalidate just that entry.
+ int FI = FSPV->getFrameIndex();
+ SpillMap.erase(FI);
+ SmallVector<int, 4> ToErase;
+ for (auto &[KeyFI, SE] : SpillMap) {
+ if (SE.OrigFI == FI)
+ ToErase.push_back(KeyFI);
+ }
+ for (int KeyFI : ToErase)
+ SpillMap.erase(KeyFI);
+ } else {
+ HasUnknownStore = true;
+ }
+ }
+ if (HasUnknownStore)
+ SpillMap.clear();
+ }
+
+ // Any register def (explicit or implicit) invalidates all aliases.
+ for (const MachineOperand &MO : MI.operands()) {
+ if (MO.isReg() && MO.isDef() && MO.getReg().isPhysical())
+ InvalidateReg(MO.getReg());
+ }
+
+ // --- Step 5: Track loads from stack slots ---
+ if (LoadedReg) {
+ int MemIdx = X86::getFirstAddrOperandIdx(MI);
+ if (MemIdx >= 0 && !MI.memoperands_empty()) {
+ RegEntry RE;
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ RE.MOs.push_back(MI.getOperand(MemIdx + i));
+ RE.LoadMI = &MI;
+ RE.FI = LoadedFI;
+ RE.Size = MI.memoperands().front()->getSize();
+ RegToFI[LoadedReg] = RE;
+ }
+ }
+ }
+
+ SmallPtrSet<MachineInstr *, 4> ToErase;
+ for (auto &[FI, SE] : SpillMap) {
+ // Only delete the store if ALL loads from SpillFI were rewritten.
+ if (SE.RewriteCount > 0 && SE.RewriteCount == SE.UseCount) {
+ if (SE.StoreMI)
+ ToErase.insert(SE.StoreMI);
+ // Only delete the load if its register is provably dead.
+ if (SE.LoadMI && SE.StoreMI &&
+ IsSafeToEraseLoad(SE.LoadMI, SE.StoreMI, SE.LoadReg))
+ ToErase.insert(SE.LoadMI);
+ }
+ }
+
+ for (MachineInstr *MI : ToErase) {
+ MI->eraseFromParent();
+ Changed = true;
+ }
+
+ return Changed;
+}
+
bool X86FixupInstTuningImpl::processInstruction(
MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
@@ -712,6 +960,7 @@ bool X86FixupInstTuningImpl::runOnMachineFunction(MachineFunction &MF) {
SM = &ST->getSchedModel();
for (MachineBasicBlock &MBB : MF) {
+ Changed |= processSpills(MBB, MF);
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
if (processInstruction(MF, MBB, I)) {
++NumInstChanges;
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
index 5d69a217fb402..abfa265092848 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -1080,8 +1080,6 @@ define i64 @f20s64(double %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
-; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
@@ -2076,9 +2074,7 @@ define double @sifdi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2205,9 +2201,7 @@ define float @siffi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2407,10 +2401,8 @@ define double @uifdi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2420,10 +2412,8 @@ define double @uifdi(i32 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
-; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: fildll (%esp)
+; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
@@ -2459,12 +2449,10 @@ define double @uifdl(i64 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -2484,10 +2472,7 @@ define double @uifdl(i64 %x) #0 {
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: wait
-; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT: movsd %xmm0, (%esp)
-; X86-SSE-NEXT: fldl (%esp)
+; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $28, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
@@ -2629,10 +2614,8 @@ define float @uiffi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2642,8 +2625,6 @@ define float @uiffi(i32 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
-; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
@@ -2681,10 +2662,8 @@ define float @uiffl(i64 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
@@ -2706,10 +2685,7 @@ define float @uiffl(i64 %x) #0 {
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: wait
-; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE-NEXT: movss %xmm0, (%esp)
-; X86-SSE-NEXT: flds (%esp)
+; X86-SSE-NEXT: flds {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
diff --git a/llvm/test/CodeGen/X86/fp80-strict-scalar.ll b/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
index b9b1ae60d479e..6276c36677d59 100644
--- a/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
+++ b/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
@@ -737,9 +737,7 @@ define x86_fp80 @sint32_to_fp80(i32 %x) #0 {
; X86: # %bb.0:
; X86-NEXT: pushl %eax
; X86-NEXT: .cfi_def_cfa_offset 8
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl %eax, (%esp)
-; X86-NEXT: fildl (%esp)
+; X86-NEXT: fildl {{[0-9]+}}(%esp)
; X86-NEXT: wait
; X86-NEXT: popl %eax
; X86-NEXT: .cfi_def_cfa_offset 4
@@ -866,10 +864,8 @@ define x86_fp80 @uint32_to_fp80(i32 %x) #0 {
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-NEXT: fildll (%esp)
+; X86-NEXT: fildll 8(%ebp)
; X86-NEXT: wait
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
@@ -899,12 +895,10 @@ define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: shrl $31, %ecx
-; X86-NEXT: fildll (%esp)
+; X86-NEXT: fildll 8(%ebp)
; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X86-NEXT: wait
; X86-NEXT: movl %ebp, %esp
diff --git a/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll b/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
index 7f58fffe2b5ed..096bd824e1bba 100644
--- a/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
+++ b/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
@@ -35,7 +35,7 @@ define double @fpext_float_to_double(float %f) nounwind {
; GLOBAL-X86-NEXT: pushl %eax
; GLOBAL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GLOBAL-X86-NEXT: movl %eax, (%esp)
-; GLOBAL-X86-NEXT: flds (%esp)
+; GLOBAL-X86-NEXT: flds {{[0-9]+}}(%esp)
; GLOBAL-X86-NEXT: popl %eax
; GLOBAL-X86-NEXT: retl
%1 = fpext float %f to double
@@ -65,7 +65,7 @@ define x86_fp80 @fpext_float_to_x86_fp80(float %f) nounwind {
; GLOBAL-X86-NEXT: pushl %eax
; GLOBAL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; GLOBAL-X86-NEXT: movl %eax, (%esp)
-; GLOBAL-X86-NEXT: flds (%esp)
+; GLOBAL-X86-NEXT: flds {{[0-9]+}}(%esp)
; GLOBAL-X86-NEXT: popl %eax
; GLOBAL-X86-NEXT: retl
;
diff --git a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
index 43c1a84f7cd6c..067bdd881e7f5 100644
--- a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
@@ -53,10 +53,8 @@ define float @u32_to_f(i32 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
-; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE1_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
@@ -69,10 +67,8 @@ define float @u32_to_f(i32 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $8, %esp
-; X87-NEXT: movl 8(%ebp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp
; X87-NEXT: retl
@@ -112,9 +108,7 @@ define float @s32_to_f(i32 %a) nounwind {
; X87-LABEL: s32_to_f:
; X87: # %bb.0:
; X87-NEXT: pushl %eax
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: popl %eax
; X87-NEXT: retl
%r = sitofp i32 %a to float
@@ -167,10 +161,8 @@ define double @u32_to_d(i32 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $8, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
-; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fildll (%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl
@@ -181,10 +173,8 @@ define double @u32_to_d(i32 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $8, %esp
-; X87-NEXT: movl 8(%ebp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp
; X87-NEXT: retl
@@ -232,18 +222,14 @@ define double @s32_to_d(i32 %a) nounwind {
; SSE1_32-LABEL: s32_to_d:
; SSE1_32: # %bb.0:
; SSE1_32-NEXT: pushl %eax
-; SSE1_32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE1_32-NEXT: movl %eax, (%esp)
-; SSE1_32-NEXT: fildl (%esp)
+; SSE1_32-NEXT: fildl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: popl %eax
; SSE1_32-NEXT: retl
;
; X87-LABEL: s32_to_d:
; X87: # %bb.0:
; X87-NEXT: pushl %eax
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: popl %eax
; X87-NEXT: retl
%r = sitofp i32 %a to double
@@ -257,10 +243,8 @@ define x86_fp80 @u32_to_x(i32 %a) nounwind {
; CHECK32-NEXT: movl %esp, %ebp
; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp
-; CHECK32-NEXT: movl 8(%ebp), %eax
-; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; CHECK32-NEXT: fildll (%esp)
+; CHECK32-NEXT: fildll 8(%ebp)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl
@@ -279,9 +263,7 @@ define x86_fp80 @s32_to_x(i32 %a) nounwind {
; CHECK32-LABEL: s32_to_x:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %eax
-; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT: movl %eax, (%esp)
-; CHECK32-NEXT: fildl (%esp)
+; CHECK32-NEXT: fildl {{[0-9]+}}(%esp)
; CHECK32-NEXT: popl %eax
; CHECK32-NEXT: retl
;
@@ -314,10 +296,8 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512DQ_32-LABEL: u64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
-; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtuqq2ps %zmm0, %ymm0
-; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
-; AVX512DQ_32-NEXT: flds (%esp)
+; AVX512DQ_32-NEXT: flds {{[0-9]+}}(%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
@@ -335,9 +315,7 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX512F_32-NEXT: fstps {{[0-9]+}}(%esp)
-; AVX512F_32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX512F_32-NEXT: vmovss %xmm0, (%esp)
-; AVX512F_32-NEXT: flds (%esp)
+; AVX512F_32-NEXT: flds {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: movl %ebp, %esp
; AVX512F_32-NEXT: popl %ebp
; AVX512F_32-NEXT: retl
@@ -355,9 +333,7 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE2_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE2_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE2_32-NEXT: fstps {{[0-9]+}}(%esp)
-; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2_32-NEXT: movss %xmm0, (%esp)
-; SSE2_32-NEXT: flds (%esp)
+; SSE2_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl
@@ -384,19 +360,15 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $24, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: fldl 8(%ebp)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE1_32-NEXT: movss %xmm0, (%esp)
-; SSE1_32-NEXT: flds (%esp)
+; SSE1_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl
@@ -407,12 +379,10 @@ define float @u64_to_f(i64 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
-; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll {{[0-9]+}}(%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
@@ -443,10 +413,8 @@ define float @s64_to_f(i64 %a) nounwind {
; AVX512DQ_32-LABEL: s64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
-; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtqq2ps %zmm0, %ymm0
-; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
-; AVX512DQ_32-NEXT: flds (%esp)
+; AVX512DQ_32-NEXT: flds {{[0-9]+}}(%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
@@ -695,12 +663,10 @@ define double @u64_to_d(i64 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
-; SSE1_32-NEXT: fildll (%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
@@ -714,12 +680,10 @@ define double @u64_to_d(i64 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
-; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -816,12 +780,10 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
-; SSE1_32-NEXT: fildll (%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
@@ -835,12 +797,10 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
-; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -1070,12 +1030,10 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK32-NEXT: movl %esp, %ebp
; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp
-; CHECK32-NEXT: movl 8(%ebp), %eax
; CHECK32-NEXT: movl 12(%ebp), %ecx
; CHECK32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: shrl $31, %ecx
-; CHECK32-NEXT: fildll (%esp)
+; CHECK32-NEXT: fildll 8(%ebp)
; CHECK32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
diff --git a/llvm/test/CodeGen/X86/x87-inout-bounce.ll b/llvm/test/CodeGen/X86/x87-inout-bounce.ll
index 161ca2c1742b1..d07d40dd7cc8f 100644
--- a/llvm/test/CodeGen/X86/x87-inout-bounce.ll
+++ b/llvm/test/CodeGen/X86/x87-inout-bounce.ll
@@ -28,11 +28,9 @@ define float @example_float() {
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: calll returns_float at PLT
; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
-; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: movss %xmm0, (%esp) # 4-byte Spill
; CHECK-NEXT: calll returns_float at PLT
; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
-; CHECK-NEXT: movss (%esp), %xmm0 # 4-byte Reload
+; CHECK-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: addss {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT: movss %xmm0, (%esp) # 4-byte Spill
@@ -80,8 +78,6 @@ define x86_fp80 @testC() {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: calll returns_long_double at PLT
; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
-; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 4
@@ -92,3 +88,28 @@ entry:
%conv1 = fpext float %conv to x86_fp80
ret x86_fp80 %conv1
}
+
+declare float @returns_x87_float()
+
+define float @testA() {
+; CHECK-LABEL: testA:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subl $28, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: calll returns_x87_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: calll returns_x87_float at PLT
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload
+; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: addss {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: addl $28, %esp
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: retl
+ %1 = call float @returns_x87_float()
+ %2 = call float @returns_x87_float()
+ %3 = fadd float %1, %2
+ ret float %3
+}
>From 13980d9e8e7a0891a5d570cdb9f40a8c97e2d925 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:44:00 -0400
Subject: [PATCH 3/9] [X86] Fix X86FixupInstTuning aliasing, liveness, and size
mismatches
Fixes a miscompile in X86FixupInstTuning where it could rewrite loads
incorrectly due to failing to invalidate tracked spilled entries when:
1. The memory location of the original stack slot is clobbered.
2. A register used in the address of the tracked load is redefined.
3. The load and store sizes do not match.
Also switches SpillMap erasure while iterating to a two-pass approach
to fix a compilation error.
---
.../vector-interleaved-load-i8-stride-6.ll | 8 ++---
.../vector-interleaved-load-i8-stride-7.ll | 32 +++++++++----------
.../vector-interleaved-store-i16-stride-7.ll | 2 +-
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
index 054df4c00e0a3..e4745e3d17cae 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
@@ -5170,7 +5170,7 @@ define void @load_i8_stride6_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: por %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa {{.*#+}} xmm7 = [65535,0,65535,65535,0,65535,65535,0]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: pand %xmm7, %xmm4
; SSE-NEXT: por {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Folded Reload
; SSE-NEXT: movdqa %xmm4, %xmm0
@@ -5214,7 +5214,7 @@ define void @load_i8_stride6_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pand %xmm10, %xmm3
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm13 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: pand %xmm7, %xmm13
; SSE-NEXT: por {{[-0-9]+}}(%r{{[sb]}}p), %xmm13 # 16-byte Folded Reload
; SSE-NEXT: movdqa %xmm13, %xmm0
@@ -5256,7 +5256,7 @@ define void @load_i8_stride6_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa %xmm10, %xmm9
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: pand %xmm7, %xmm10
; SSE-NEXT: por {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Folded Reload
; SSE-NEXT: movdqa %xmm10, %xmm0
@@ -5299,7 +5299,7 @@ define void @load_i8_stride6_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa %xmm9, %xmm1
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movdqa (%rsp), %xmm0
; SSE-NEXT: pand %xmm7, %xmm0
; SSE-NEXT: por {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
index 319735da0a6c4..2d5e25c136a96 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
@@ -4176,7 +4176,7 @@ define void @load_i8_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm10, %xmm0
; SSE-NEXT: pandn %xmm7, %xmm0
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: por %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm0
@@ -4242,7 +4242,7 @@ define void @load_i8_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa {{.*#+}} xmm11 = [65535,65535,65535,0,65535,65535,0,65535]
; SSE-NEXT: movdqa %xmm11, %xmm0
; SSE-NEXT: pandn %xmm8, %xmm0
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pand %xmm11, %xmm1
; SSE-NEXT: por %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
@@ -4374,7 +4374,7 @@ define void @load_i8_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[2,1,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1],xmm5[2],xmm0[2],xmm5[3],xmm0[3]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
; SSE-NEXT: pandn %xmm0, %xmm3
@@ -4551,7 +4551,7 @@ define void @load_i8_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm1[0,1,2,1]
; SSE-NEXT: pshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,5,7,6,7]
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: punpckhbw {{.*#+}} xmm8 = xmm8[8],xmm9[8],xmm8[9],xmm9[9],xmm8[10],xmm9[10],xmm8[11],xmm9[11],xmm8[12],xmm9[12],xmm8[13],xmm9[13],xmm8[14],xmm9[14],xmm8[15],xmm9[15]
; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
@@ -4606,7 +4606,7 @@ define void @load_i8_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm2[0,1,2,1]
; SSE-NEXT: pshufhw {{.*#+}} xmm10 = xmm10[0,1,2,3,5,7,6,7]
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm10[4],xmm0[5],xmm10[5],xmm0[6],xmm10[6],xmm0[7],xmm10[7]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm11[8],xmm2[9],xmm11[9],xmm2[10],xmm11[10],xmm2[11],xmm11[11],xmm2[12],xmm11[12],xmm2[13],xmm11[13],xmm2[14],xmm11[14],xmm2[15],xmm11[15]
; SSE-NEXT: pxor %xmm12, %xmm12
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
@@ -8279,7 +8279,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa %xmm15, %xmm9
; SSE-NEXT: movdqa %xmm15, %xmm0
; SSE-NEXT: pandn %xmm7, %xmm0
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pand %xmm15, %xmm1
; SSE-NEXT: por %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
@@ -8343,7 +8343,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm15, %xmm0
; SSE-NEXT: pandn %xmm11, %xmm0
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: movdqa (%rsp), %xmm1
; SSE-NEXT: pand %xmm15, %xmm1
; SSE-NEXT: por %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
@@ -8405,7 +8405,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa %xmm9, %xmm0
; SSE-NEXT: pandn {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pand %xmm9, %xmm1
; SSE-NEXT: movdqa %xmm9, %xmm13
; SSE-NEXT: por %xmm0, %xmm1
@@ -8539,7 +8539,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15]
; SSE-NEXT: pxor %xmm6, %xmm6
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
@@ -8592,7 +8592,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,1,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
; SSE-NEXT: pandn %xmm0, %xmm4
@@ -8644,7 +8644,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[2,1,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
; SSE-NEXT: pandn %xmm0, %xmm4
@@ -8697,7 +8697,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,1,2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1],xmm4[2],xmm0[2],xmm4[3],xmm0[3]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm6 # 16-byte Reload
; SSE-NEXT: pandn %xmm0, %xmm6
@@ -9001,7 +9001,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,1]
; SSE-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,7,6,7]
; SSE-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm3[8],xmm1[9],xmm3[9],xmm1[10],xmm3[10],xmm1[11],xmm3[11],xmm1[12],xmm3[12],xmm1[13],xmm3[13],xmm1[14],xmm3[14],xmm1[15],xmm3[15]
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
; SSE-NEXT: pandn %xmm1, %xmm10
@@ -9054,7 +9054,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm4[0,1,2,1]
; SSE-NEXT: pshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,5,7,6,7]
; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm8[4],xmm1[5],xmm8[5],xmm1[6],xmm8[6],xmm1[7],xmm8[7]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
+; SSE-NEXT: movdqa (%rsp), %xmm4
; SSE-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm0[8],xmm4[9],xmm0[9],xmm4[10],xmm0[10],xmm4[11],xmm0[11],xmm4[12],xmm0[12],xmm4[13],xmm0[13],xmm4[14],xmm0[14],xmm4[15],xmm0[15]
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm12 # 16-byte Reload
; SSE-NEXT: pandn %xmm4, %xmm12
@@ -9107,7 +9107,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm0[0,1,2,1]
; SSE-NEXT: pshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,5,7,6,7]
; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm8[4],xmm1[5],xmm8[5],xmm1[6],xmm8[6],xmm1[7],xmm8[7]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
+; SSE-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm13[8],xmm5[9],xmm13[9],xmm5[10],xmm13[10],xmm5[11],xmm13[11],xmm5[12],xmm13[12],xmm5[13],xmm13[13],xmm5[14],xmm13[14],xmm5[15],xmm13[15]
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm13 # 16-byte Reload
@@ -9160,7 +9160,7 @@ define void @load_i8_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm2[0,1,2,1]
; SSE-NEXT: pshufhw {{.*#+}} xmm8 = xmm8[0,1,2,3,5,7,6,7]
; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm8[4],xmm1[5],xmm8[5],xmm1[6],xmm8[6],xmm1[7],xmm8[7]
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm14[8],xmm2[9],xmm14[9],xmm2[10],xmm14[10],xmm2[11],xmm14[11],xmm2[12],xmm14[12],xmm2[13],xmm14[13],xmm2[14],xmm14[14],xmm2[15],xmm14[15]
; SSE-NEXT: pxor %xmm15, %xmm15
; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
index 6e0d9efbb083c..04927574be122 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
@@ -8752,7 +8752,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; SSE-NEXT: movaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Folded Reload
; SSE-NEXT: # xmm9 = xmm9[0],mem[0]
-; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: shufps $212, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0,1],mem[1,3]
; SSE-NEXT: shufps {{.*#+}} xmm9 = xmm9[2,0],xmm0[0,2]
>From ff8d525c2500e1cefa2f3e5490db77354243b380 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:48:39 -0400
Subject: [PATCH 4/9] Update X86FixupInstTuning.cpp
---
llvm/lib/Target/X86/X86FixupInstTuning.cpp | 26 ++++++++++++++++------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index dd0d56f27be1e..a80a169d66542 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -173,6 +173,7 @@ bool X86FixupInstTuningImpl::processSpills(MachineBasicBlock &MBB,
// Calls clobber registers. Memory state (SpillMap) is preserved
// because local stack slots don't escape through calls.
RegToFI.clear();
+ SpillMap.clear();
continue;
}
@@ -304,13 +305,24 @@ bool X86FixupInstTuningImpl::processSpills(MachineBasicBlock &MBB,
if (LoadedReg) {
int MemIdx = X86::getFirstAddrOperandIdx(MI);
if (MemIdx >= 0 && !MI.memoperands_empty()) {
- RegEntry RE;
- for (int i = 0; i < X86::AddrNumOperands; ++i)
- RE.MOs.push_back(MI.getOperand(MemIdx + i));
- RE.LoadMI = &MI;
- RE.FI = LoadedFI;
- RE.Size = MI.memoperands().front()->getSize();
- RegToFI[LoadedReg] = RE;
+ bool ClobbersAddr = false;
+ for (int i = 0; i < X86::AddrNumOperands; ++i) {
+ const MachineOperand &MO = MI.getOperand(MemIdx + i);
+ if (MO.isReg() && MO.getReg() &&
+ MI.definesRegister(MO.getReg(), TRI)) {
+ ClobbersAddr = true;
+ break;
+ }
+ }
+ if (!ClobbersAddr) {
+ RegEntry RE;
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ RE.MOs.push_back(MI.getOperand(MemIdx + i));
+ RE.LoadMI = &MI;
+ RE.FI = LoadedFI;
+ RE.Size = MI.memoperands().front()->getSize();
+ RegToFI[LoadedReg] = RE;
+ }
}
}
}
>From cc10c63159343b60bd2d5a3b30d6eb4e72f2848b Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:49:17 -0400
Subject: [PATCH 5/9] [X86] Fix self-invalidating loads and call clobbers in
X86FixupInstTuning
Addresses a critical miscompile where an instruction could redefine its
own address register (e.g., movl 4(%eax), %eax) and falsely seed
RegToFI with stale address operands because load tracking occurred after
register invalidation. It now skips load tracking if the instruction
redefines any register used in its address operands.
Also clears SpillMap across calls to ensure caller-saved registers
in OrigMOs do not survive and corrupt subsequent rewrites.
---
llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll | 4 ----
1 file changed, 4 deletions(-)
diff --git a/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll b/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
index 096bd824e1bba..c1da2d6e73be6 100644
--- a/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
+++ b/llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
@@ -33,8 +33,6 @@ define double @fpext_float_to_double(float %f) nounwind {
; GLOBAL-X86-LABEL: fpext_float_to_double:
; GLOBAL-X86: # %bb.0:
; GLOBAL-X86-NEXT: pushl %eax
-; GLOBAL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; GLOBAL-X86-NEXT: movl %eax, (%esp)
; GLOBAL-X86-NEXT: flds {{[0-9]+}}(%esp)
; GLOBAL-X86-NEXT: popl %eax
; GLOBAL-X86-NEXT: retl
@@ -63,8 +61,6 @@ define x86_fp80 @fpext_float_to_x86_fp80(float %f) nounwind {
; GLOBAL-X86-LABEL: fpext_float_to_x86_fp80:
; GLOBAL-X86: # %bb.0:
; GLOBAL-X86-NEXT: pushl %eax
-; GLOBAL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; GLOBAL-X86-NEXT: movl %eax, (%esp)
; GLOBAL-X86-NEXT: flds {{[0-9]+}}(%esp)
; GLOBAL-X86-NEXT: popl %eax
; GLOBAL-X86-NEXT: retl
>From b1541f041dce86677b0699c21bf526edf77ef048 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:52:57 -0400
Subject: [PATCH 6/9] Update X86FixupInstTuning.cpp
---
llvm/lib/Target/X86/X86FixupInstTuning.cpp | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index a80a169d66542..63e2923743f04 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -23,14 +23,19 @@
#include "X86.h"
#include "X86InstrInfo.h"
-#include "X86RegisterInfo.h"
#include "X86Subtarget.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/IR/Analysis.h"
@@ -188,6 +193,10 @@ bool X86FixupInstTuningImpl::processSpills(MachineBasicBlock &MBB,
SpillEntry &SE = It->second;
const MachineMemOperand *MMO = MI.memoperands().front();
if (MMO->getSize() == SE.Size && MMO->getOffset() == SE.Offset) {
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ int64_t OrigSize = MFI.getObjectSize(SE.OrigFI);
+ if (SE.Size.hasValue() && OrigSize < (int64_t)SE.Size.getValue())
+ continue;
SE.UseCount++;
if (!SE.Invalid) {
int MemIdx = X86::getFirstAddrOperandIdx(MI);
@@ -224,6 +233,10 @@ bool X86FixupInstTuningImpl::processSpills(MachineBasicBlock &MBB,
if (It != SpillMap.end()) {
SpillEntry &SE = It->second;
if (MMO->getSize() == SE.Size && MMO->getOffset() == SE.Offset) {
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ int64_t OrigSize = MFI.getObjectSize(SE.OrigFI);
+ if (SE.Size.hasValue() && OrigSize < (int64_t)SE.Size.getValue())
+ break;
SE.UseCount++;
if (!SE.Invalid) {
for (int i = 0; i < X86::AddrNumOperands; ++i)
>From 212162aa876946a0e9646dc780712f15ac0a62ca Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:53:20 -0400
Subject: [PATCH 7/9] [X86] Fix X86FixupInstTuning rewriting loads with
mismatched access sizes
Addresses a silent miscompile where 8-byte loads (like fildll) could be
redirected to 4-byte original argument stack slots (like those used for
u32->f64 bounce buffers). This would cause the upper 4 bytes of the load
to read garbage from adjacent stack memory.
Adds a strict size check ensuring that the original stack object size
is at least as large as the memory access size before rewriting.
---
llvm/test/CodeGen/X86/scalar-int-to-fp.ll | 56 +++++++++++++++++------
1 file changed, 42 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
index 067bdd881e7f5..3df35d2a1fb1d 100644
--- a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
@@ -53,8 +53,10 @@ define float @u32_to_f(i32 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
+; SSE1_32-NEXT: movl 8(%ebp), %eax
+; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fildll 8(%ebp)
+; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE1_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
@@ -67,8 +69,10 @@ define float @u32_to_f(i32 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $8, %esp
+; X87-NEXT: movl 8(%ebp), %eax
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll 8(%ebp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp
; X87-NEXT: retl
@@ -161,8 +165,10 @@ define double @u32_to_d(i32 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $8, %esp
+; SSE1_32-NEXT: movl 8(%ebp), %eax
+; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fildll 8(%ebp)
+; SSE1_32-NEXT: fildll (%esp)
; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl
@@ -173,8 +179,10 @@ define double @u32_to_d(i32 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $8, %esp
+; X87-NEXT: movl 8(%ebp), %eax
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll 8(%ebp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp
; X87-NEXT: retl
@@ -243,8 +251,10 @@ define x86_fp80 @u32_to_x(i32 %a) nounwind {
; CHECK32-NEXT: movl %esp, %ebp
; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp
+; CHECK32-NEXT: movl 8(%ebp), %eax
+; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; CHECK32-NEXT: fildll 8(%ebp)
+; CHECK32-NEXT: fildll (%esp)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl
@@ -296,8 +306,10 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512DQ_32-LABEL: u64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
+; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtuqq2ps %zmm0, %ymm0
-; AVX512DQ_32-NEXT: flds {{[0-9]+}}(%esp)
+; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
+; AVX512DQ_32-NEXT: flds (%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
@@ -360,9 +372,11 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $24, %esp
+; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fldl 8(%ebp)
+; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
@@ -379,10 +393,12 @@ define float @u64_to_f(i64 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
+; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll 8(%ebp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
@@ -413,8 +429,10 @@ define float @s64_to_f(i64 %a) nounwind {
; AVX512DQ_32-LABEL: s64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
+; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtqq2ps %zmm0, %ymm0
-; AVX512DQ_32-NEXT: flds {{[0-9]+}}(%esp)
+; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
+; AVX512DQ_32-NEXT: flds (%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
@@ -663,10 +681,12 @@ define double @u64_to_d(i64 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
+; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
-; SSE1_32-NEXT: fildll 8(%ebp)
+; SSE1_32-NEXT: fildll (%esp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
@@ -680,10 +700,12 @@ define double @u64_to_d(i64 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
+; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll 8(%ebp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -780,10 +802,12 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
+; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
-; SSE1_32-NEXT: fildll 8(%ebp)
+; SSE1_32-NEXT: fildll (%esp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
@@ -797,10 +821,12 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
+; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll 8(%ebp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -1030,10 +1056,12 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK32-NEXT: movl %esp, %ebp
; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp
+; CHECK32-NEXT: movl 8(%ebp), %eax
; CHECK32-NEXT: movl 12(%ebp), %ecx
; CHECK32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: shrl $31, %ecx
-; CHECK32-NEXT: fildll 8(%ebp)
+; CHECK32-NEXT: fildll (%esp)
; CHECK32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
>From c6b1c1774ef7bfc5c591d07349cd4ea4f062c850 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:55:47 -0400
Subject: [PATCH 8/9] Update fp-intrinsics.ll
---
llvm/test/CodeGen/X86/fp-intrinsics.ll | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
index abfa265092848..cdd56f32a9781 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -2401,8 +2401,10 @@ define double @uifdi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
+; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll {{[0-9]+}}(%esp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: wait
; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2412,8 +2414,10 @@ define double @uifdi(i32 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
+; X86-SSE-NEXT: fildll (%esp)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
@@ -2449,10 +2453,12 @@ define double @uifdl(i64 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
+; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll {{[0-9]+}}(%esp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -2614,8 +2620,10 @@ define float @uiffi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
+; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll {{[0-9]+}}(%esp)
+; X87-NEXT: fildll (%esp)
; X87-NEXT: wait
; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2625,6 +2633,8 @@ define float @uiffi(i32 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
@@ -2662,8 +2672,10 @@ define float @uiffl(i64 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
+; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
>From 1b76abd27aea3f262b31aeddf90acd59b8e0efca Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 2 Aug 2026 13:57:49 -0400
Subject: [PATCH 9/9] [X86] Update test expectations for X86FixupInstTuning bug
fixes
Regenerates test expectations after fixing silent miscompiles
(mismatched size re-writes, address redefinitions, and call clobbers)
in X86FixupInstTuning.
---
.../CodeGen/X86/fp-strict-scalar-inttofp.ll | 28 ++++-------------
llvm/test/CodeGen/X86/ftrunc.ll | 4 +--
llvm/test/CodeGen/X86/scalar-fp-to-i64.ll | 30 +++++++------------
3 files changed, 19 insertions(+), 43 deletions(-)
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
index f0aa3827ce937..17aa07683b4f3 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll
@@ -249,9 +249,7 @@ define float @sitofp_i32tof32(i32 %x) #0 {
; X87: # %bb.0:
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -595,10 +593,7 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-X86-NEXT: fstps {{[0-9]+}}(%esp)
-; SSE-X86-NEXT: wait
-; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE-X86-NEXT: movss %xmm0, (%esp)
-; SSE-X86-NEXT: flds (%esp)
+; SSE-X86-NEXT: flds {{[0-9]+}}(%esp)
; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movl %ebp, %esp
; SSE-X86-NEXT: popl %ebp
@@ -637,10 +632,7 @@ define float @uitofp_i64tof32(i64 %x) #0 {
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-X86-NEXT: fstps {{[0-9]+}}(%esp)
-; AVX-X86-NEXT: wait
-; AVX-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-X86-NEXT: vmovss %xmm0, (%esp)
-; AVX-X86-NEXT: flds (%esp)
+; AVX-X86-NEXT: flds {{[0-9]+}}(%esp)
; AVX-X86-NEXT: wait
; AVX-X86-NEXT: movl %ebp, %esp
; AVX-X86-NEXT: popl %ebp
@@ -884,9 +876,7 @@ define double @sitofp_i32tof64(i32 %x) #0 {
; X87: # %bb.0:
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -1284,10 +1274,7 @@ define double @uitofp_i64tof64(i64 %x) #0 {
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-X86-NEXT: fstpl {{[0-9]+}}(%esp)
-; SSE-X86-NEXT: wait
-; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-X86-NEXT: movsd %xmm0, (%esp)
-; SSE-X86-NEXT: fldl (%esp)
+; SSE-X86-NEXT: fldl {{[0-9]+}}(%esp)
; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movl %ebp, %esp
; SSE-X86-NEXT: popl %ebp
@@ -1326,10 +1313,7 @@ define double @uitofp_i64tof64(i64 %x) #0 {
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-X86-NEXT: fstpl {{[0-9]+}}(%esp)
-; AVX-X86-NEXT: wait
-; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-X86-NEXT: vmovsd %xmm0, (%esp)
-; AVX-X86-NEXT: fldl (%esp)
+; AVX-X86-NEXT: fldl {{[0-9]+}}(%esp)
; AVX-X86-NEXT: wait
; AVX-X86-NEXT: movl %ebp, %esp
; AVX-X86-NEXT: popl %ebp
diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
index 1ab9040a2810f..599cea901196f 100644
--- a/llvm/test/CodeGen/X86/ftrunc.ll
+++ b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -513,7 +513,7 @@ define double @trunc_signed_f64_no_fast_math(double %x) nounwind {
; X86-AVX1-NEXT: subl $24, %esp
; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX1-NEXT: vmovsd %xmm0, (%esp)
-; X86-AVX1-NEXT: fldl (%esp)
+; X86-AVX1-NEXT: fldl 8(%ebp)
; X86-AVX1-NEXT: fisttpll (%esp)
; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX1-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
@@ -748,7 +748,7 @@ define double @trunc_signed_f64_disable_via_intrinsic(double %x) #0 {
; X86-AVX1-NEXT: subl $32, %esp
; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX1-NEXT: vmovsd %xmm0, (%esp)
-; X86-AVX1-NEXT: fldl (%esp)
+; X86-AVX1-NEXT: fldl 8(%ebp)
; X86-AVX1-NEXT: fisttpll (%esp)
; X86-AVX1-NEXT: xorl %eax, %eax
; X86-AVX1-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
diff --git a/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll b/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
index 3287869f2c601..cec58ca87d63d 100644
--- a/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
+++ b/llvm/test/CodeGen/X86/scalar-fp-to-i64.ll
@@ -339,7 +339,7 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-AVX512F-WIN-NEXT: subl $8, %esp
; X86-AVX512F-WIN-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX512F-WIN-NEXT: vmovss %xmm0, (%esp)
-; X86-AVX512F-WIN-NEXT: flds (%esp)
+; X86-AVX512F-WIN-NEXT: flds 8(%ebp)
; X86-AVX512F-WIN-NEXT: fisttpll (%esp)
; X86-AVX512F-WIN-NEXT: movl (%esp), %eax
; X86-AVX512F-WIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -352,7 +352,7 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-AVX512F-LIN-NEXT: subl $12, %esp
; X86-AVX512F-LIN-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX512F-LIN-NEXT: vmovss %xmm0, (%esp)
-; X86-AVX512F-LIN-NEXT: flds (%esp)
+; X86-AVX512F-LIN-NEXT: flds {{[0-9]+}}(%esp)
; X86-AVX512F-LIN-NEXT: fisttpll (%esp)
; X86-AVX512F-LIN-NEXT: movl (%esp), %eax
; X86-AVX512F-LIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -367,7 +367,7 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-SSE3-WIN-NEXT: subl $8, %esp
; X86-SSE3-WIN-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE3-WIN-NEXT: movss %xmm0, (%esp)
-; X86-SSE3-WIN-NEXT: flds (%esp)
+; X86-SSE3-WIN-NEXT: flds 8(%ebp)
; X86-SSE3-WIN-NEXT: fisttpll (%esp)
; X86-SSE3-WIN-NEXT: movl (%esp), %eax
; X86-SSE3-WIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -380,7 +380,7 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-SSE3-LIN-NEXT: subl $12, %esp
; X86-SSE3-LIN-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE3-LIN-NEXT: movss %xmm0, (%esp)
-; X86-SSE3-LIN-NEXT: flds (%esp)
+; X86-SSE3-LIN-NEXT: flds {{[0-9]+}}(%esp)
; X86-SSE3-LIN-NEXT: fisttpll (%esp)
; X86-SSE3-LIN-NEXT: movl (%esp), %eax
; X86-SSE3-LIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -398,9 +398,7 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-SSE2-WIN-NEXT: movl %esp, %ebp
; X86-SSE2-WIN-NEXT: andl $-8, %esp
; X86-SSE2-WIN-NEXT: subl $16, %esp
-; X86-SSE2-WIN-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE2-WIN-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
-; X86-SSE2-WIN-NEXT: flds {{[0-9]+}}(%esp)
+; X86-SSE2-WIN-NEXT: flds 8(%ebp)
; X86-SSE2-WIN-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE2-WIN-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE2-WIN-NEXT: orl $3072, %eax # imm = 0xC00
@@ -408,7 +406,7 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-SSE2-WIN-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE2-WIN-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE2-WIN-NEXT: fldcw {{[0-9]+}}(%esp)
-; X86-SSE2-WIN-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-WIN-NEXT: movl 8(%ebp), %eax
; X86-SSE2-WIN-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE2-WIN-NEXT: movl %ebp, %esp
; X86-SSE2-WIN-NEXT: popl %ebp
@@ -417,8 +415,6 @@ define i64 @f_to_s64(float %a) nounwind {
; X86-SSE2-LIN-LABEL: f_to_s64:
; X86-SSE2-LIN: # %bb.0:
; X86-SSE2-LIN-NEXT: subl $20, %esp
-; X86-SSE2-LIN-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE2-LIN-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: flds {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: movzwl {{[0-9]+}}(%esp), %eax
@@ -772,7 +768,7 @@ define i64 @d_to_s64(double %a) nounwind {
; X86-AVX512F-WIN-NEXT: subl $8, %esp
; X86-AVX512F-WIN-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX512F-WIN-NEXT: vmovsd %xmm0, (%esp)
-; X86-AVX512F-WIN-NEXT: fldl (%esp)
+; X86-AVX512F-WIN-NEXT: fldl 8(%ebp)
; X86-AVX512F-WIN-NEXT: fisttpll (%esp)
; X86-AVX512F-WIN-NEXT: movl (%esp), %eax
; X86-AVX512F-WIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -785,7 +781,7 @@ define i64 @d_to_s64(double %a) nounwind {
; X86-AVX512F-LIN-NEXT: subl $12, %esp
; X86-AVX512F-LIN-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX512F-LIN-NEXT: vmovsd %xmm0, (%esp)
-; X86-AVX512F-LIN-NEXT: fldl (%esp)
+; X86-AVX512F-LIN-NEXT: fldl {{[0-9]+}}(%esp)
; X86-AVX512F-LIN-NEXT: fisttpll (%esp)
; X86-AVX512F-LIN-NEXT: movl (%esp), %eax
; X86-AVX512F-LIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -800,7 +796,7 @@ define i64 @d_to_s64(double %a) nounwind {
; X86-SSE3-WIN-NEXT: subl $8, %esp
; X86-SSE3-WIN-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE3-WIN-NEXT: movsd %xmm0, (%esp)
-; X86-SSE3-WIN-NEXT: fldl (%esp)
+; X86-SSE3-WIN-NEXT: fldl 8(%ebp)
; X86-SSE3-WIN-NEXT: fisttpll (%esp)
; X86-SSE3-WIN-NEXT: movl (%esp), %eax
; X86-SSE3-WIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -813,7 +809,7 @@ define i64 @d_to_s64(double %a) nounwind {
; X86-SSE3-LIN-NEXT: subl $12, %esp
; X86-SSE3-LIN-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE3-LIN-NEXT: movsd %xmm0, (%esp)
-; X86-SSE3-LIN-NEXT: fldl (%esp)
+; X86-SSE3-LIN-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE3-LIN-NEXT: fisttpll (%esp)
; X86-SSE3-LIN-NEXT: movl (%esp), %eax
; X86-SSE3-LIN-NEXT: movl {{[0-9]+}}(%esp), %edx
@@ -831,9 +827,7 @@ define i64 @d_to_s64(double %a) nounwind {
; X86-SSE2-WIN-NEXT: movl %esp, %ebp
; X86-SSE2-WIN-NEXT: andl $-8, %esp
; X86-SSE2-WIN-NEXT: subl $16, %esp
-; X86-SSE2-WIN-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-WIN-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
-; X86-SSE2-WIN-NEXT: fldl {{[0-9]+}}(%esp)
+; X86-SSE2-WIN-NEXT: fldl 8(%ebp)
; X86-SSE2-WIN-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE2-WIN-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE2-WIN-NEXT: orl $3072, %eax # imm = 0xC00
@@ -850,8 +844,6 @@ define i64 @d_to_s64(double %a) nounwind {
; X86-SSE2-LIN-LABEL: d_to_s64:
; X86-SSE2-LIN: # %bb.0:
; X86-SSE2-LIN-NEXT: subl $20, %esp
-; X86-SSE2-LIN-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE2-LIN-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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