[llvm] e7dd336 - [M68k] Prevent COPY instruction from killing live condition flags (#168485)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 2 10:47:15 PDT 2026
Author: Dan Salvato
Date: 2026-08-02T12:47:10-05:00
New Revision: e7dd336e0f7884c34108a1e722205a16c3f5307b
URL: https://github.com/llvm/llvm-project/commit/e7dd336e0f7884c34108a1e722205a16c3f5307b
DIFF: https://github.com/llvm/llvm-project/commit/e7dd336e0f7884c34108a1e722205a16c3f5307b.diff
LOG: [M68k] Prevent COPY instruction from killing live condition flags (#168485)
Added:
Modified:
llvm/lib/Target/M68k/M68kInstrData.td
llvm/lib/Target/M68k/M68kInstrInfo.cpp
llvm/lib/Target/M68k/M68kInstrInfo.td
llvm/lib/Target/M68k/M68kSubtarget.h
llvm/test/CodeGen/M68k/Atomics/rmw.ll
llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index fd654be09dc97..b7b2d0ac48519 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -395,7 +395,6 @@ def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 1 0 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Defs = [CCR] in {
class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
: MxInst<(outs CCRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
let Inst = (ascend
@@ -406,7 +405,6 @@ class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
class MxMoveToCCRPseudo<MxOperand MEMOp>
: MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)>;
-} // let Defs = [CCR]
let mayLoad = 1 in
foreach AM = MxMoveSrcAMs in {
@@ -425,7 +423,6 @@ def MOV16cd : MxMoveToCCR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 0 1 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Uses = [CCR] in {
class MxMoveFromCCR_R
: MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>,
Requires<[ AtLeastM68010 ]> {
@@ -445,7 +442,6 @@ class MxMoveFromCCRPseudo<MxOperand MEMOp>
: MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
class MxMoveFromCCR_RPseudo<MxOperand MEMOp>
: MxPseudo<(outs MEMOp:$dst), (ins CCRC:$src)>;
-} // let Uses = [CCR]
let mayStore = 1 in
foreach AM = MxMoveDstAMs in {
@@ -466,7 +462,6 @@ def MOV16dc : MxMoveFromCCR_R;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 1 1 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Defs = [SR] in {
class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
: MxInst<(outs SRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
let Inst = (ascend
@@ -474,7 +469,6 @@ class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
SRC_ENC.Supplement
);
}
-} // let Defs = [SR]
let mayLoad = 1 in
foreach AM = MxMoveSrcAMs in {
@@ -491,20 +485,20 @@ def MOV16sd : MxMoveToSR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 0 0 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Uses = [SR] in {
class MxMoveFromSR_R
- : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []> {
+ : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []>,
+ Requires<[ IsM68000 ]> {
let Inst = (descend 0b0100000011, MxEncAddrMode_d<"dst">.EA);
}
class MxMoveFromSR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
- : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []> {
+ : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []>,
+ Requires<[ IsM68000 ]> {
let Inst = (ascend
(descend 0b0100000011, DST_ENC.EA),
DST_ENC.Supplement
);
}
-} // let Uses = [SR]
let mayStore = 1 in
foreach AM = MxMoveDstAMs in {
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 0c4708eb98daa..c7cdb99a58d3e 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -688,86 +688,142 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const DebugLoc &DL, Register DstReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
- const auto &Subtarget = MBB.getParent()->getSubtarget<M68kSubtarget>();
unsigned Opc = 0;
+ MachineFunction &MF = *MBB.getParent();
+ const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
- // First deal with the normal symmetric copies.
- if (M68k::XR32RegClass.contains(DstReg, SrcReg))
+ // Symmetric register copies
+ if (M68k::XR32RegClass.contains(DstReg, SrcReg)) {
Opc = M68k::MOV32rr;
- else if (M68k::XR16RegClass.contains(DstReg, SrcReg))
+ } else if (M68k::XR16RegClass.contains(DstReg, SrcReg)) {
Opc = M68k::MOV16rr;
- else if (M68k::DR8RegClass.contains(DstReg, SrcReg))
+ } else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) {
Opc = M68k::MOV8dd;
-
- if (Opc) {
- BuildMI(MBB, MI, DL, get(Opc), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
}
- // Now deal with asymmetrically sized copies. The cases that follow are upcast
- // moves.
- //
- // NOTE
- // These moves are not aware of type nature of these values and thus
- // won't do any SExt or ZExt and upper bits will basically contain garbage.
- MachineInstrBuilder MIB(*MBB.getParent(), MI);
- if (M68k::DR8RegClass.contains(SrcReg)) {
- if (M68k::XR16RegClass.contains(DstReg))
- Opc = M68k::MOVXd16d8;
- else if (M68k::XR32RegClass.contains(DstReg))
- Opc = M68k::MOVXd32d8;
+ // Asymmetric register copies
+ // NOTE: There is no implicit sext/zext occurring during these moves, so the
+ // upper bits will be undefined.
+ // 8 -> 16
+ else if (M68k::DR8RegClass.contains(SrcReg) &&
+ M68k::XR16RegClass.contains(DstReg)) {
+ Opc = M68k::MOVXd16d8;
+ // 8 -> 32
+ } else if (M68k::DR8RegClass.contains(SrcReg) &&
+ M68k::XR32RegClass.contains(DstReg)) {
+ Opc = M68k::MOVXd32d8;
+ // 16 -> 32
} else if (M68k::XR16RegClass.contains(SrcReg) &&
- M68k::XR32RegClass.contains(DstReg))
+ M68k::XR32RegClass.contains(DstReg)) {
Opc = M68k::MOVXd32d16;
-
- if (Opc) {
- BuildMI(MBB, MI, DL, get(Opc), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
}
- bool FromCCR = SrcReg == M68k::CCR;
- bool FromSR = SrcReg == M68k::SR;
- bool ToCCR = DstReg == M68k::CCR;
- bool ToSR = DstReg == M68k::SR;
-
- if (FromCCR) {
- Opc = M68k::MOV16dc;
- if (!Subtarget.atLeastM68010()) {
- Opc = M68k::MOV16ds;
- SrcReg = M68k::SR;
- }
- if (!M68k::DR8RegClass.contains(DstReg) &&
- !M68k::DR16RegClass.contains(DstReg) &&
- !M68k::DR32RegClass.contains(DstReg)) {
+ // Copy from CCR
+ // NOTE: M68000 uses MOVE from SR to copy from CCR, all other variants use
+ // MOVE from CCR.
+ else if (SrcReg == M68k::CCR) {
+ if (M68k::DR8RegClass.contains(DstReg) ||
+ M68k::DR16RegClass.contains(DstReg) ||
+ M68k::DR32RegClass.contains(DstReg)) {
+ Opc = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
+ } else {
LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');
llvm_unreachable("Invalid register for MOVE from CCR");
}
- } else if (ToCCR) {
- Opc = M68k::MOV16cd;
- if (M68k::DR8RegClass.contains(SrcReg)) {
- // Promote used register to the next class
- SrcReg = getRegisterInfo().getMatchingSuperReg(
- SrcReg, M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass);
- } else if (!M68k::DR16RegClass.contains(SrcReg) &&
- !M68k::DR32RegClass.contains(SrcReg)) {
+ }
+
+ // Copy to CCR
+ else if (DstReg == M68k::CCR) {
+ if (M68k::DR8RegClass.contains(SrcReg) ||
+ M68k::DR16RegClass.contains(SrcReg) ||
+ M68k::DR32RegClass.contains(SrcReg)) {
+ Opc = M68k::MOV16cd;
+ } else {
LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");
llvm_unreachable("Invalid register for MOVE to CCR");
}
- } else if (FromSR || ToSR) {
- llvm_unreachable("Cannot emit SR copy instruction");
}
- if (Opc) {
+ // SR should never be a valid register for copying
+ else if (SrcReg == M68k::SR || DstReg == M68k::SR)
+ llvm_unreachable("Cannot explicitly copy to/from SR");
+
+ // We should now have our opcode
+ if (!Opc) {
+ LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
+ << RI.getName(DstReg) << '\n');
+ llvm_unreachable("Cannot emit physreg copy instruction");
+ }
+
+ // FIXME
+ // Below is a workaround to prevent a live CCR from being killed by the COPY
+ // instruction. LLVM sometimes inserts a COPY pseudo instruction between
+ // compare and branch during MIR generation (e.g. during PHI node elimination)
+ // without any idea that on M68k, this is extremely likely to implicitly kill
+ // the CCR.
+ // The workaround checks whether CCR is live during this copy, and if so,
+ // backs up CCR and restores it after the copy. It's inefficient and prevents
+ // M68000-targeted builds from running on 010+ (because 000 uses MOVE from SR
+ // and 010+ uses MOVE from CCR).
+ // The fix condition is to prevent COPY from ever being inserted while CCR is
+ // live (which would also stop this workaround from ever triggering).
+
+ unsigned CCRSrcReg = STI.isM68000() ? M68k::SR : M68k::CCR;
+
+ // Get the live registers right before the COPY instruction. If CCR is
+ // live, the MOVE is going to kill it, so we will need to preserve it.
+ LiveRegUnits UsedRegs(RI);
+ UsedRegs.addLiveOuts(MBB);
+ auto InstUpToI = MBB.end();
+ while (InstUpToI != MI) {
+ UsedRegs.stepBackward(*--InstUpToI);
+ }
+
+ if (SrcReg == M68k::CCR) {
+ BuildMI(MBB, MI, DL, get(Opc), DstReg).addReg(CCRSrcReg);
+ return;
+ }
+ if (DstReg == M68k::CCR) {
+ BuildMI(MBB, MI, DL, get(Opc), M68k::CCR)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+ if (UsedRegs.available(M68k::CCR)) {
BuildMI(MBB, MI, DL, get(Opc), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
- LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
- << RI.getName(DstReg) << '\n');
- llvm_unreachable("Cannot emit physreg copy instruction");
+ // CCR is live, so we must restore it after the copy. Prepare push/pop ops.
+ // 68000 must use MOVE from SR, 68010+ must use MOVE from CCR. In either
+ // case, upon moving back, MOVE to CCR will mask out the upper byte anyway.
+
+ // Look for an available data register for the CCR, or push to stack if
+ // there are none
+ BitVector Allocatable =
+ RI.getAllocatableSet(MF, RI.getRegClass(M68k::DR16RegClassID));
+ for (Register Reg : Allocatable.set_bits()) {
+ if (!RI.regsOverlap(DstReg, Reg) && (UsedRegs.available(Reg))) {
+ unsigned CCRPushOp = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
+ unsigned CCRPopOp = M68k::MOV16cd;
+ BuildMI(MBB, MI, DL, get(CCRPushOp), Reg).addReg(CCRSrcReg);
+ BuildMI(MBB, MI, DL, get(Opc), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(CCRPopOp), M68k::CCR).addReg(Reg);
+ return;
+ }
+ }
+
+ unsigned CCRPushOp = STI.isM68000() ? M68k::MOV16es : M68k::MOV16ec;
+ unsigned CCRPopOp = M68k::MOV16co;
+
+ BuildMI(MBB, MI, DL, get(CCRPushOp))
+ .addReg(RI.getStackRegister())
+ .addReg(CCRSrcReg);
+ BuildMI(MBB, MI, DL, get(Opc), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(CCRPopOp), M68k::CCR).addReg(RI.getStackRegister());
+ return;
}
namespace {
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 422b737721e2b..7804a24f30948 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -490,6 +490,9 @@ def IsPIC : Predicate<"TM.isPositionIndependent()">;
def IsNotPIC : Predicate<"!TM.isPositionIndependent()">;
// ISA versions
+def IsM68000 : Predicate<"Subtarget->isM68000()">,
+ AssemblerPredicate<(all_of FeatureISA00)>;
+
foreach i = [0,1,2,4,6] in
def AtLeastM680 # i # "0" : Predicate<"Subtarget->atLeastM680"#i#"0()">,
AssemblerPredicate<(all_of
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index 4f9685814d9a9..0a46f3b8e371f 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -82,6 +82,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
/// of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
+ bool isM68000() const { return SubtargetKind == M00; }
bool atLeastM68000() const { return SubtargetKind >= M00; }
bool atLeastM68010() const { return SubtargetKind >= M10; }
bool atLeastM68020() const { return SubtargetKind >= M20; }
diff --git a/llvm/test/CodeGen/M68k/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
index 8549524836a78..8de7f952977af 100644
--- a/llvm/test/CodeGen/M68k/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
@@ -1,24 +1,38 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC-000
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC-010
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68020 -verify-machineinstrs | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 -verify-machineinstrs | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 -verify-machineinstrs | FileCheck %s --check-prefix=ATOMIC
define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_add_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_add_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_add_i8:
; ATOMIC: .cfi_startproc
@@ -40,7 +54,9 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB0_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -51,19 +67,33 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16:
; ATOMIC: .cfi_startproc
@@ -85,7 +115,9 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB1_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -96,18 +128,31 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_and_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_and_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_and_i32:
; ATOMIC: .cfi_startproc
@@ -129,7 +174,9 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB2_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -140,21 +187,37 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xor_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #20, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -24
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (32,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_fetch_xor_8
-; NO-ATOMIC-NEXT: adda.l #20, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #20, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-000-NEXT: adda.l #20, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #20, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-010-NEXT: adda.l #20, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xor_i64:
; ATOMIC: .cfi_startproc
@@ -176,19 +239,33 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_or_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_or_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_or_i8:
; ATOMIC: .cfi_startproc
@@ -210,7 +287,9 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB4_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -221,23 +300,41 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
}
define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atmoicrmw_nand_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d2
-; NO-ATOMIC-NEXT: move.l %d2, %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_nand_2
-; NO-ATOMIC-NEXT: move.w %d2, %d0
-; NO-ATOMIC-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-000-NEXT: move.l %d2, %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-000-NEXT: move.w %d2, %d0
+; NO-ATOMIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-010-NEXT: move.l %d2, %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-010-NEXT: move.w %d2, %d0
+; NO-ATOMIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atmoicrmw_nand_i16:
; ATOMIC: .cfi_startproc
@@ -260,7 +357,9 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d1, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB5_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -271,18 +370,31 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_min_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_min_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_min_i32:
; ATOMIC: .cfi_startproc
@@ -303,13 +415,17 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB6_4
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d2, %d0
; ATOMIC-NEXT: sub.l %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.l %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: ble .LBB6_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB6_1 Depth=1
@@ -324,54 +440,107 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_max_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #52, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-NEXT: move.l (64,%sp), %d3
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (60,%sp), %d4
-; NO-ATOMIC-NEXT: move.l (56,%sp), %d5
-; NO-ATOMIC-NEXT: jsr __atomic_load_8
-; NO-ATOMIC-NEXT: lea (24,%sp), %a2
-; NO-ATOMIC-NEXT: bra .LBB7_1
-; NO-ATOMIC-NEXT: .LBB7_3: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d1, (12,%sp)
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (20,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (16,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8
-; NO-ATOMIC-NEXT: move.b %d0, %d2
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d1
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_4
-; NO-ATOMIC-NEXT: .LBB7_1: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
-; NO-ATOMIC-NEXT: move.l %d0, (24,%sp)
-; NO-ATOMIC-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l %a2, (4,%sp)
-; NO-ATOMIC-NEXT: move.l %d4, %d2
-; NO-ATOMIC-NEXT: sub.l %d1, %d2
-; NO-ATOMIC-NEXT: move.l %d5, %d2
-; NO-ATOMIC-NEXT: subx.l %d0, %d2
-; NO-ATOMIC-NEXT: slt %d2
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_3
-; NO-ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d4, %d1
-; NO-ATOMIC-NEXT: move.l %d5, %d0
-; NO-ATOMIC-NEXT: bra .LBB7_3
-; NO-ATOMIC-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #52, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #52, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-000-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-000-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-000-NEXT: lea (24,%sp), %a2
+; NO-ATOMIC-000-NEXT: bra .LBB7_1
+; NO-ATOMIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-000-NEXT: move.b %d0, %d2
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_4
+; NO-ATOMIC-000-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-000-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-000-NEXT: move.w %sr, -(%sp)
+; NO-ATOMIC-000-NEXT: move.l %d5, %d2
+; NO-ATOMIC-000-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-000-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-000-NEXT: slt %d2
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_3
+; NO-ATOMIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d4, %d1
+; NO-ATOMIC-000-NEXT: move.l %d5, %d0
+; NO-ATOMIC-000-NEXT: bra .LBB7_3
+; NO-ATOMIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #52, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #52, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-010-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-010-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-010-NEXT: lea (24,%sp), %a2
+; NO-ATOMIC-010-NEXT: bra .LBB7_1
+; NO-ATOMIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-010-NEXT: move.b %d0, %d2
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_4
+; NO-ATOMIC-010-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-010-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-010-NEXT: move.w %ccr, -(%sp)
+; NO-ATOMIC-010-NEXT: move.l %d5, %d2
+; NO-ATOMIC-010-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-010-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-010-NEXT: slt %d2
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_3
+; NO-ATOMIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d4, %d1
+; NO-ATOMIC-010-NEXT: move.l %d5, %d0
+; NO-ATOMIC-010-NEXT: bra .LBB7_3
+; NO-ATOMIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #52, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_max_i64:
; ATOMIC: .cfi_startproc
@@ -407,7 +576,9 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %a2, (4,%sp)
; ATOMIC-NEXT: move.l %d4, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
+; ATOMIC-NEXT: move.w %ccr, -(%sp)
; ATOMIC-NEXT: move.l %d5, %d2
+; ATOMIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-NEXT: subx.l %d0, %d2
; ATOMIC-NEXT: slt %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
@@ -426,19 +597,33 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_i8_umin:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umin_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_i8_umin:
; ATOMIC: .cfi_startproc
@@ -459,13 +644,17 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB8_4
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d2, %d0
; ATOMIC-NEXT: sub.b %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.b %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bls .LBB8_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB8_1 Depth=1
@@ -480,19 +669,33 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_umax_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umax_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_umax_i16:
; ATOMIC: .cfi_startproc
@@ -513,13 +716,17 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB9_4
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d2, %d0
; ATOMIC-NEXT: sub.w %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.w %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bhi .LBB9_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB9_1 Depth=1
@@ -534,19 +741,33 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
}
define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i16:
; ATOMIC: .cfi_startproc
@@ -566,7 +787,9 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB10_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -578,18 +801,31 @@ entry:
}
define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i32:
; ATOMIC: .cfi_startproc
@@ -609,7 +845,9 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB11_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -621,19 +859,33 @@ entry:
}
define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i8_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i8_arid:
; ATOMIC: .cfi_startproc
@@ -655,7 +907,9 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.b %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -669,19 +923,33 @@ start:
}
define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16_arid:
; ATOMIC: .cfi_startproc
@@ -703,7 +971,9 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.w %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -717,19 +987,33 @@ start:
}
define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i32_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i32_arid:
; ATOMIC: .cfi_startproc
@@ -751,7 +1035,9 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.l %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
index 9009d5a53e2a6..97c30b841a51e 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC-000
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC-010
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC-000
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC-010
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68020 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=ATOMIC
@@ -11,33 +11,61 @@
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=ATOMIC-PIC
define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_add_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_add_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_add_i8:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_add_i8:
; ATOMIC: .cfi_startproc
@@ -59,7 +87,9 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB0_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -86,7 +116,9 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.b %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB0_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -97,33 +129,61 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16:
; ATOMIC: .cfi_startproc
@@ -145,7 +205,9 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB1_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -172,7 +234,9 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB1_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -183,31 +247,57 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_and_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_and_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_and_i32:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_and_i32:
; ATOMIC: .cfi_startproc
@@ -229,7 +319,9 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB2_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -256,7 +348,9 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.l %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB2_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -267,37 +361,69 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xor_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #20, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -24
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (32,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_fetch_xor_8
-; NO-ATOMIC-NEXT: adda.l #20, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_xor_i64:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #20, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -24
-; NO-ATOMIC-PIC-NEXT: move.l (28,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (32,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #20, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #20, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-000-NEXT: adda.l #20, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #20, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-010-NEXT: adda.l #20, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #20, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-PIC-000-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #20, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #20, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-PIC-010-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #20, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xor_i64:
; ATOMIC: .cfi_startproc
@@ -335,33 +461,61 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_or_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_or_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_or_i8:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_or_i8:
; ATOMIC: .cfi_startproc
@@ -383,7 +537,9 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB4_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -410,7 +566,9 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.b %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB4_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -421,41 +579,77 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
}
define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atmoicrmw_nand_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d2
-; NO-ATOMIC-NEXT: move.l %d2, %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_nand_2
-; NO-ATOMIC-NEXT: move.w %d2, %d0
-; NO-ATOMIC-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atmoicrmw_nand_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d2
-; NO-ATOMIC-PIC-NEXT: move.l %d2, %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: move.w %d2, %d0
-; NO-ATOMIC-PIC-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-000-NEXT: move.l %d2, %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-000-NEXT: move.w %d2, %d0
+; NO-ATOMIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-010-NEXT: move.l %d2, %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-010-NEXT: move.w %d2, %d0
+; NO-ATOMIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-PIC-000-NEXT: move.l %d2, %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: move.w %d2, %d0
+; NO-ATOMIC-PIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-PIC-010-NEXT: move.l %d2, %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: move.w %d2, %d0
+; NO-ATOMIC-PIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atmoicrmw_nand_i16:
; ATOMIC: .cfi_startproc
@@ -478,7 +672,9 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d1, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB5_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -506,7 +702,9 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d1, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB5_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -517,31 +715,57 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_min_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_min_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_min_i32:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_min_i32:
; ATOMIC: .cfi_startproc
@@ -562,13 +786,17 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB6_4
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d2, %d0
; ATOMIC-NEXT: sub.l %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.l %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: ble .LBB6_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB6_1 Depth=1
@@ -598,13 +826,17 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.l %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: bne .LBB6_4
; ATOMIC-PIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.l %d2, %d0
; ATOMIC-PIC-NEXT: sub.l %d1, %d0
+; ATOMIC-PIC-NEXT: move.w %ccr, %d0
; ATOMIC-PIC-NEXT: move.l %d2, %d3
+; ATOMIC-PIC-NEXT: move.w %d0, %ccr
; ATOMIC-PIC-NEXT: ble .LBB6_3
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; in Loop: Header=BB6_1 Depth=1
@@ -619,103 +851,209 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_max_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #52, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-NEXT: move.l (64,%sp), %d3
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (60,%sp), %d4
-; NO-ATOMIC-NEXT: move.l (56,%sp), %d5
-; NO-ATOMIC-NEXT: jsr __atomic_load_8
-; NO-ATOMIC-NEXT: lea (24,%sp), %a2
-; NO-ATOMIC-NEXT: bra .LBB7_1
-; NO-ATOMIC-NEXT: .LBB7_3: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d1, (12,%sp)
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (20,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (16,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8
-; NO-ATOMIC-NEXT: move.b %d0, %d2
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d1
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_4
-; NO-ATOMIC-NEXT: .LBB7_1: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
-; NO-ATOMIC-NEXT: move.l %d0, (24,%sp)
-; NO-ATOMIC-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l %a2, (4,%sp)
-; NO-ATOMIC-NEXT: move.l %d4, %d2
-; NO-ATOMIC-NEXT: sub.l %d1, %d2
-; NO-ATOMIC-NEXT: move.l %d5, %d2
-; NO-ATOMIC-NEXT: subx.l %d0, %d2
-; NO-ATOMIC-NEXT: slt %d2
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_3
-; NO-ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d4, %d1
-; NO-ATOMIC-NEXT: move.l %d5, %d0
-; NO-ATOMIC-NEXT: bra .LBB7_3
-; NO-ATOMIC-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #52, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_max_i64:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #52, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-PIC-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-PIC-NEXT: move.l (64,%sp), %d3
-; NO-ATOMIC-PIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (60,%sp), %d4
-; NO-ATOMIC-PIC-NEXT: move.l (56,%sp), %d5
-; NO-ATOMIC-PIC-NEXT: jsr (__atomic_load_8 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: lea (24,%sp), %a2
-; NO-ATOMIC-PIC-NEXT: bra .LBB7_1
-; NO-ATOMIC-PIC-NEXT: .LBB7_3: ; %atomicrmw.start
-; NO-ATOMIC-PIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-PIC-NEXT: move.l %d1, (12,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #5, (20,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #5, (16,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__atomic_compare_exchange_8 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: move.b %d0, %d2
-; NO-ATOMIC-PIC-NEXT: move.l (28,%sp), %d1
-; NO-ATOMIC-PIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-PIC-NEXT: bne .LBB7_4
-; NO-ATOMIC-PIC-NEXT: .LBB7_1: ; %atomicrmw.start
-; NO-ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (24,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %a2, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d4, %d2
-; NO-ATOMIC-PIC-NEXT: sub.l %d1, %d2
-; NO-ATOMIC-PIC-NEXT: move.l %d5, %d2
-; NO-ATOMIC-PIC-NEXT: subx.l %d0, %d2
-; NO-ATOMIC-PIC-NEXT: slt %d2
-; NO-ATOMIC-PIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-PIC-NEXT: bne .LBB7_3
-; NO-ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
-; NO-ATOMIC-PIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-PIC-NEXT: move.l %d4, %d1
-; NO-ATOMIC-PIC-NEXT: move.l %d5, %d0
-; NO-ATOMIC-PIC-NEXT: bra .LBB7_3
-; NO-ATOMIC-PIC-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-PIC-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
-; NO-ATOMIC-PIC-NEXT: adda.l #52, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #52, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-000-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-000-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-000-NEXT: lea (24,%sp), %a2
+; NO-ATOMIC-000-NEXT: bra .LBB7_1
+; NO-ATOMIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-000-NEXT: move.b %d0, %d2
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_4
+; NO-ATOMIC-000-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-000-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-000-NEXT: move.w %sr, -(%sp)
+; NO-ATOMIC-000-NEXT: move.l %d5, %d2
+; NO-ATOMIC-000-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-000-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-000-NEXT: slt %d2
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_3
+; NO-ATOMIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d4, %d1
+; NO-ATOMIC-000-NEXT: move.l %d5, %d0
+; NO-ATOMIC-000-NEXT: bra .LBB7_3
+; NO-ATOMIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #52, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #52, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-010-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-010-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-010-NEXT: lea (24,%sp), %a2
+; NO-ATOMIC-010-NEXT: bra .LBB7_1
+; NO-ATOMIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-010-NEXT: move.b %d0, %d2
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_4
+; NO-ATOMIC-010-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-010-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-010-NEXT: move.w %ccr, -(%sp)
+; NO-ATOMIC-010-NEXT: move.l %d5, %d2
+; NO-ATOMIC-010-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-010-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-010-NEXT: slt %d2
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_3
+; NO-ATOMIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d4, %d1
+; NO-ATOMIC-010-NEXT: move.l %d5, %d0
+; NO-ATOMIC-010-NEXT: bra .LBB7_3
+; NO-ATOMIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #52, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #52, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-PIC-000-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-PIC-000-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-PIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-PIC-000-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_load_8 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: lea (24,%sp), %a2
+; NO-ATOMIC-PIC-000-NEXT: bra .LBB7_1
+; NO-ATOMIC-PIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-PIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_compare_exchange_8 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: move.b %d0, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-PIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-000-NEXT: bne .LBB7_4
+; NO-ATOMIC-PIC-000-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-PIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-PIC-000-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.w %sr, -(%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d5, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-PIC-000-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-PIC-000-NEXT: slt %d2
+; NO-ATOMIC-PIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-000-NEXT: bne .LBB7_3
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-PIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d5, %d0
+; NO-ATOMIC-PIC-000-NEXT: bra .LBB7_3
+; NO-ATOMIC-PIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-PIC-000-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
+; NO-ATOMIC-PIC-000-NEXT: adda.l #52, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #52, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-PIC-010-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-PIC-010-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-PIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-PIC-010-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_load_8 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: lea (24,%sp), %a2
+; NO-ATOMIC-PIC-010-NEXT: bra .LBB7_1
+; NO-ATOMIC-PIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-PIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_compare_exchange_8 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: move.b %d0, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-PIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-010-NEXT: bne .LBB7_4
+; NO-ATOMIC-PIC-010-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-PIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-PIC-010-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.w %ccr, -(%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d5, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-PIC-010-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-PIC-010-NEXT: slt %d2
+; NO-ATOMIC-PIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-010-NEXT: bne .LBB7_3
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-PIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d5, %d0
+; NO-ATOMIC-PIC-010-NEXT: bra .LBB7_3
+; NO-ATOMIC-PIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-PIC-010-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
+; NO-ATOMIC-PIC-010-NEXT: adda.l #52, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_max_i64:
; ATOMIC: .cfi_startproc
@@ -751,7 +1089,9 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-NEXT: move.l %a2, (4,%sp)
; ATOMIC-NEXT: move.l %d4, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
+; ATOMIC-NEXT: move.w %ccr, -(%sp)
; ATOMIC-NEXT: move.l %d5, %d2
+; ATOMIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-NEXT: subx.l %d0, %d2
; ATOMIC-NEXT: slt %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
@@ -800,7 +1140,9 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: move.l %a2, (4,%sp)
; ATOMIC-PIC-NEXT: move.l %d4, %d2
; ATOMIC-PIC-NEXT: sub.l %d1, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, -(%sp)
; ATOMIC-PIC-NEXT: move.l %d5, %d2
+; ATOMIC-PIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-PIC-NEXT: subx.l %d0, %d2
; ATOMIC-PIC-NEXT: slt %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
@@ -819,33 +1161,61 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_i8_umin:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umin_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_i8_umin:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_i8_umin:
; ATOMIC: .cfi_startproc
@@ -866,13 +1236,17 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB8_4
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d2, %d0
; ATOMIC-NEXT: sub.b %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.b %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bls .LBB8_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB8_1 Depth=1
@@ -902,13 +1276,17 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.b %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: bne .LBB8_4
; ATOMIC-PIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.b %d2, %d0
; ATOMIC-PIC-NEXT: sub.b %d1, %d0
+; ATOMIC-PIC-NEXT: move.w %ccr, %d0
; ATOMIC-PIC-NEXT: move.b %d2, %d3
+; ATOMIC-PIC-NEXT: move.w %d0, %ccr
; ATOMIC-PIC-NEXT: bls .LBB8_3
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; in Loop: Header=BB8_1 Depth=1
@@ -923,33 +1301,61 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_umax_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umax_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_umax_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_umax_i16:
; ATOMIC: .cfi_startproc
@@ -970,13 +1376,17 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB9_4
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d2, %d0
; ATOMIC-NEXT: sub.w %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.w %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bhi .LBB9_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB9_1 Depth=1
@@ -1006,13 +1416,17 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: bne .LBB9_4
; ATOMIC-PIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.w %d2, %d0
; ATOMIC-PIC-NEXT: sub.w %d1, %d0
+; ATOMIC-PIC-NEXT: move.w %ccr, %d0
; ATOMIC-PIC-NEXT: move.w %d2, %d3
+; ATOMIC-PIC-NEXT: move.w %d0, %ccr
; ATOMIC-PIC-NEXT: bhi .LBB9_3
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; in Loop: Header=BB9_1 Depth=1
@@ -1027,33 +1441,61 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
}
define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_xchg_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i16:
; ATOMIC: .cfi_startproc
@@ -1073,7 +1515,9 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB10_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1098,7 +1542,9 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB10_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1110,31 +1556,57 @@ entry:
}
define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_xchg_i32:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i32:
; ATOMIC: .cfi_startproc
@@ -1154,7 +1626,9 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB11_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1179,7 +1653,9 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.l %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB11_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1191,33 +1667,61 @@ entry:
}
define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i8_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i8_arid:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-PIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-PIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i8_arid:
; ATOMIC: .cfi_startproc
@@ -1239,7 +1743,9 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.b %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1266,7 +1772,9 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: seq %d1
; ATOMIC-PIC-NEXT: and.b #1, %d1
; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-PIC-NEXT: move.w %ccr, %d2
; ATOMIC-PIC-NEXT: move.b %d0, %d1
+; ATOMIC-PIC-NEXT: move.w %d2, %ccr
; ATOMIC-PIC-NEXT: beq .LBB12_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1280,33 +1788,61 @@ start:
}
define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i16_arid:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-PIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-PIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16_arid:
; ATOMIC: .cfi_startproc
@@ -1328,7 +1864,9 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.w %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1355,7 +1893,9 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: seq %d1
; ATOMIC-PIC-NEXT: and.b #1, %d1
; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-PIC-NEXT: move.w %ccr, %d2
; ATOMIC-PIC-NEXT: move.w %d0, %d1
+; ATOMIC-PIC-NEXT: move.w %d2, %ccr
; ATOMIC-PIC-NEXT: beq .LBB13_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1369,33 +1909,61 @@ start:
}
define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i32_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i32_arid:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-PIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-PIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i32_arid:
; ATOMIC: .cfi_startproc
@@ -1417,7 +1985,9 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.l %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1444,7 +2014,9 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: seq %d1
; ATOMIC-PIC-NEXT: and.b #1, %d1
; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-PIC-NEXT: move.w %ccr, %d2
; ATOMIC-PIC-NEXT: move.l %d0, %d1
+; ATOMIC-PIC-NEXT: move.w %d2, %ccr
; ATOMIC-PIC-NEXT: beq .LBB14_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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