[llvm] [X86] Lower vector integer division and remainder through float division (PR #205263)

[Phoebe Wang via llvm-commits]

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@@ -50564,6 +50572,200 @@ static SDValue combineMulToPMADD52(SDNode *N, const SDLoc &DL,
   return SDValue();
 }
 
+// x86 has no vector integer divide instructions. Lower vector
+// UDIV/SDIV/UREM/SREM through float division instead of scalarizing into N
+// scalar hardware divides.
+static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
+                                TargetLowering::DAGCombinerInfo &DCI,
+                                const X86Subtarget &Subtarget) {
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  // Run before the legalizer expands the division.
+  if (!VT.isVector() || !Subtarget.hasSSE2() || !DCI.isBeforeLegalizeOps())
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phoebewang wrote:

Is `DCI.isBeforeLegalizeOps` redundant given we check `VT.isVector`?

https://github.com/llvm/llvm-project/pull/205263