[llvm] [WebAssembly] Add v8f16 select instruction patterns (PR #213280)

[Anutosh Bhat via llvm-commits]

https://github.com/anutosh491 updated https://github.com/llvm/llvm-project/pull/213280

>From 2a7203b3aa933d7e3736399139f668fe2bf9a70a Mon Sep 17 00:00:00 2001
From: anutosh491 <andersonbhat491 at gmail.com>
Date: Fri, 31 Jul 2026 19:43:17 +0530
Subject: [PATCH] [WebAssembly] Add v8f16 select instruction patterns

---
 .../WebAssembly/WebAssemblyInstrSIMD.td       |  4 ++--
 .../CodeGen/WebAssembly/f16-intrinsics.ll     | 22 +++++++++++++++++++
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index a93fb1ccc3dd9..a77083cb1e1ff 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -938,7 +938,7 @@ def : Pat<(vec.vt (vselect
           (ANDNOT $c, $x)>;
 
 // Also implement vselect in terms of bitselect
-foreach vec = StdVecs in
+foreach vec = AllVecs in
 def : Pat<(vec.vt (vselect
             (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
           (BITSELECT $v1, $v2, $c)>;
@@ -948,7 +948,7 @@ defm SELECT_V128 :
   I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), (outs), (ins), [],
     "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>;
 
-foreach vec = StdVecs in {
+foreach vec = AllVecs in {
 def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
           (SELECT_V128 $lhs, $rhs, $cond)>;
 
diff --git a/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
index 264f3601486b8..32531716f1a56 100644
--- a/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
@@ -89,6 +89,28 @@ define <8 x half> @insert_lane_v8f16(<8 x half> %v, half %x) {
   ret <8 x half> %r
 }
 
+; CHECK-LABEL: select_v8f16:
+; CHECK:       v128.select $push0=, $1, $2, $0
+; CHECK-NEXT:  return $pop0
+define <8 x half> @select_v8f16(i1 zeroext %cond, <8 x half> %a,
+                                 <8 x half> %b) {
+  %result = select i1 %cond, <8 x half> %a, <8 x half> %b
+  ret <8 x half> %result
+}
+
+; CHECK-LABEL: vselect_v8f16:
+; CHECK:       i32.const $push0=, 15
+; CHECK-NEXT:  i16x8.shl $push1=, $0, $pop0
+; CHECK-NEXT:  i32.const $push4=, 15
+; CHECK-NEXT:  i16x8.shr_s $push2=, $pop1, $pop4
+; CHECK-NEXT:  v128.bitselect $push3=, $1, $2, $pop2
+; CHECK-NEXT:  return $pop3
+define <8 x half> @vselect_v8f16(<8 x i1> %cond, <8 x half> %a,
+                                  <8 x half> %b) {
+  %result = select <8 x i1> %cond, <8 x half> %a, <8 x half> %b
+  ret <8 x half> %result
+}
+
 ; CHECK-LABEL: add_v8f16:
 ; CHECK:       f16x8.add $push0=, $0, $1
 ; CHECK-NEXT:  return $pop0