[llvm] [X86] Eliminate dead SSE loads and stores after rewriting stack spills (PR #213498)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 1 18:28:37 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: AZero13 (AZero13)
<details>
<summary>Changes</summary>
These spills are redundant and can be removed.
---
Patch is 24.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213498.diff
5 Files Affected:
- (modified) llvm/lib/Target/X86/X86FixupInstTuning.cpp (+82)
- (modified) llvm/test/CodeGen/X86/fp-intrinsics.ll (+8-32)
- (modified) llvm/test/CodeGen/X86/fp80-strict-scalar.ll (+3-9)
- (modified) llvm/test/CodeGen/X86/scalar-int-to-fp.ll (+21-63)
- (added) llvm/test/CodeGen/X86/x87-inout-bounce.ll (+115)
``````````diff
diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index 621fd35a03cd5..e9582e8e46f89 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -29,7 +29,9 @@
#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/IR/Analysis.h"
using namespace llvm;
@@ -47,6 +49,8 @@ class X86FixupInstTuningImpl {
bool processInstruction(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I);
+ bool processSpills(MachineBasicBlock &MBB, MachineFunction &MF);
+
const X86InstrInfo *TII = nullptr;
const X86Subtarget *ST = nullptr;
const MCSchedModel *SM = nullptr;
@@ -88,6 +92,83 @@ static std::optional<bool> CmpOptionals(T NewVal, T CurVal) {
return std::nullopt;
}
+bool X86FixupInstTuningImpl::processSpills(MachineBasicBlock &MBB, MachineFunction &MF) {
+ bool Changed = false;
+ struct StackAccess {
+ SmallVector<MachineOperand, X86::AddrNumOperands> MOs;
+ MachineInstr *StoreMI = nullptr;
+ MachineInstr *LoadMI = nullptr;
+ };
+ DenseMap<int, StackAccess> SpillMap;
+ DenseMap<unsigned, StackAccess> RegToFI;
+ SmallPtrSet<MachineInstr *, 4> StoresToErase;
+
+ for (MachineInstr &MI : MBB) {
+ if (MI.isCall()) {
+ RegToFI.clear();
+ continue;
+ }
+
+ int MemIdx = X86::getFirstAddrOperandIdx(MI);
+ if (MemIdx >= 0) {
+ for (MachineMemOperand *MMO : MI.memoperands()) {
+ if (MMO->isLoad()) {
+ if (const auto *FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(MMO->getPseudoValue())) {
+ int FI = FSPV->getFrameIndex();
+ if (SpillMap.count(FI)) {
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ MI.getOperand(MemIdx + i) = SpillMap[FI].MOs[i];
+ if (SpillMap[FI].StoreMI)
+ StoresToErase.insert(SpillMap[FI].StoreMI);
+ if (SpillMap[FI].LoadMI)
+ StoresToErase.insert(SpillMap[FI].LoadMI);
+ Changed = true;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ int LoadedFI = -1;
+ unsigned LoadedReg = TII->isLoadFromStackSlotPostFE(MI, LoadedFI);
+
+ int StoredFI = -1;
+ unsigned StoredReg = TII->isStoreToStackSlotPostFE(MI, StoredFI);
+
+ if (StoredReg) {
+ if (RegToFI.count(StoredReg)) {
+ StackAccess SA = RegToFI[StoredReg];
+ SA.StoreMI = &MI;
+ SpillMap[StoredFI] = SA;
+ } else {
+ SpillMap.erase(StoredFI);
+ }
+ }
+
+ for (auto &Def : MI.defs()) {
+ if (Def.isReg()) RegToFI.erase(Def.getReg());
+ }
+
+ if (LoadedReg) {
+ int MemIdx = X86::getFirstAddrOperandIdx(MI);
+ if (MemIdx >= 0) {
+ StackAccess SA;
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ SA.MOs.push_back(MI.getOperand(MemIdx + i));
+ SA.LoadMI = &MI;
+ RegToFI[LoadedReg] = SA;
+ }
+ }
+ }
+
+ for (MachineInstr *MI : StoresToErase) {
+ MI->eraseFromParent();
+ Changed = true;
+ }
+ return Changed;
+}
+
bool X86FixupInstTuningImpl::processInstruction(
MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
@@ -712,6 +793,7 @@ bool X86FixupInstTuningImpl::runOnMachineFunction(MachineFunction &MF) {
SM = &ST->getSchedModel();
for (MachineBasicBlock &MBB : MF) {
+ Changed |= processSpills(MBB, MF);
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
if (processInstruction(MF, MBB, I)) {
++NumInstChanges;
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
index 5d69a217fb402..abfa265092848 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -1080,8 +1080,6 @@ define i64 @f20s64(double %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
-; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
@@ -2076,9 +2074,7 @@ define double @sifdi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2205,9 +2201,7 @@ define float @siffi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2407,10 +2401,8 @@ define double @uifdi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2420,10 +2412,8 @@ define double @uifdi(i32 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
-; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: fildll (%esp)
+; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
@@ -2459,12 +2449,10 @@ define double @uifdl(i64 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -2484,10 +2472,7 @@ define double @uifdl(i64 %x) #0 {
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: wait
-; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-SSE-NEXT: movsd %xmm0, (%esp)
-; X86-SSE-NEXT: fldl (%esp)
+; X86-SSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $28, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
@@ -2629,10 +2614,8 @@ define float @uiffi(i32 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: wait
; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4
@@ -2642,8 +2625,6 @@ define float @uiffi(i32 %x) #0 {
; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24
-; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
@@ -2681,10 +2662,8 @@ define float @uiffl(i64 %x) #0 {
; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
@@ -2706,10 +2685,7 @@ define float @uiffl(i64 %x) #0 {
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
-; X86-SSE-NEXT: wait
-; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-SSE-NEXT: movss %xmm0, (%esp)
-; X86-SSE-NEXT: flds (%esp)
+; X86-SSE-NEXT: flds {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4
diff --git a/llvm/test/CodeGen/X86/fp80-strict-scalar.ll b/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
index b9b1ae60d479e..6276c36677d59 100644
--- a/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
+++ b/llvm/test/CodeGen/X86/fp80-strict-scalar.ll
@@ -737,9 +737,7 @@ define x86_fp80 @sint32_to_fp80(i32 %x) #0 {
; X86: # %bb.0:
; X86-NEXT: pushl %eax
; X86-NEXT: .cfi_def_cfa_offset 8
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl %eax, (%esp)
-; X86-NEXT: fildl (%esp)
+; X86-NEXT: fildl {{[0-9]+}}(%esp)
; X86-NEXT: wait
; X86-NEXT: popl %eax
; X86-NEXT: .cfi_def_cfa_offset 4
@@ -866,10 +864,8 @@ define x86_fp80 @uint32_to_fp80(i32 %x) #0 {
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X86-NEXT: fildll (%esp)
+; X86-NEXT: fildll 8(%ebp)
; X86-NEXT: wait
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
@@ -899,12 +895,10 @@ define x86_fp80 @uint64_to_fp80(i64 %x) #0 {
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp
-; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: shrl $31, %ecx
-; X86-NEXT: fildll (%esp)
+; X86-NEXT: fildll 8(%ebp)
; X86-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X86-NEXT: wait
; X86-NEXT: movl %ebp, %esp
diff --git a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
index 43c1a84f7cd6c..067bdd881e7f5 100644
--- a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
+++ b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll
@@ -53,10 +53,8 @@ define float @u32_to_f(i32 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
-; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE1_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
@@ -69,10 +67,8 @@ define float @u32_to_f(i32 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $8, %esp
-; X87-NEXT: movl 8(%ebp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp
; X87-NEXT: retl
@@ -112,9 +108,7 @@ define float @s32_to_f(i32 %a) nounwind {
; X87-LABEL: s32_to_f:
; X87: # %bb.0:
; X87-NEXT: pushl %eax
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: popl %eax
; X87-NEXT: retl
%r = sitofp i32 %a to float
@@ -167,10 +161,8 @@ define double @u32_to_d(i32 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $8, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
-; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fildll (%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl
@@ -181,10 +173,8 @@ define double @u32_to_d(i32 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $8, %esp
-; X87-NEXT: movl 8(%ebp), %eax
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: movl $0, {{[0-9]+}}(%esp)
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp
; X87-NEXT: retl
@@ -232,18 +222,14 @@ define double @s32_to_d(i32 %a) nounwind {
; SSE1_32-LABEL: s32_to_d:
; SSE1_32: # %bb.0:
; SSE1_32-NEXT: pushl %eax
-; SSE1_32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE1_32-NEXT: movl %eax, (%esp)
-; SSE1_32-NEXT: fildl (%esp)
+; SSE1_32-NEXT: fildl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: popl %eax
; SSE1_32-NEXT: retl
;
; X87-LABEL: s32_to_d:
; X87: # %bb.0:
; X87-NEXT: pushl %eax
-; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X87-NEXT: movl %eax, (%esp)
-; X87-NEXT: fildl (%esp)
+; X87-NEXT: fildl {{[0-9]+}}(%esp)
; X87-NEXT: popl %eax
; X87-NEXT: retl
%r = sitofp i32 %a to double
@@ -257,10 +243,8 @@ define x86_fp80 @u32_to_x(i32 %a) nounwind {
; CHECK32-NEXT: movl %esp, %ebp
; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp
-; CHECK32-NEXT: movl 8(%ebp), %eax
-; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: movl $0, {{[0-9]+}}(%esp)
-; CHECK32-NEXT: fildll (%esp)
+; CHECK32-NEXT: fildll 8(%ebp)
; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl
@@ -279,9 +263,7 @@ define x86_fp80 @s32_to_x(i32 %a) nounwind {
; CHECK32-LABEL: s32_to_x:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %eax
-; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK32-NEXT: movl %eax, (%esp)
-; CHECK32-NEXT: fildl (%esp)
+; CHECK32-NEXT: fildl {{[0-9]+}}(%esp)
; CHECK32-NEXT: popl %eax
; CHECK32-NEXT: retl
;
@@ -314,10 +296,8 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512DQ_32-LABEL: u64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
-; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtuqq2ps %zmm0, %ymm0
-; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
-; AVX512DQ_32-NEXT: flds (%esp)
+; AVX512DQ_32-NEXT: flds {{[0-9]+}}(%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
@@ -335,9 +315,7 @@ define float @u64_to_f(i64 %a) nounwind {
; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX512F_32-NEXT: fstps {{[0-9]+}}(%esp)
-; AVX512F_32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX512F_32-NEXT: vmovss %xmm0, (%esp)
-; AVX512F_32-NEXT: flds (%esp)
+; AVX512F_32-NEXT: flds {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: movl %ebp, %esp
; AVX512F_32-NEXT: popl %ebp
; AVX512F_32-NEXT: retl
@@ -355,9 +333,7 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE2_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE2_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE2_32-NEXT: fstps {{[0-9]+}}(%esp)
-; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2_32-NEXT: movss %xmm0, (%esp)
-; SSE2_32-NEXT: flds (%esp)
+; SSE2_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl
@@ -384,19 +360,15 @@ define float @u64_to_f(i64 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $24, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
+; SSE1_32-NEXT: fldl 8(%ebp)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE1_32-NEXT: movss %xmm0, (%esp)
-; SSE1_32-NEXT: flds (%esp)
+; SSE1_32-NEXT: flds {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl
@@ -407,12 +379,10 @@ define float @u64_to_f(i64 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
-; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll {{[0-9]+}}(%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp)
@@ -443,10 +413,8 @@ define float @s64_to_f(i64 %a) nounwind {
; AVX512DQ_32-LABEL: s64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
-; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtqq2ps %zmm0, %ymm0
-; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
-; AVX512DQ_32-NEXT: flds (%esp)
+; AVX512DQ_32-NEXT: flds {{[0-9]+}}(%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
@@ -695,12 +663,10 @@ define double @u64_to_d(i64 %a) nounwind {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
-; SSE1_32-NEXT: fildll (%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
@@ -714,12 +680,10 @@ define double @u64_to_d(i64 %a) nounwind {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
-; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -816,12 +780,10 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; SSE1_32-NEXT: movl %esp, %ebp
; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp
-; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx
-; SSE1_32-NEXT: fildll (%esp)
+; SSE1_32-NEXT: fildll 8(%ebp)
; SSE1_32-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
@@ -835,12 +797,10 @@ define double @u64_to_d_optsize(i64 %a) nounwind optsize {
; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp
-; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx
-; X87-NEXT: fildll (%esp)
+; X87-NEXT: fildll 8(%ebp)
; X87-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp)
@@ -1070,12 +1030,10 @@ define x86_fp80 @u64_to_x(i64 %a) nounwind {
; CHECK32-NEXT: movl %esp, %ebp
; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp
-; CHECK32-NEXT: movl 8(%ebp), %eax
; CHECK32-NEXT: movl 12(%ebp), %ecx
; CHECK32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; CHECK32-NE...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213498
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