[llvm] [ExpandReductions] Add support for non-pow2 vector counts (PR #208738)
Prajwal KP via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 1 08:46:38 PDT 2026
https://github.com/Prajwal-kp-18 updated https://github.com/llvm/llvm-project/pull/208738
>From 900d6e968891d8bccfae011573cdaeea92a97867 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Fri, 10 Jul 2026 19:52:57 +0530
Subject: [PATCH 1/2] [CodeGen] Expand non-pow2 vector reductions by
scalarizing
---
llvm/lib/CodeGen/ExpandReductions.cpp | 46 +++-
llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll | 155 ++++-------
llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll | 96 +++----
llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll | 149 +++++------
llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll | 63 ++---
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 161 ++++--------
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 161 ++++--------
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 122 +++------
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 124 +++------
llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll | 80 +++---
.../Generic/expand-experimental-reductions.ll | 6 +-
.../RISCV/rvv/fixed-vectors-reduction-int.ll | 19 +-
.../test/CodeGen/RISCV/rvv/vreductions-int.ll | 246 +++++++++++-------
.../llvm-intrinsics/llvm-vector-reduce/add.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/and.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/mul.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/or.ll | 8 +-
.../llvm-vector-reduce/smax.ll | 8 +-
.../llvm-vector-reduce/smin.ll | 8 +-
.../llvm-vector-reduce/umax.ll | 8 +-
.../llvm-vector-reduce/umin.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/xor.ll | 8 +-
.../WebAssembly/simd-vecreduce-bool.ll | 4 +-
.../CodeGen/X86/vector-reduce-fmax-nnan.ll | 24 +-
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll | 127 ++++++---
25 files changed, 706 insertions(+), 949 deletions(-)
diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
index d075a677e0586..94d7dd2699ab0 100644
--- a/llvm/lib/CodeGen/ExpandReductions.cpp
+++ b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -28,6 +28,21 @@ using namespace llvm;
namespace {
+Value *expandScalarizedReduction(IRBuilderBase &Builder, Value *Vec,
+ unsigned RdxOpcode, RecurKind RK) {
+ auto *VecTy = cast<FixedVectorType>(Vec->getType());
+ Value *Res = Builder.CreateExtractElement(Vec, uint64_t(0));
+ for (unsigned I = 1, E = VecTy->getNumElements(); I != E; ++I) {
+ Value *Ext = Builder.CreateExtractElement(Vec, I);
+ if (RdxOpcode == Instruction::ICmp || RdxOpcode == Instruction::FCmp)
+ Res = createMinMaxOp(Builder, RK, Res, Ext);
+ else
+ Res = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, Res, Ext,
+ "bin.rdx");
+ }
+ return Res;
+}
+
bool expandReductions(Function &F, const TargetTransformInfo *TTI,
DominatorTree *DT, LoopInfo *LI) {
bool Changed = false;
@@ -86,12 +101,11 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
Rdx = expandReductionViaLoop(Builder, Vec, RdxOpcode, Acc, DT, LI);
break;
}
- if (!FMF.allowReassoc())
+ if (!FMF.allowReassoc() ||
+ !isPowerOf2_32(
+ cast<FixedVectorType>(Vec->getType())->getNumElements()))
Rdx = getOrderedReduction(Builder, Acc, Vec, RdxOpcode, RK);
else {
- if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()))
- continue;
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
Rdx = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, Acc, Rdx,
"bin.rdx");
@@ -110,10 +124,9 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
Value *Vec = II->getArgOperand(0);
auto *FTy = cast<FixedVectorType>(Vec->getType());
unsigned NumElts = FTy->getNumElements();
- if (!isPowerOf2_32(NumElts))
- continue;
- if (FTy->getElementType() == Builder.getInt1Ty()) {
+ if (FTy->getElementType() == Builder.getInt1Ty() &&
+ isPowerOf2_32(NumElts)) {
Rdx = Builder.CreateBitCast(Vec, Builder.getIntNTy(NumElts));
if (ID == Intrinsic::vector_reduce_and) {
Rdx = Builder.CreateICmpEQ(
@@ -125,6 +138,10 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
break;
}
unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+ if (!isPowerOf2_32(NumElts)) {
+ Rdx = expandScalarizedReduction(Builder, Vec, RdxOpcode, RK);
+ break;
+ }
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
@@ -144,8 +161,10 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
break;
}
if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()))
- continue;
+ cast<FixedVectorType>(Vec->getType())->getNumElements())) {
+ Rdx = expandScalarizedReduction(Builder, Vec, RdxOpcode, RK);
+ break;
+ }
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
@@ -154,11 +173,14 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
// We require "nnan" to use a shuffle reduction; "nsz" is implied by the
// semantics of the reduction.
Value *Vec = II->getArgOperand(0);
- if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()) ||
- !FMF.noNaNs())
+ if (!FMF.noNaNs())
continue;
unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+ if (!isPowerOf2_32(
+ cast<FixedVectorType>(Vec->getType())->getNumElements())) {
+ Rdx = expandScalarizedReduction(Builder, Vec, RdxOpcode, RK);
+ break;
+ }
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index 01b7293dcd7ab..04cf72c55838d 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -110,76 +110,48 @@ entry:
}
define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_add_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_add_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_add_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_add_v3i8:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i8:
@@ -205,9 +177,9 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i8:
@@ -217,9 +189,9 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i8:
@@ -1298,10 +1270,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_add_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_add_v3i16:
@@ -1319,53 +1290,37 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_add_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_pk_add_u16 v1, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_add_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_add_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_add_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_add_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-SDAG-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_add_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_add_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_add_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i16:
@@ -1393,9 +1348,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
@@ -1406,9 +1361,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
index 0ae4b05aa7c89..e045d3440c2ed 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
@@ -161,76 +161,48 @@ entry:
}
define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_and_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_and_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_and_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_and_v3i8:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_and_v3i8:
@@ -248,9 +220,9 @@ define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i8:
@@ -260,9 +232,9 @@ define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_and_v3i8:
@@ -1068,9 +1040,9 @@ define i16 @test_vector_reduce_and_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_and_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_and_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
index b931b312ff251..a0f2d5830adb1 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
@@ -175,8 +175,12 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_mul_v3i8:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_mul_v3i8:
@@ -186,62 +190,41 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_mul_lo_u32 v0, v0, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v1, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_mul_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_mul_lo_u16_e32 v0, v1, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_mul_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_mul_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_mul_lo_u16 v0, v1, v0
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_mul_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_mul_v3i8:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_mul_v3i8:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
@@ -267,9 +250,9 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i8:
@@ -279,9 +262,9 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v1, v0
+; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
@@ -1240,12 +1223,12 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_mul_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_or_b32_e32 v1, 0x10000, v1
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v1, v0, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, 1, v0
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_mul_v3i16:
@@ -1263,53 +1246,37 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_mul_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v1, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_mul_lo_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_mul_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_lo_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_mul_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_mul_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_mul_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_mul_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
@@ -1337,9 +1304,9 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
@@ -1350,9 +1317,9 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
index d7db9c845b4ad..f0896f23a980c 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
@@ -161,39 +161,25 @@ entry:
}
define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_or_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_or_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_or_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_or_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-GISEL-LABEL: test_vector_reduce_or_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_or_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_or_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -205,8 +191,8 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX10-SDAG-LABEL: test_vector_reduce_or_v3i8:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -218,17 +204,17 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -244,9 +230,9 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i8:
@@ -256,9 +242,9 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -1098,10 +1084,9 @@ define i16 @test_vector_reduce_or_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_or_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_or_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 219961c35071d..34a76a47ebff7 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -137,11 +137,9 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-SDAG-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0xff80
-; GFX7-SDAG-NEXT: v_max3_i32 v0, v1, v0, s4
+; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -153,28 +151,20 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_smax_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_max_i16_sdwa v0, sext(v1), v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_max_i16_e32 v0, 0xff80, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_smax_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_max_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_smax_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_max_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX9-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX9-SDAG-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0xff80
-; GFX9-SDAG-NEXT: v_max3_i16 v0, v1, v0, s0
+; GFX9-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-SDAG-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -190,10 +180,9 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-SDAG-NEXT: v_max_i16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_max3_i16 v0, v1, v0, 0xff80
+; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX10-SDAG-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -208,28 +197,21 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v0.l, 0xff80
+; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_max3_i16 v0, v1, v0, 0xff80
+; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -249,17 +231,11 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v0.l, 0xff80
+; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i8:
@@ -270,11 +246,10 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: v_max3_i16 v0, v1, v0, 0xff80
+; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -1694,12 +1669,10 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_smax_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX7-SDAG-NEXT: v_bfe_i32 v2, v0, 0, 16
+; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX7-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v2, s4
+; GFX7-SDAG-NEXT: v_max3_i32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v3i16:
@@ -1718,62 +1691,34 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_max_i16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_smax_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0x8000
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v1, s0, v1, v2
-; GFX9-SDAG-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_max_i16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_smax_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX10-SDAG-NEXT: v_perm_b32 v1, s4, v1, 0x5040100
-; GFX10-SDAG-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_max_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_smax_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_smax_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_smax_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i16:
@@ -1791,12 +1736,9 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x8000
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v2.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
@@ -1806,14 +1748,9 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 376a64bb86271..0b3abaa8a59d8 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -137,11 +137,9 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-SDAG-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0x7f
-; GFX7-SDAG-NEXT: v_min3_i32 v0, v1, v0, s4
+; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -153,28 +151,20 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_smin_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_min_i16_sdwa v0, sext(v1), v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_min_i16_e32 v0, 0x7f, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_smin_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_min_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_smin_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_min_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX9-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX9-SDAG-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0x7f
-; GFX9-SDAG-NEXT: v_min3_i16 v0, v1, v0, s0
+; GFX9-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-SDAG-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -190,10 +180,9 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-SDAG-NEXT: v_min_i16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_min3_i16 v0, v1, v0, 0x7f
+; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX10-SDAG-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -208,28 +197,21 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v0.l, 0x7f
+; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_min3_i16 v0, v1, v0, 0x7f
+; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -249,17 +231,11 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v0.l, 0x7f
+; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i8:
@@ -270,11 +246,10 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: v_min3_i16 v0, v1, v0, 0x7f
+; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -1694,12 +1669,10 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_smin_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX7-SDAG-NEXT: v_bfe_i32 v2, v0, 0, 16
+; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX7-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v2, s4
+; GFX7-SDAG-NEXT: v_min3_i32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v3i16:
@@ -1718,62 +1691,34 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_min_i16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_smin_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0x7fff
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v1, s0, v1, v2
-; GFX9-SDAG-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_min_i16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_smin_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x7fff
-; GFX10-SDAG-NEXT: v_perm_b32 v1, s4, v1, 0x5040100
-; GFX10-SDAG-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_min_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_smin_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_smin_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_smin_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i16:
@@ -1791,12 +1736,9 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fff
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v2.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
@@ -1806,14 +1748,9 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7fff
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 087832601598a..7687005c77946 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -137,9 +137,9 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-SDAG-NEXT: v_max3_u32 v0, v1, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -151,27 +151,20 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_umax_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_max_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_umax_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_umax_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_max_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX9-SDAG-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-SDAG-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -187,9 +180,9 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-SDAG-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-SDAG-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -205,20 +198,20 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -239,10 +232,10 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i8:
@@ -253,10 +246,10 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -1583,11 +1576,10 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_umax_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7-SDAG-NEXT: v_max_u32_e32 v1, v2, v1
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-SDAG-NEXT: v_max3_u32 v0, v1, v0, 0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-SDAG-NEXT: v_max3_u32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v3i16:
@@ -1606,58 +1598,34 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_max_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_umax_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-SDAG-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_max_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_umax_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-SDAG-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_max_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_umax_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_umax_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_umax_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i16:
@@ -1675,12 +1643,9 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v2.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
@@ -1690,12 +1655,9 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 5443cce424a5c..7510978cb4234 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -137,9 +137,9 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-SDAG-NEXT: v_min3_u32 v0, v1, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -151,27 +151,20 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_umin_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_min_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_umin_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_umin_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umin_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX9-SDAG-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-SDAG-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -187,9 +180,9 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-SDAG-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-SDAG-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -205,20 +198,20 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -239,10 +232,10 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i8:
@@ -253,10 +246,10 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -1363,12 +1356,10 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_umin_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7-SDAG-NEXT: s_mov_b32 s4, 0xffff
-; GFX7-SDAG-NEXT: v_min_u32_e32 v1, v2, v1
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-SDAG-NEXT: v_min3_u32 v0, v1, v0, s4
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-SDAG-NEXT: v_min3_u32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v3i16:
@@ -1387,59 +1378,34 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_min_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_umin_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v1, -1, v1, v2
-; GFX9-SDAG-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_min_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_umin_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_perm_b32 v1, -1, v1, 0x5040100
-; GFX10-SDAG-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_min_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_umin_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_umin_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_umin_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, -1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, -1, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i16:
@@ -1457,12 +1423,9 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, -1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v2.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
@@ -1472,12 +1435,9 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, -1, v1, 0x5040100
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
index b9a8ea279ad15..8a160be83a6cb 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
@@ -161,53 +161,32 @@ entry:
}
define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_xor_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_xor_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_xor_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_xor_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: test_vector_reduce_xor_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_xor_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_xor_v3i8:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_xor_v3i8:
@@ -219,17 +198,17 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_xor_v3i8:
@@ -245,9 +224,9 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i8:
@@ -257,9 +236,9 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_xor_v3i8:
@@ -1045,10 +1024,9 @@ define i16 @test_vector_reduce_xor_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_xor_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_xor_v3i16:
diff --git a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
index b8e473cbaa4c8..d8876a20591fe 100644
--- a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
+++ b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
@@ -305,7 +305,11 @@ entry:
define i8 @test_v3i8(<3 x i8> %a) nounwind {
; CHECK-LABEL: @test_v3i8(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> [[A:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i8> [[A:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i8> [[A]], i64 1
+; CHECK-NEXT: [[BIN_RDX:%.*]] = and i8 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i8> [[A]], i64 2
+; CHECK-NEXT: [[B:%.*]] = and i8 [[BIN_RDX]], [[TMP2]]
; CHECK-NEXT: ret i8 [[B]]
;
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index 4ef25e3ec8fbf..66c1db12d6705 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -5379,20 +5379,15 @@ define i8 @vreduce_mul_v2i8(ptr %x) {
define i8 @vreduce_mul_v3i8(ptr %x) {
; CHECK-LABEL: vreduce_mul_v3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 1
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
-; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v9, v8, 3
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vmul.vv v8, v9, v8
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vslidedown.vi v9, v8, 1
+; CHECK-NEXT: vmv.x.s a1, v9
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: vmv.x.s a1, v8
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: ret
%v = load <3 x i8>, ptr %x
%red = call i8 @llvm.vector.reduce.mul.v3i8(<3 x i8> %v)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
index 0c2fee71b45af..f4a1fc4f578a3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
@@ -2420,112 +2420,158 @@ define signext i32 @vreduce_mul_nxv4i32_exact_vlen(<vscale x 4 x i32> %v) vscale
}
define signext i32 @vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen(<vscale x 8 x i32> %v) vscale_range(2,2) {
-; CHECK-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v11, v10, 3
-; CHECK-NEXT: vmv.x.s a0, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vmv.x.s a1, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 1
-; CHECK-NEXT: vmv.x.s a2, v11
-; CHECK-NEXT: vmv.x.s a3, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vmv.x.s a4, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 2
-; CHECK-NEXT: vmv.x.s a5, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.x.s a6, v10
-; CHECK-NEXT: vmv.x.s a7, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 3
-; CHECK-NEXT: vmv.x.s t0, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vmv.x.s t1, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vmv.x.s t2, v8
-; CHECK-NEXT: vmv.x.s t3, v9
-; CHECK-NEXT: vmv.v.x v8, t3
-; CHECK-NEXT: vslide1down.vx v8, v8, t2
-; CHECK-NEXT: vslide1down.vx v8, v8, t1
-; CHECK-NEXT: vslide1down.vx v9, v8, t0
-; CHECK-NEXT: vmv.v.x v8, a7
-; CHECK-NEXT: vmv.v.x v10, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a6
-; CHECK-NEXT: vslide1down.vx v10, v10, a2
-; CHECK-NEXT: vslide1down.vx v8, v8, a5
-; CHECK-NEXT: vslide1down.vx v10, v10, a1
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: vslide1down.vx v10, v10, a0
-; CHECK-NEXT: vmv.v.i v11, 1
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v11, v10, 1
+; RV32-NEXT: vmv.x.s a0, v11
+; RV32-NEXT: vmv.x.s a1, v10
+; RV32-NEXT: vslidedown.vi v11, v9, 3
+; RV32-NEXT: vmv.x.s a2, v11
+; RV32-NEXT: vslidedown.vi v11, v9, 1
+; RV32-NEXT: vmv.x.s a3, v11
+; RV32-NEXT: vmv.x.s a4, v9
+; RV32-NEXT: vslidedown.vi v11, v8, 3
+; RV32-NEXT: vmv.x.s a5, v11
+; RV32-NEXT: vslidedown.vi v11, v8, 2
+; RV32-NEXT: vmv.x.s a6, v11
+; RV32-NEXT: vmv.x.s a7, v8
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s t0, v8
+; RV32-NEXT: vslidedown.vi v8, v9, 2
+; RV32-NEXT: vmv.x.s t1, v8
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: mul a5, a6, a5
+; RV32-NEXT: mul a3, a4, a3
+; RV32-NEXT: mul a1, a2, a1
+; RV32-NEXT: vslidedown.vi v8, v10, 2
+; RV32-NEXT: vmv.x.s a2, v8
+; RV32-NEXT: mul a4, a7, a5
+; RV32-NEXT: mul a3, a3, t1
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: mul a1, a4, a3
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: vslidedown.vi v8, v10, 3
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: vmv.x.s a1, v8
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v11, v10, 1
+; RV64-NEXT: vmv.x.s a0, v11
+; RV64-NEXT: vmv.x.s a1, v10
+; RV64-NEXT: vslidedown.vi v11, v9, 3
+; RV64-NEXT: vmv.x.s a2, v11
+; RV64-NEXT: vslidedown.vi v11, v9, 1
+; RV64-NEXT: vmv.x.s a3, v11
+; RV64-NEXT: vmv.x.s a4, v9
+; RV64-NEXT: vslidedown.vi v11, v8, 3
+; RV64-NEXT: vmv.x.s a5, v11
+; RV64-NEXT: vslidedown.vi v11, v8, 2
+; RV64-NEXT: vmv.x.s a6, v11
+; RV64-NEXT: vmv.x.s a7, v8
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s t0, v8
+; RV64-NEXT: vslidedown.vi v8, v9, 2
+; RV64-NEXT: vmv.x.s t1, v8
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: mul a5, a6, a5
+; RV64-NEXT: mul a3, a4, a3
+; RV64-NEXT: mul a1, a2, a1
+; RV64-NEXT: vslidedown.vi v8, v10, 2
+; RV64-NEXT: vmv.x.s a2, v8
+; RV64-NEXT: mul a4, a7, a5
+; RV64-NEXT: mul a3, a3, t1
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: mul a1, a4, a3
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: vslidedown.vi v8, v10, 3
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: vmv.x.s a1, v8
+; RV64-NEXT: mulw a0, a0, a1
+; RV64-NEXT: ret
%sub = call <vscale x 6 x i32> @llvm.vector.extract.nxv6i32.nxv8i32(<vscale x 8 x i32> %v, i64 0)
%red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %sub)
ret i32 %red
}
define signext i32 @vreduce_mul_nxv6i32_exact_vlen(<vscale x 6 x i32> %v) vscale_range(2,2) {
-; CHECK-LABEL: vreduce_mul_nxv6i32_exact_vlen:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v11, v10, 3
-; CHECK-NEXT: vmv.x.s a0, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vmv.x.s a1, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 1
-; CHECK-NEXT: vmv.x.s a2, v11
-; CHECK-NEXT: vmv.x.s a3, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vmv.x.s a4, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 2
-; CHECK-NEXT: vmv.x.s a5, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.x.s a6, v10
-; CHECK-NEXT: vmv.x.s a7, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 3
-; CHECK-NEXT: vmv.x.s t0, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vmv.x.s t1, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vmv.x.s t2, v8
-; CHECK-NEXT: vmv.x.s t3, v9
-; CHECK-NEXT: vmv.v.x v8, t3
-; CHECK-NEXT: vslide1down.vx v8, v8, t2
-; CHECK-NEXT: vslide1down.vx v8, v8, t1
-; CHECK-NEXT: vslide1down.vx v9, v8, t0
-; CHECK-NEXT: vmv.v.x v8, a7
-; CHECK-NEXT: vmv.v.x v10, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a6
-; CHECK-NEXT: vslide1down.vx v10, v10, a2
-; CHECK-NEXT: vslide1down.vx v8, v8, a5
-; CHECK-NEXT: vslide1down.vx v10, v10, a1
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: vslide1down.vx v10, v10, a0
-; CHECK-NEXT: vmv.v.i v11, 1
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vreduce_mul_nxv6i32_exact_vlen:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v11, v10, 1
+; RV32-NEXT: vmv.x.s a0, v11
+; RV32-NEXT: vmv.x.s a1, v10
+; RV32-NEXT: vslidedown.vi v11, v9, 3
+; RV32-NEXT: vmv.x.s a2, v11
+; RV32-NEXT: vslidedown.vi v11, v9, 1
+; RV32-NEXT: vmv.x.s a3, v11
+; RV32-NEXT: vmv.x.s a4, v9
+; RV32-NEXT: vslidedown.vi v11, v8, 3
+; RV32-NEXT: vmv.x.s a5, v11
+; RV32-NEXT: vslidedown.vi v11, v8, 2
+; RV32-NEXT: vmv.x.s a6, v11
+; RV32-NEXT: vmv.x.s a7, v8
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s t0, v8
+; RV32-NEXT: vslidedown.vi v8, v9, 2
+; RV32-NEXT: vmv.x.s t1, v8
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: mul a5, a6, a5
+; RV32-NEXT: mul a3, a4, a3
+; RV32-NEXT: mul a1, a2, a1
+; RV32-NEXT: vslidedown.vi v8, v10, 2
+; RV32-NEXT: vmv.x.s a2, v8
+; RV32-NEXT: mul a4, a7, a5
+; RV32-NEXT: mul a3, a3, t1
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: mul a1, a4, a3
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: vslidedown.vi v8, v10, 3
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: vmv.x.s a1, v8
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_mul_nxv6i32_exact_vlen:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v11, v10, 1
+; RV64-NEXT: vmv.x.s a0, v11
+; RV64-NEXT: vmv.x.s a1, v10
+; RV64-NEXT: vslidedown.vi v11, v9, 3
+; RV64-NEXT: vmv.x.s a2, v11
+; RV64-NEXT: vslidedown.vi v11, v9, 1
+; RV64-NEXT: vmv.x.s a3, v11
+; RV64-NEXT: vmv.x.s a4, v9
+; RV64-NEXT: vslidedown.vi v11, v8, 3
+; RV64-NEXT: vmv.x.s a5, v11
+; RV64-NEXT: vslidedown.vi v11, v8, 2
+; RV64-NEXT: vmv.x.s a6, v11
+; RV64-NEXT: vmv.x.s a7, v8
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s t0, v8
+; RV64-NEXT: vslidedown.vi v8, v9, 2
+; RV64-NEXT: vmv.x.s t1, v8
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: mul a5, a6, a5
+; RV64-NEXT: mul a3, a4, a3
+; RV64-NEXT: mul a1, a2, a1
+; RV64-NEXT: vslidedown.vi v8, v10, 2
+; RV64-NEXT: vmv.x.s a2, v8
+; RV64-NEXT: mul a4, a7, a5
+; RV64-NEXT: mul a3, a3, t1
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: mul a1, a4, a3
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: vslidedown.vi v8, v10, 3
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: vmv.x.s a1, v8
+; RV64-NEXT: mulw a0, a0, a1
+; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %v)
ret i32 %red
}
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
index 39cbd8726400a..292aee52ad1c8 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
@@ -31,8 +31,8 @@
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpIAdd %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpIAdd %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -48,8 +48,8 @@
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpIAdd %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpIAdd %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -65,8 +65,8 @@
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpIAdd %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpIAdd %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -82,8 +82,8 @@
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpIAdd %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpIAdd %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
index a911cdf094045..4e02dbfc2c115 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
@@ -31,8 +31,8 @@
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseAnd %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseAnd %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -48,8 +48,8 @@
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseAnd %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseAnd %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -65,8 +65,8 @@
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseAnd %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseAnd %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -82,8 +82,8 @@
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseAnd %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseAnd %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
index 86e6d42de55d1..8c65e42addeff 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpIMul %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpIMul %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpIMul %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpIMul %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpIMul %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpIMul %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpIMul %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpIMul %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
index 34e5272ecd629..e7e0348c43ca4 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseOr %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseOr %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseOr %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseOr %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseOr %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseOr %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseOr %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseOr %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
index eafd4e096a728..4a49999a81b78 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] s_max %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] s_max %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] s_max %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] s_max %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] s_max %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] s_max %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
index bbd22d4c6d4c5..8d9c128f36165 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] s_min %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] s_min %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] s_min %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] s_min %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] s_min %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] s_min %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
index 80be288d0b941..a0ddc19d65fc4 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] u_max %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] u_max %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] u_max %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] u_max %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] u_max %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] u_max %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
index 2c4832c877783..2516c0a3ecda1 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] u_min %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] u_min %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] u_min %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] u_min %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] u_min %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] u_min %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
index 2532154cfc15c..d20d754f88ca1 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseXor %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseXor %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseXor %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseXor %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseXor %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseXor %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseXor %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseXor %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
index a6100dd08d7c6..b30c3ca188d5f 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
@@ -265,9 +265,7 @@ define i1 @test_all_v7i1(<7 x i1> %x) {
; CHECK-NEXT: i32.and $push3=, $pop2, $4
; CHECK-NEXT: i32.and $push4=, $pop3, $5
; CHECK-NEXT: i32.and $push5=, $pop4, $6
-; CHECK-NEXT: i32.const $push6=, 1
-; CHECK-NEXT: i32.and $push7=, $pop5, $pop6
-; CHECK-NEXT: return $pop7
+; CHECK-NEXT: return $pop5
%ret = call i1 @llvm.vector.reduce.and.v7i1(<7 x i1> %x)
ret i1 %ret
}
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll b/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
index 179790c46f33c..eee61b20da9fd 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
@@ -216,25 +216,11 @@ define double @test_v2f64(<2 x double> %a0) {
}
define double @test_v3f64(<3 x double> %a0) {
-; SSE2-LABEL: test_v3f64:
-; SSE2: # %bb.0:
-; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE2-NEXT: shufpd {{.*#+}} xmm2 = xmm2[0],mem[1]
-; SSE2-NEXT: maxpd %xmm2, %xmm0
-; SSE2-NEXT: movapd %xmm0, %xmm1
-; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
-; SSE2-NEXT: maxsd %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSE41-LABEL: test_v3f64:
-; SSE41: # %bb.0:
-; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1]
-; SSE41-NEXT: maxpd %xmm2, %xmm0
-; SSE41-NEXT: movapd %xmm0, %xmm1
-; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
-; SSE41-NEXT: maxsd %xmm1, %xmm0
-; SSE41-NEXT: retq
+; SSE-LABEL: test_v3f64:
+; SSE: # %bb.0:
+; SSE-NEXT: maxsd %xmm1, %xmm0
+; SSE-NEXT: maxsd %xmm2, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: test_v3f64:
; AVX: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index acc90d2b4488d..15a349827dfd8 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -2072,35 +2072,82 @@ define zeroext i1 @PR44781(ptr %0) {
}
define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
-; SSE-LABEL: mask_v3i1:
-; SSE: # %bb.0:
-; SSE-NEXT: pcmpeqd %xmm1, %xmm0
-; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; SSE-NEXT: por %xmm0, %xmm1
-; SSE-NEXT: movd %xmm1, %eax
-; SSE-NEXT: testb $1, %al
-; SSE-NEXT: je .LBB30_2
-; SSE-NEXT: # %bb.1:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: ret{{[l|q]}}
-; SSE-NEXT: .LBB30_2:
-; SSE-NEXT: movl $1, %eax
-; SSE-NEXT: ret{{[l|q]}}
+; X86-SSE2-LABEL: mask_v3i1:
+; X86-SSE2: # %bb.0:
+; X86-SSE2-NEXT: pushl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
+; X86-SSE2-NEXT: .cfi_offset %ebp, -8
+; X86-SSE2-NEXT: movl %esp, %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
+; X86-SSE2-NEXT: andl $-16, %esp
+; X86-SSE2-NEXT: subl $32, %esp
+; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
+; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
+; X86-SSE2-NEXT: pxor %xmm0, %xmm1
+; X86-SSE2-NEXT: movdqa %xmm1, (%esp)
+; X86-SSE2-NEXT: movzbl (%esp), %eax
+; X86-SSE2-NEXT: orb {{[0-9]+}}(%esp), %al
+; X86-SSE2-NEXT: orb {{[0-9]+}}(%esp), %al
+; X86-SSE2-NEXT: testb $1, %al
+; X86-SSE2-NEXT: je .LBB30_3
+; X86-SSE2-NEXT: # %bb.1:
+; X86-SSE2-NEXT: xorl %eax, %eax
+; X86-SSE2-NEXT: jmp .LBB30_2
+; X86-SSE2-NEXT: .LBB30_3:
+; X86-SSE2-NEXT: movl $1, %eax
+; X86-SSE2-NEXT: .LBB30_2:
+; X86-SSE2-NEXT: movl %ebp, %esp
+; X86-SSE2-NEXT: popl %ebp
+; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
+; X86-SSE2-NEXT: retl
+;
+; X64-SSE2-LABEL: mask_v3i1:
+; X64-SSE2: # %bb.0:
+; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
+; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
+; X64-SSE2-NEXT: pxor %xmm0, %xmm1
+; X64-SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)
+; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
+; X64-SSE2-NEXT: orb -{{[0-9]+}}(%rsp), %al
+; X64-SSE2-NEXT: orb -{{[0-9]+}}(%rsp), %al
+; X64-SSE2-NEXT: testb $1, %al
+; X64-SSE2-NEXT: je .LBB30_2
+; X64-SSE2-NEXT: # %bb.1:
+; X64-SSE2-NEXT: xorl %eax, %eax
+; X64-SSE2-NEXT: retq
+; X64-SSE2-NEXT: .LBB30_2:
+; X64-SSE2-NEXT: movl $1, %eax
+; X64-SSE2-NEXT: retq
+;
+; SSE4-LABEL: mask_v3i1:
+; SSE4: # %bb.0:
+; SSE4-NEXT: pcmpeqd %xmm1, %xmm0
+; SSE4-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE4-NEXT: pxor %xmm0, %xmm1
+; SSE4-NEXT: movd %xmm1, %eax
+; SSE4-NEXT: pextrb $4, %xmm1, %ecx
+; SSE4-NEXT: orl %eax, %ecx
+; SSE4-NEXT: pextrb $8, %xmm1, %eax
+; SSE4-NEXT: orl %ecx, %eax
+; SSE4-NEXT: testb $1, %al
+; SSE4-NEXT: je .LBB30_2
+; SSE4-NEXT: # %bb.1:
+; SSE4-NEXT: xorl %eax, %eax
+; SSE4-NEXT: ret{{[l|q]}}
+; SSE4-NEXT: .LBB30_2:
+; SSE4-NEXT: movl $1, %eax
+; SSE4-NEXT: ret{{[l|q]}}
;
; AVX1OR2-LABEL: mask_v3i1:
; AVX1OR2: # %bb.0:
; AVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX1OR2-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX1OR2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm1
-; AVX1OR2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; AVX1OR2-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX1OR2-NEXT: vmovd %xmm0, %eax
+; AVX1OR2-NEXT: vpextrb $4, %xmm0, %ecx
+; AVX1OR2-NEXT: orl %eax, %ecx
+; AVX1OR2-NEXT: vpextrb $8, %xmm0, %eax
+; AVX1OR2-NEXT: orl %ecx, %eax
; AVX1OR2-NEXT: testb $1, %al
; AVX1OR2-NEXT: je .LBB30_2
; AVX1OR2-NEXT: # %bb.1:
@@ -2116,11 +2163,13 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vpcmpneqd %zmm1, %zmm0, %k0
; AVX512F-NEXT: kshiftrw $2, %k0, %k1
-; AVX512F-NEXT: korw %k1, %k0, %k1
-; AVX512F-NEXT: kshiftrw $1, %k0, %k0
-; AVX512F-NEXT: korw %k0, %k1, %k0
-; AVX512F-NEXT: kmovw %k0, %eax
-; AVX512F-NEXT: testb $1, %al
+; AVX512F-NEXT: kmovw %k1, %eax
+; AVX512F-NEXT: kshiftrw $1, %k0, %k1
+; AVX512F-NEXT: kmovw %k1, %ecx
+; AVX512F-NEXT: kmovw %k0, %edx
+; AVX512F-NEXT: orb %cl, %dl
+; AVX512F-NEXT: orb %al, %dl
+; AVX512F-NEXT: testb $1, %dl
; AVX512F-NEXT: je .LBB30_2
; AVX512F-NEXT: # %bb.1:
; AVX512F-NEXT: xorl %eax, %eax
@@ -2137,11 +2186,13 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512BW-NEXT: vpcmpneqd %zmm1, %zmm0, %k0
; AVX512BW-NEXT: kshiftrw $2, %k0, %k1
-; AVX512BW-NEXT: korw %k1, %k0, %k1
-; AVX512BW-NEXT: kshiftrw $1, %k0, %k0
-; AVX512BW-NEXT: korw %k0, %k1, %k0
-; AVX512BW-NEXT: kmovd %k0, %eax
-; AVX512BW-NEXT: testb $1, %al
+; AVX512BW-NEXT: kmovd %k1, %eax
+; AVX512BW-NEXT: kshiftrw $1, %k0, %k1
+; AVX512BW-NEXT: kmovd %k1, %ecx
+; AVX512BW-NEXT: kmovd %k0, %edx
+; AVX512BW-NEXT: orb %cl, %dl
+; AVX512BW-NEXT: orb %al, %dl
+; AVX512BW-NEXT: testb $1, %dl
; AVX512BW-NEXT: je .LBB30_2
; AVX512BW-NEXT: # %bb.1:
; AVX512BW-NEXT: xorl %eax, %eax
@@ -2156,11 +2207,13 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpcmpneqd %xmm1, %xmm0, %k0
; AVX512VL-NEXT: kshiftrb $2, %k0, %k1
-; AVX512VL-NEXT: korw %k1, %k0, %k1
-; AVX512VL-NEXT: kshiftrb $1, %k0, %k0
-; AVX512VL-NEXT: korw %k0, %k1, %k0
-; AVX512VL-NEXT: kmovd %k0, %eax
-; AVX512VL-NEXT: testb $1, %al
+; AVX512VL-NEXT: kmovd %k1, %eax
+; AVX512VL-NEXT: kshiftrb $1, %k0, %k1
+; AVX512VL-NEXT: kmovd %k1, %ecx
+; AVX512VL-NEXT: kmovd %k0, %edx
+; AVX512VL-NEXT: orb %cl, %dl
+; AVX512VL-NEXT: orb %al, %dl
+; AVX512VL-NEXT: testb $1, %dl
; AVX512VL-NEXT: je .LBB30_2
; AVX512VL-NEXT: # %bb.1:
; AVX512VL-NEXT: xorl %eax, %eax
>From 57eae25a80ef5a140fc07f55f8a2cd5fc41cd745 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Sat, 1 Aug 2026 15:00:20 +0530
Subject: [PATCH 2/2] [CodeGen] Pad non-pow2 i1 reductions to a power of 2
instead of scalarizing
---
llvm/lib/CodeGen/ExpandReductions.cpp | 15 ++-
.../Generic/expand-experimental-reductions.ll | 31 ++++++
.../WebAssembly/simd-vecreduce-bool.ll | 42 +++++---
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll | 102 ++++++------------
4 files changed, 106 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
index 94d7dd2699ab0..f7a120b7c9d6a 100644
--- a/llvm/lib/CodeGen/ExpandReductions.cpp
+++ b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -23,6 +23,7 @@
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Transforms/Utils/LoopUtils.h"
+#include <numeric>
using namespace llvm;
@@ -125,9 +126,17 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
auto *FTy = cast<FixedVectorType>(Vec->getType());
unsigned NumElts = FTy->getNumElements();
- if (FTy->getElementType() == Builder.getInt1Ty() &&
- isPowerOf2_32(NumElts)) {
- Rdx = Builder.CreateBitCast(Vec, Builder.getIntNTy(NumElts));
+ if (FTy->getElementType() == Builder.getInt1Ty()) {
+ unsigned Width = PowerOf2Ceil(NumElts);
+ if (Width != NumElts) {
+ Constant *Identity = ID == Intrinsic::vector_reduce_and
+ ? Constant::getAllOnesValue(FTy)
+ : Constant::getNullValue(FTy);
+ SmallVector<int, 16> Mask(Width);
+ std::iota(Mask.begin(), Mask.end(), 0);
+ Vec = Builder.CreateShuffleVector(Vec, Identity, Mask);
+ }
+ Rdx = Builder.CreateBitCast(Vec, Builder.getIntNTy(Width));
if (ID == Intrinsic::vector_reduce_and) {
Rdx = Builder.CreateICmpEQ(
Rdx, ConstantInt::getAllOnesValue(Rdx->getType()));
diff --git a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
index d8876a20591fe..f7d2f25ffeea1 100644
--- a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
+++ b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
@@ -20,6 +20,9 @@ declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
declare i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8>)
+declare i1 @llvm.vector.reduce.or.v3i1(<3 x i1>)
+declare i1 @llvm.vector.reduce.and.v7i1(<7 x i1>)
+
define i64 @add_i64(<2 x i64> %vec) {
; CHECK-LABEL: @add_i64(
; CHECK-NEXT: entry:
@@ -316,3 +319,31 @@ entry:
%b = call i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8> %a)
ret i8 %b
}
+
+; i1 reductions of a non power of two vector are padded out with the identity
+; element rather than scalarized.
+define i1 @test_or_v3i1(<3 x i1> %a) nounwind {
+; CHECK-LABEL: @test_or_v3i1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x i1> [[A:%.*]], <3 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+entry:
+ %b = call i1 @llvm.vector.reduce.or.v3i1(<3 x i1> %a)
+ ret i1 %b
+}
+
+define i1 @test_and_v7i1(<7 x i1> %a) nounwind {
+; CHECK-LABEL: @test_and_v7i1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <7 x i1> [[A:%.*]], <7 x i1> splat (i1 true), <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[TMP0]] to i8
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+entry:
+ %b = call i1 @llvm.vector.reduce.and.v7i1(<7 x i1> %a)
+ ret i1 %b
+}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
index b30c3ca188d5f..955e2af8dc178 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
@@ -244,13 +244,20 @@ define i1 @test_any_v7i1(<7 x i1> %x) {
; CHECK-LABEL: test_any_v7i1:
; CHECK: .functype test_any_v7i1 (i32, i32, i32, i32, i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.or $push0=, $0, $1
-; CHECK-NEXT: i32.or $push1=, $pop0, $2
-; CHECK-NEXT: i32.or $push2=, $pop1, $3
-; CHECK-NEXT: i32.or $push3=, $pop2, $4
-; CHECK-NEXT: i32.or $push4=, $pop3, $5
-; CHECK-NEXT: i32.or $push5=, $pop4, $6
-; CHECK-NEXT: return $pop5
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i16x8.replace_lane $push1=, $pop0, 0, $0
+; CHECK-NEXT: i16x8.replace_lane $push2=, $pop1, 1, $1
+; CHECK-NEXT: i16x8.replace_lane $push3=, $pop2, 2, $2
+; CHECK-NEXT: i16x8.replace_lane $push4=, $pop3, 3, $3
+; CHECK-NEXT: i16x8.replace_lane $push5=, $pop4, 4, $4
+; CHECK-NEXT: i16x8.replace_lane $push6=, $pop5, 5, $5
+; CHECK-NEXT: i16x8.replace_lane $push7=, $pop6, 6, $6
+; CHECK-NEXT: i32.const $push8=, 15
+; CHECK-NEXT: i16x8.shl $push9=, $pop7, $pop8
+; CHECK-NEXT: i32.const $push12=, 15
+; CHECK-NEXT: i16x8.shr_s $push10=, $pop9, $pop12
+; CHECK-NEXT: v128.any_true $push11=, $pop10
+; CHECK-NEXT: return $pop11
%ret = call i1 @llvm.vector.reduce.or.v7i1(<7 x i1> %x)
ret i1 %ret
}
@@ -259,13 +266,20 @@ define i1 @test_all_v7i1(<7 x i1> %x) {
; CHECK-LABEL: test_all_v7i1:
; CHECK: .functype test_all_v7i1 (i32, i32, i32, i32, i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.and $push0=, $0, $1
-; CHECK-NEXT: i32.and $push1=, $pop0, $2
-; CHECK-NEXT: i32.and $push2=, $pop1, $3
-; CHECK-NEXT: i32.and $push3=, $pop2, $4
-; CHECK-NEXT: i32.and $push4=, $pop3, $5
-; CHECK-NEXT: i32.and $push5=, $pop4, $6
-; CHECK-NEXT: return $pop5
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 65535
+; CHECK-NEXT: i16x8.replace_lane $push1=, $pop0, 0, $0
+; CHECK-NEXT: i16x8.replace_lane $push2=, $pop1, 1, $1
+; CHECK-NEXT: i16x8.replace_lane $push3=, $pop2, 2, $2
+; CHECK-NEXT: i16x8.replace_lane $push4=, $pop3, 3, $3
+; CHECK-NEXT: i16x8.replace_lane $push5=, $pop4, 4, $4
+; CHECK-NEXT: i16x8.replace_lane $push6=, $pop5, 5, $5
+; CHECK-NEXT: i16x8.replace_lane $push7=, $pop6, 6, $6
+; CHECK-NEXT: i32.const $push8=, 15
+; CHECK-NEXT: i16x8.shl $push9=, $pop7, $pop8
+; CHECK-NEXT: i32.const $push12=, 15
+; CHECK-NEXT: i16x8.shr_s $push10=, $pop9, $pop12
+; CHECK-NEXT: i16x8.all_true $push11=, $pop10
+; CHECK-NEXT: return $pop11
%ret = call i1 @llvm.vector.reduce.and.v7i1(<7 x i1> %x)
ret i1 %ret
}
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index 15a349827dfd8..2dabbf965c635 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -2074,43 +2074,26 @@ define zeroext i1 @PR44781(ptr %0) {
define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; X86-SSE2-LABEL: mask_v3i1:
; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: pushl %ebp
-; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
-; X86-SSE2-NEXT: .cfi_offset %ebp, -8
-; X86-SSE2-NEXT: movl %esp, %ebp
-; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
-; X86-SSE2-NEXT: andl $-16, %esp
-; X86-SSE2-NEXT: subl $32, %esp
; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
-; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
-; X86-SSE2-NEXT: pxor %xmm0, %xmm1
-; X86-SSE2-NEXT: movdqa %xmm1, (%esp)
-; X86-SSE2-NEXT: movzbl (%esp), %eax
-; X86-SSE2-NEXT: orb {{[0-9]+}}(%esp), %al
-; X86-SSE2-NEXT: orb {{[0-9]+}}(%esp), %al
-; X86-SSE2-NEXT: testb $1, %al
-; X86-SSE2-NEXT: je .LBB30_3
+; X86-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-SSE2-NEXT: pslld $31, %xmm0
+; X86-SSE2-NEXT: movmskps %xmm0, %eax
+; X86-SSE2-NEXT: testl %eax, %eax
+; X86-SSE2-NEXT: je .LBB30_2
; X86-SSE2-NEXT: # %bb.1:
; X86-SSE2-NEXT: xorl %eax, %eax
-; X86-SSE2-NEXT: jmp .LBB30_2
-; X86-SSE2-NEXT: .LBB30_3:
-; X86-SSE2-NEXT: movl $1, %eax
+; X86-SSE2-NEXT: retl
; X86-SSE2-NEXT: .LBB30_2:
-; X86-SSE2-NEXT: movl %ebp, %esp
-; X86-SSE2-NEXT: popl %ebp
-; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
+; X86-SSE2-NEXT: movl $1, %eax
; X86-SSE2-NEXT: retl
;
; X64-SSE2-LABEL: mask_v3i1:
; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
-; X64-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
-; X64-SSE2-NEXT: pxor %xmm0, %xmm1
-; X64-SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)
-; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; X64-SSE2-NEXT: orb -{{[0-9]+}}(%rsp), %al
-; X64-SSE2-NEXT: orb -{{[0-9]+}}(%rsp), %al
-; X64-SSE2-NEXT: testb $1, %al
+; X64-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-SSE2-NEXT: pslld $31, %xmm0
+; X64-SSE2-NEXT: movmskps %xmm0, %eax
+; X64-SSE2-NEXT: testl %eax, %eax
; X64-SSE2-NEXT: je .LBB30_2
; X64-SSE2-NEXT: # %bb.1:
; X64-SSE2-NEXT: xorl %eax, %eax
@@ -2124,12 +2107,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; SSE4-NEXT: pcmpeqd %xmm1, %xmm0
; SSE4-NEXT: pcmpeqd %xmm1, %xmm1
; SSE4-NEXT: pxor %xmm0, %xmm1
-; SSE4-NEXT: movd %xmm1, %eax
-; SSE4-NEXT: pextrb $4, %xmm1, %ecx
-; SSE4-NEXT: orl %eax, %ecx
-; SSE4-NEXT: pextrb $8, %xmm1, %eax
-; SSE4-NEXT: orl %ecx, %eax
-; SSE4-NEXT: testb $1, %al
+; SSE4-NEXT: pxor %xmm0, %xmm0
+; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5,6,7]
+; SSE4-NEXT: pslld $31, %xmm0
+; SSE4-NEXT: movmskps %xmm0, %eax
+; SSE4-NEXT: testl %eax, %eax
; SSE4-NEXT: je .LBB30_2
; SSE4-NEXT: # %bb.1:
; SSE4-NEXT: xorl %eax, %eax
@@ -2143,12 +2125,10 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX1OR2-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX1OR2-NEXT: vmovd %xmm0, %eax
-; AVX1OR2-NEXT: vpextrb $4, %xmm0, %ecx
-; AVX1OR2-NEXT: orl %eax, %ecx
-; AVX1OR2-NEXT: vpextrb $8, %xmm0, %eax
-; AVX1OR2-NEXT: orl %ecx, %eax
-; AVX1OR2-NEXT: testb $1, %al
+; AVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX1OR2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5,6,7]
+; AVX1OR2-NEXT: vpslld $31, %xmm0, %xmm0
+; AVX1OR2-NEXT: vtestps %xmm0, %xmm0
; AVX1OR2-NEXT: je .LBB30_2
; AVX1OR2-NEXT: # %bb.1:
; AVX1OR2-NEXT: xorl %eax, %eax
@@ -2161,15 +2141,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vpcmpneqd %zmm1, %zmm0, %k0
-; AVX512F-NEXT: kshiftrw $2, %k0, %k1
-; AVX512F-NEXT: kmovw %k1, %eax
-; AVX512F-NEXT: kshiftrw $1, %k0, %k1
-; AVX512F-NEXT: kmovw %k1, %ecx
-; AVX512F-NEXT: kmovw %k0, %edx
-; AVX512F-NEXT: orb %cl, %dl
-; AVX512F-NEXT: orb %al, %dl
-; AVX512F-NEXT: testb $1, %dl
+; AVX512F-NEXT: movb $7, %al
+; AVX512F-NEXT: kmovw %eax, %k1
+; AVX512F-NEXT: vpcmpneqd %zmm1, %zmm0, %k0 {%k1}
+; AVX512F-NEXT: kmovw %k0, %eax
+; AVX512F-NEXT: testb $7, %al
; AVX512F-NEXT: je .LBB30_2
; AVX512F-NEXT: # %bb.1:
; AVX512F-NEXT: xorl %eax, %eax
@@ -2184,15 +2160,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512BW-NEXT: vpcmpneqd %zmm1, %zmm0, %k0
-; AVX512BW-NEXT: kshiftrw $2, %k0, %k1
-; AVX512BW-NEXT: kmovd %k1, %eax
-; AVX512BW-NEXT: kshiftrw $1, %k0, %k1
-; AVX512BW-NEXT: kmovd %k1, %ecx
-; AVX512BW-NEXT: kmovd %k0, %edx
-; AVX512BW-NEXT: orb %cl, %dl
-; AVX512BW-NEXT: orb %al, %dl
-; AVX512BW-NEXT: testb $1, %dl
+; AVX512BW-NEXT: movb $7, %al
+; AVX512BW-NEXT: kmovd %eax, %k1
+; AVX512BW-NEXT: vpcmpneqd %zmm1, %zmm0, %k0 {%k1}
+; AVX512BW-NEXT: kmovd %k0, %eax
+; AVX512BW-NEXT: testb $7, %al
; AVX512BW-NEXT: je .LBB30_2
; AVX512BW-NEXT: # %bb.1:
; AVX512BW-NEXT: xorl %eax, %eax
@@ -2205,15 +2177,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
;
; AVX512VL-LABEL: mask_v3i1:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vpcmpneqd %xmm1, %xmm0, %k0
-; AVX512VL-NEXT: kshiftrb $2, %k0, %k1
-; AVX512VL-NEXT: kmovd %k1, %eax
-; AVX512VL-NEXT: kshiftrb $1, %k0, %k1
-; AVX512VL-NEXT: kmovd %k1, %ecx
-; AVX512VL-NEXT: kmovd %k0, %edx
-; AVX512VL-NEXT: orb %cl, %dl
-; AVX512VL-NEXT: orb %al, %dl
-; AVX512VL-NEXT: testb $1, %dl
+; AVX512VL-NEXT: movb $7, %al
+; AVX512VL-NEXT: kmovd %eax, %k1
+; AVX512VL-NEXT: vpcmpneqd %xmm1, %xmm0, %k0 {%k1}
+; AVX512VL-NEXT: kmovd %k0, %eax
+; AVX512VL-NEXT: testb $7, %al
; AVX512VL-NEXT: je .LBB30_2
; AVX512VL-NEXT: # %bb.1:
; AVX512VL-NEXT: xorl %eax, %eax
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