[llvm] [SLPVectorizer] Extract overlapping scalar load from vector load (PR #213426)

[Akshay K via llvm-commits]

kumarak wrote:

@alexey-bataev Thanks for taking a look. I am still getting familiar with the SLP cost model and will appreciate your feedback.

I am looking into the missed-optimization case described in issue #205978. The scalar load is causing a reload from memory under register pressure, even though both loads fall on the same chain and there are no stores in between.

```asm
     ; kept scalar load
     cmovnel  d+24(%rip), %edx      ; reload from memory
     ; value taken from the vector load
     cmovnel  %esi, %edx            ; register
```

It seems the cost model for lower extract and scalar load is the same on x86 targets. For different targets, like ARM/AArch64, it will be more. I would like to get your suggestions on two different possible solutions.

1. Would it make sense to keep it in the SLP and only drop the scalar when the extract is no more expensive than the load? I can push a follow-up commit for your review.

2. Do you suggest cleaning it up in the later passes, like DAGCombine? I had a PR related to it, but there are specific challenges in handling it there.


> This is wrong. The decision to keep the load is chosen based on the cost model, so it is expected behavior

https://github.com/llvm/llvm-project/pull/213426