[llvm] 460c1d3 - [NFC][PowerPC] add `ppcf128` tests for fneg and nofpclass (#213307)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 11:52:14 PDT 2026
Author: Folkert de Vries
Date: 2026-07-31T20:52:08+02:00
New Revision: 460c1d327baaa10c2e237418f661084fb33b72e9
URL: https://github.com/llvm/llvm-project/commit/460c1d327baaa10c2e237418f661084fb33b72e9
DIFF: https://github.com/llvm/llvm-project/commit/460c1d327baaa10c2e237418f661084fb33b72e9.diff
LOG: [NFC][PowerPC] add `ppcf128` tests for fneg and nofpclass (#213307)
Added:
Modified:
llvm/test/CodeGen/PowerPC/fneg.ll
llvm/test/CodeGen/PowerPC/nofpclass.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/fneg.ll b/llvm/test/CodeGen/PowerPC/fneg.ll
index 26cfa1e82c694..191594ab72316 100644
--- a/llvm/test/CodeGen/PowerPC/fneg.ll
+++ b/llvm/test/CodeGen/PowerPC/fneg.ll
@@ -1,13 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -ppc-asm-full-reg-names | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=BE32
define double @test1(double %a, double %b, double %c, double %d) {
-; CHECK-LABEL: test1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fmul f0, f3, f4
-; CHECK-NEXT: fmul f1, f1, f2
-; CHECK-NEXT: fadd f1, f1, f0
-; CHECK-NEXT: blr
+; LE-LABEL: test1:
+; LE: # %bb.0:
+; LE-NEXT: xsmuldp 0, 3, 4
+; LE-NEXT: xsmuldp 1, 1, 2
+; LE-NEXT: xsadddp 1, 1, 0
+; LE-NEXT: blr
+;
+; BE-LABEL: test1:
+; BE: # %bb.0:
+; BE-NEXT: fmul 0, 3, 4
+; BE-NEXT: fmul 1, 1, 2
+; BE-NEXT: fadd 1, 1, 0
+; BE-NEXT: blr
+;
+; BE32-LABEL: test1:
+; BE32: # %bb.0:
+; BE32-NEXT: fmul f0, f3, f4
+; BE32-NEXT: fmul f1, f1, f2
+; BE32-NEXT: fadd f1, f1, f0
+; BE32-NEXT: blr
%tmp2 = fsub double -0.000000e+00, %c
%tmp4 = fmul double %tmp2, %d
%tmp7 = fmul double %a, %b
@@ -18,10 +34,21 @@ define double @test1(double %a, double %b, double %c, double %d) {
declare float @llvm.fmuladd.f32(float, float, float) #4
define float @fma_fneg_fneg(float %x, float %y, float %z) {
-; CHECK-LABEL: fma_fneg_fneg:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fmadds f1, f1, f2, f3
-; CHECK-NEXT: blr
+; LE-LABEL: fma_fneg_fneg:
+; LE: # %bb.0:
+; LE-NEXT: xsmaddasp 3, 1, 2
+; LE-NEXT: fmr 1, 3
+; LE-NEXT: blr
+;
+; BE-LABEL: fma_fneg_fneg:
+; BE: # %bb.0:
+; BE-NEXT: fmadds 1, 1, 2, 3
+; BE-NEXT: blr
+;
+; BE32-LABEL: fma_fneg_fneg:
+; BE32: # %bb.0:
+; BE32-NEXT: fmadds f1, f1, f2, f3
+; BE32-NEXT: blr
%negx = fneg float %x
%negy = fneg float %y
%r = call float @llvm.fmuladd.f32(float %negx, float %negy, float %z)
@@ -29,11 +56,24 @@ define float @fma_fneg_fneg(float %x, float %y, float %z) {
}
define float @fma_fneg_fsub(float %x, float %y0, float %y1, float %z) {
-; CHECK-LABEL: fma_fneg_fsub:
-; CHECK: # %bb.0:
-; CHECK-NEXT: fsubs f0, f3, f2
-; CHECK-NEXT: fmadds f1, f1, f0, f4
-; CHECK-NEXT: blr
+; LE-LABEL: fma_fneg_fsub:
+; LE: # %bb.0:
+; LE-NEXT: xssubsp 0, 3, 2
+; LE-NEXT: xsmaddasp 4, 1, 0
+; LE-NEXT: fmr 1, 4
+; LE-NEXT: blr
+;
+; BE-LABEL: fma_fneg_fsub:
+; BE: # %bb.0:
+; BE-NEXT: fsubs 0, 3, 2
+; BE-NEXT: fmadds 1, 1, 0, 4
+; BE-NEXT: blr
+;
+; BE32-LABEL: fma_fneg_fsub:
+; BE32: # %bb.0:
+; BE32-NEXT: fsubs f0, f3, f2
+; BE32-NEXT: fmadds f1, f1, f0, f4
+; BE32-NEXT: blr
%negx = fneg float %x
%negy = fsub nsz float %y0, %y1
%r = call float @llvm.fmuladd.f32(float %negx, float %negy, float %z)
@@ -42,14 +82,32 @@ define float @fma_fneg_fsub(float %x, float %y0, float %y1, float %z) {
; Verify that we didn't hit assertion for this case.
define double @fneg_no_ice(float %x) {
-; CHECK-LABEL: fneg_no_ice:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lis r3, .LCPI3_0 at ha
-; CHECK-NEXT: lfs f0, .LCPI3_0 at l(r3)
-; CHECK-NEXT: fsubs f0, f0, f1
-; CHECK-NEXT: fmul f1, f0, f0
-; CHECK-NEXT: fmul f1, f0, f1
-; CHECK-NEXT: blr
+; LE-LABEL: fneg_no_ice:
+; LE: # %bb.0:
+; LE-NEXT: vspltisw 2, 1
+; LE-NEXT: xvcvsxwdp 0, 34
+; LE-NEXT: xssubsp 0, 0, 1
+; LE-NEXT: xsmuldp 1, 0, 0
+; LE-NEXT: xsmuldp 1, 0, 1
+; LE-NEXT: blr
+;
+; BE-LABEL: fneg_no_ice:
+; BE: # %bb.0:
+; BE-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; BE-NEXT: lfs 0, .LCPI3_0 at toc@l(3)
+; BE-NEXT: fsubs 0, 0, 1
+; BE-NEXT: fmul 1, 0, 0
+; BE-NEXT: fmul 1, 0, 1
+; BE-NEXT: blr
+;
+; BE32-LABEL: fneg_no_ice:
+; BE32: # %bb.0:
+; BE32-NEXT: lis r3, .LCPI3_0 at ha
+; BE32-NEXT: lfs f0, .LCPI3_0 at l(r3)
+; BE32-NEXT: fsubs f0, f0, f1
+; BE32-NEXT: fmul f1, f0, f0
+; BE32-NEXT: fmul f1, f0, f1
+; BE32-NEXT: blr
%y = fsub fast float 1.0, %x
%e = fpext float %y to double
%e2 = fmul double %e, %e
@@ -58,14 +116,115 @@ define double @fneg_no_ice(float %x) {
}
define double @fneg_fmul_const(double %x) {
-; CHECK-LABEL: fneg_fmul_const:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lis r3, .LCPI4_0 at ha
-; CHECK-NEXT: lfd f0, .LCPI4_0 at l(r3)
-; CHECK-NEXT: fmul f1, f1, f0
-; CHECK-NEXT: blr
+; LE-LABEL: fneg_fmul_const:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; LE-NEXT: lfd 0, .LCPI4_0 at toc@l(3)
+; LE-NEXT: xsmuldp 1, 1, 0
+; LE-NEXT: blr
+;
+; BE-LABEL: fneg_fmul_const:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; BE-NEXT: lfd 0, .LCPI4_0 at toc@l(3)
+; BE-NEXT: fmul 1, 1, 0
+; BE-NEXT: blr
+;
+; BE32-LABEL: fneg_fmul_const:
+; BE32: # %bb.0: # %entry
+; BE32-NEXT: lis r3, .LCPI4_0 at ha
+; BE32-NEXT: lfd f0, .LCPI4_0 at l(r3)
+; BE32-NEXT: fmul f1, f1, f0
+; BE32-NEXT: blr
entry:
%f = fmul double %x, 1.2345
%s = fneg double %f
ret double %s
}
+
+define i1 @fneg_msb(ppc_fp128 nofpclass(nan ninf nsub nnorm nzero) %x) {
+; LE-LABEL: fneg_msb:
+; LE: # %bb.0: # %entry
+; LE-NEXT: li 3, 1
+; LE-NEXT: blr
+;
+; BE-LABEL: fneg_msb:
+; BE: # %bb.0: # %entry
+; BE-NEXT: li 3, 1
+; BE-NEXT: blr
+;
+; BE32-LABEL: fneg_msb:
+; BE32: # %bb.0: # %entry
+; BE32-NEXT: li r3, 1
+; BE32-NEXT: blr
+entry:
+ %neg = fneg ppc_fp128 %x
+ %v = bitcast ppc_fp128 %neg to i128
+ %cmp = icmp slt i128 %v, 0
+ ret i1 %cmp
+}
+
+define i1 @fneg_bit63(ppc_fp128 nofpclass(nan ninf nsub nnorm nzero) %x) {
+; LE-LABEL: fneg_bit63:
+; LE: # %bb.0: # %entry
+; LE-NEXT: mffprd 3, 1
+; LE-NEXT: rldicl 3, 3, 1, 63
+; LE-NEXT: blr
+;
+; BE-LABEL: fneg_bit63:
+; BE: # %bb.0: # %entry
+; BE-NEXT: stfd 2, -8(1)
+; BE-NEXT: ld 3, -8(1)
+; BE-NEXT: not 3, 3
+; BE-NEXT: rldicl 3, 3, 1, 63
+; BE-NEXT: blr
+;
+; BE32-LABEL: fneg_bit63:
+; BE32: # %bb.0: # %entry
+; BE32-NEXT: stwu r1, -32(r1)
+; BE32-NEXT: .cfi_def_cfa_offset 32
+; BE32-NEXT: stfd f2, 16(r1)
+; BE32-NEXT: lwz r3, 16(r1)
+; BE32-NEXT: not r3, r3
+; BE32-NEXT: srwi r3, r3, 31
+; BE32-NEXT: addi r1, r1, 32
+; BE32-NEXT: blr
+entry:
+ %neg = fneg ppc_fp128 %x
+ %v = bitcast ppc_fp128 %neg to i128
+ %masked = and i128 %v, 9223372036854775808 ; 1 << 63
+ %cmp = icmp ne i128 %masked, 0
+ ret i1 %cmp
+}
+
+define i1 @fneg_fneg_msb(ppc_fp128 nofpclass(nan ninf nsub nnorm nzero) %x) {
+; LE-LABEL: fneg_fneg_msb:
+; LE: # %bb.0: # %entry
+; LE-NEXT: mffprd 3, 1
+; LE-NEXT: rldicl 3, 3, 1, 63
+; LE-NEXT: blr
+;
+; BE-LABEL: fneg_fneg_msb:
+; BE: # %bb.0: # %entry
+; BE-NEXT: stfd 2, -8(1)
+; BE-NEXT: ld 3, -8(1)
+; BE-NEXT: rldicl 3, 3, 1, 63
+; BE-NEXT: blr
+;
+; BE32-LABEL: fneg_fneg_msb:
+; BE32: # %bb.0: # %entry
+; BE32-NEXT: stwu r1, -32(r1)
+; BE32-NEXT: .cfi_def_cfa_offset 32
+; BE32-NEXT: stfd f2, 16(r1)
+; BE32-NEXT: lwz r3, 16(r1)
+; BE32-NEXT: srwi r3, r3, 31
+; BE32-NEXT: addi r1, r1, 32
+; BE32-NEXT: blr
+entry:
+ %neg = fneg ppc_fp128 %x
+ %neg2 = fneg ppc_fp128 %neg
+ %v = bitcast ppc_fp128 %neg2 to i128
+ %masked = and i128 %v, 9223372036854775808 ; 1 << 63
+ %cmp = icmp ne i128 %masked, 0
+ ret i1 %cmp
+}
diff --git a/llvm/test/CodeGen/PowerPC/nofpclass.ll b/llvm/test/CodeGen/PowerPC/nofpclass.ll
index b08e810cd1cca..6d447f09b1b3e 100644
--- a/llvm/test/CodeGen/PowerPC/nofpclass.ll
+++ b/llvm/test/CodeGen/PowerPC/nofpclass.ll
@@ -1,15 +1,57 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
-; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=BE32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s -check-prefix=AIX
-; TODO: Update this test after adding the proper expansion of nofpclass for
-; ppc_fp128 to test with more masks and to demonstrate preserving nofpclass
-; after legalization.
+define i1 @negative(ppc_fp128 nofpclass(nan pinf psub pnorm pzero) %x) {
+; LE-LABEL: negative:
+; LE: # %bb.0: # %entry
+; LE-NEXT: li 3, 1
+; LE-NEXT: blr
+;
+; BE-LABEL: negative:
+; BE: # %bb.0: # %entry
+; BE-NEXT: li 3, 1
+; BE-NEXT: blr
+;
+; BE32-LABEL: negative:
+; BE32: # %bb.0: # %entry
+; BE32-NEXT: li 3, 1
+; BE32-NEXT: blr
+;
+; AIX-LABEL: negative:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: li 3, 1
+; AIX-NEXT: blr
+entry:
+ %v = bitcast ppc_fp128 %x to i128
+ %cmp = icmp slt i128 %v, 0
+ ret i1 %cmp
+}
-define ppc_fp128 @f(ppc_fp128 nofpclass(nan) %s) {
-; CHECK-LABEL: f:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: blr
+define i1 @nonnegative(ppc_fp128 nofpclass(nan ninf nsub nnorm nzero) %x) {
+; LE-LABEL: nonnegative:
+; LE: # %bb.0: # %entry
+; LE-NEXT: li 3, 0
+; LE-NEXT: blr
+;
+; BE-LABEL: nonnegative:
+; BE: # %bb.0: # %entry
+; BE-NEXT: li 3, 0
+; BE-NEXT: blr
+;
+; BE32-LABEL: nonnegative:
+; BE32: # %bb.0: # %entry
+; BE32-NEXT: li 3, 0
+; BE32-NEXT: blr
+;
+; AIX-LABEL: nonnegative:
+; AIX: # %bb.0: # %entry
+; AIX-NEXT: li 3, 0
+; AIX-NEXT: blr
entry:
- ret ppc_fp128 %s
+ %v = bitcast ppc_fp128 %x to i128
+ %cmp = icmp slt i128 %v, 0
+ ret i1 %cmp
}
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