[llvm] [AMDGPU] Analyze REG_SEQUENCE To Remove Redundant CMP Instructions (PR #167364)

[Patrick Simmons via llvm-commits]

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@@ -1313,6 +1313,34 @@ Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,
   return Reg;
 }
 
+MachineInstr *
+SIInstrInfo::pierceThroughRegSequence(const MachineInstr &MI) const {
+  if (MI.getOpcode() != AMDGPU::REG_SEQUENCE || MI.getNumOperands() != 5)
+    return nullptr;
+
+  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+  int64_t SubRegValues[2];
+  bool SubRegIsConst[2];
+  MachineInstr *RealDefs[2];
+  for (unsigned I : {2, 4}) {
+    unsigned ArrayIdx = MI.getOperand(I).getImm() == AMDGPU::sub0 ? 0 : 1;
+    Register Subreg = MI.getOperand(I - 1).getReg();
+    RealDefs[ArrayIdx] = MRI.getUniqueVRegDef(Subreg);
+    SubRegIsConst[ArrayIdx] = getConstValDefinedInReg(
+        *RealDefs[ArrayIdx], Subreg, SubRegValues[ArrayIdx]);
+  }
+
+  for (unsigned I : {0, 1})
+    if (SubRegIsConst[I] && !SubRegValues[I] &&
+        MRI.getRegClass(RealDefs[(I + 1) % 2]->getOperand(0).getReg())
+                    ->MC->getSizeInBits() *
+                2 ==
+            MRI.getRegClass(MI.getOperand(0).getReg())->MC->getSizeInBits())
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linuxrocks123 wrote:

@arsenm I don't think you're right about that, because, if you were, the assert in `foldVGPRCopyIntoRegSequence` in `llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp` would be invalid.  That assert will fire if a REG_SEQUENCE with an SGPR destination register does not also have SGPR sources.

Would you like me to put a similar assert in here?

https://github.com/llvm/llvm-project/pull/167364