[llvm] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 3) (PR #213135)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 09:29:08 PDT 2026
https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/213135
>From a86111a08544cc6f2b192a2a7a2517f29bc313e8 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Thu, 30 Jul 2026 14:26:32 -0400
Subject: [PATCH] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs
(part 3)
Migrate trigonometric, division, remainder, multiply-add, and min/max
opcodes to extended floating-point LLTs.
Remove redundant scalar clamps that request unsupported f128-to-f64
narrowing, while retaining required f16-to-f32 widening.
Also update the relevant MIR tests.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 94 +-
.../AMDGPU/GlobalISel/legalize-fcos.mir | 766 +++---
.../AMDGPU/GlobalISel/legalize-fdiv.mir | 2288 ++++++++---------
.../AMDGPU/GlobalISel/legalize-fmad.s16.mir | 1558 +++++------
.../AMDGPU/GlobalISel/legalize-fmad.s32.mir | 908 +++----
.../AMDGPU/GlobalISel/legalize-fmad.s64.mir | 104 +-
.../AMDGPU/GlobalISel/legalize-fmaximum.mir | 294 +--
.../AMDGPU/GlobalISel/legalize-fmaxnum.mir | 1218 ++++-----
.../AMDGPU/GlobalISel/legalize-fminimum.mir | 294 +--
.../AMDGPU/GlobalISel/legalize-fminnum.mir | 1218 ++++-----
.../AMDGPU/GlobalISel/legalize-fsin.mir | 766 +++---
11 files changed, 4761 insertions(+), 4747 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6bf05f9808d78..f8f8395c1abac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -736,8 +736,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
S32, S64, S16, V2S16
};
- const std::initializer_list<LLT> FPTypesPK16_64 = {S32, S64, S16, V2S16,
- V2S64};
+ const std::initializer_list<LLT> ExtendedFPTypesBase = {F32, F64};
+ const std::initializer_list<LLT> ExtendedFPTypes16 = {F32, F64, F16};
+ const std::initializer_list<LLT> ExtendedFPTypesPK16 = {F32, F64, F16, V2F16};
+ const std::initializer_list<LLT> ExtendedFPTypesPK16_64 = {F32, F64, F16,
+ V2F16, V2F64};
const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32;
const LLT MinExtendedFPTy = ST.has16BitInsts() ? F16 : F32;
@@ -989,10 +992,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder({G_FADD, G_FMUL, G_FMA, G_FCANONICALIZE,
G_STRICT_FADD, G_STRICT_FMUL, G_STRICT_FMA})
.legalFor({F32, F64});
- auto &TrigActions = getActionDefinitionsBuilder({G_FSIN, G_FCOS})
- .customFor({S32, S64});
- auto &FDIVActions = getActionDefinitionsBuilder(G_FDIV)
- .customFor({S32, S64});
+ auto &TrigActions =
+ getActionDefinitionsBuilder({G_FSIN, G_FCOS}).customFor({F32, F64});
+ auto &FDIVActions = getActionDefinitionsBuilder(G_FDIV).customFor({F32, F64});
if (ST.has16BitInsts()) {
if (ST.hasVOP3PInsts())
@@ -1000,8 +1002,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
else
FPOpActions.legalFor({F16});
- TrigActions.customFor({S16});
- FDIVActions.customFor({S16});
+ TrigActions.customFor({F16});
+ FDIVActions.customFor({F16});
}
if (ST.hasAnyPackedFP32Ops()) {
@@ -1023,59 +1025,52 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder({G_FMINNUM_IEEE, G_FMAXNUM_IEEE});
if (ST.hasVOP3PInsts()) {
- MinNumMaxNumIeee.legalFor(FPTypesPK16)
+ MinNumMaxNumIeee.legalFor(ExtendedFPTypesPK16)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampScalar(0, S16, S64)
+ .clampMaxNumElements(0, F16, 2)
.scalarize(0);
} else if (ST.has16BitInsts()) {
- MinNumMaxNumIeee.legalFor(FPTypes16).clampScalar(0, S16, S64).scalarize(0);
+ MinNumMaxNumIeee.legalFor(ExtendedFPTypes16).scalarize(0);
} else {
- MinNumMaxNumIeee.legalFor(FPTypesBase)
- .clampScalar(0, S32, S64)
- .scalarize(0);
+ MinNumMaxNumIeee.legalFor(ExtendedFPTypesBase).scalarize(0);
}
auto &MinNumMaxNum = getActionDefinitionsBuilder(
{G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM});
if (ST.hasAnyPackedFP64Ops()) {
- MinNumMaxNum.customFor(FPTypesPK16_64)
+ MinNumMaxNum.customFor(ExtendedFPTypesPK16_64)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampMaxNumElements(0, S64, 2)
- .clampScalar(0, S16, S64)
+ .clampMaxNumElements(0, F16, 2)
+ .clampMaxNumElements(0, F64, 2)
.scalarize(0);
} else if (ST.hasVOP3PInsts()) {
- MinNumMaxNum.customFor(FPTypesPK16)
- .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampScalar(0, S16, S64)
- .scalarize(0);
+ MinNumMaxNum.customFor(ExtendedFPTypesPK16)
+ .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
+ .clampMaxNumElements(0, F16, 2)
+ .scalarize(0);
} else if (ST.has16BitInsts()) {
- MinNumMaxNum.customFor(FPTypes16)
- .clampScalar(0, S16, S64)
- .scalarize(0);
+ MinNumMaxNum.customFor(ExtendedFPTypes16).scalarize(0);
} else {
- MinNumMaxNum.customFor(FPTypesBase)
- .clampScalar(0, S32, S64)
- .scalarize(0);
+ MinNumMaxNum.customFor(ExtendedFPTypesBase).scalarize(0);
+ }
+
+ if (!ST.has16BitInsts()) {
+ MinNumMaxNumIeee.minScalar(0, F32);
+ MinNumMaxNum.minScalar(0, F32);
}
if (ST.hasVOP3PInsts())
FPOpActions.clampMaxNumElementsStrict(0, F16, 2);
FPOpActions.scalarize(0);
- if (!ST.has16BitInsts())
+ TrigActions.scalarize(0);
+ FDIVActions.scalarize(0);
+ if (!ST.has16BitInsts()) {
FPOpActions.minScalar(0, F32);
-
- TrigActions
- .scalarize(0)
- .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
-
- FDIVActions
- .scalarize(0)
- .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
+ TrigActions.minScalar(0, F32);
+ FDIVActions.minScalar(0, F32);
+ }
auto &FNegAbs = getActionDefinitionsBuilder({G_FNEG, G_FABS});
FNegAbs.legalFor(FPTypesPK16)
@@ -1191,20 +1186,19 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// Whether this is legal depends on the floating point mode for the function.
auto &FMad = getActionDefinitionsBuilder(G_FMAD);
if (ST.hasMadF16() && ST.hasMadMacF32Insts())
- FMad.customFor({S32, S16});
+ FMad.customFor({F32, F16});
else if (ST.hasMadMacF32Insts())
- FMad.customFor({S32});
+ FMad.customFor({F32});
else if (ST.hasMadF16())
- FMad.customFor({S16});
+ FMad.customFor({F16});
FMad.scalarize(0)
.lower();
auto &FRem = getActionDefinitionsBuilder(G_FREM);
if (ST.has16BitInsts()) {
- FRem.customFor({S16, S32, S64});
+ FRem.customFor({F16, F32, F64});
} else {
- FRem.minScalar(0, S32)
- .customFor({S32, S64});
+ FRem.minScalar(0, F32).customFor({F32, F64});
}
FRem.scalarize(0);
@@ -2270,19 +2264,19 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.hasIEEEMinimumMaximumInsts()) {
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
- .legalFor(FPTypesPK16)
- .clampMaxNumElements(0, S16, 2)
+ .legalFor(ExtendedFPTypesPK16)
+ .clampMaxNumElements(0, F16, 2)
.scalarize(0);
} else if (ST.hasVOP3PInsts()) {
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
- .lowerFor({V2S16})
- .clampMaxNumElementsStrict(0, S16, 2)
+ .lowerFor({V2F16})
+ .clampMaxNumElementsStrict(0, F16, 2)
.scalarize(0)
.lower();
} else {
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
.scalarize(0)
- .clampScalar(0, S32, S64)
+ .clampScalar(0, F32, F64)
.lower();
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
index 1970f01423c48..d33766b79f38a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
@@ -14,33 +14,33 @@ body: |
; SI-LABEL: name: test_fcos_s32
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; VI-LABEL: name: test_fcos_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; GFX9-LABEL: name: test_fcos_s32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCOS %0
$vgpr0 = COPY %1
...
@@ -53,33 +53,33 @@ body: |
; SI-LABEL: name: test_fcos_s64
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](f64)
;
; VI-LABEL: name: test_fcos_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](f64)
;
; GFX9-LABEL: name: test_fcos_s64
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FCOS %0
$vgpr0_vgpr1 = COPY %1
...
---
@@ -91,43 +91,43 @@ body: |
; SI-LABEL: name: test_fcos_s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fcos_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fcos_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FCOS %1
- %3:_(s32) = G_ANYEXT %2
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f16) = G_TRUNC %0
+ %2:_(f16) = G_FCOS %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -140,47 +140,47 @@ body: |
; SI-LABEL: name: test_fcos_v2s32
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fcos_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fcos_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT]](s32), [[INT1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f32)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT]](f32), [[INT1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FCOS %0
$vgpr0_vgpr1 = COPY %1
...
@@ -193,55 +193,55 @@ body: |
; SI-LABEL: name: test_fcos_v3s32
; SI: liveins: $vgpr0_vgpr1_vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; SI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; SI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]](s32)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32), [[INT5]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; VI-LABEL: name: test_fcos_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; VI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]](s32)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32), [[INT5]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; GFX9-LABEL: name: test_fcos_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](s32)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL2]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT]](s32), [[INT1]](s32), [[INT2]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f32)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](f32)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL2]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT]](f32), [[INT1]](f32), [[INT2]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FCOS %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
@@ -254,47 +254,47 @@ body: |
; SI-LABEL: name: test_fcos_v2s64
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s64)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s64)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT1]](s64), [[INT3]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f64)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f64)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f64)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT1]](f64), [[INT3]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; VI-LABEL: name: test_fcos_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s64)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s64)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT1]](s64), [[INT3]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f64)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f64)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f64)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT1]](f64), [[INT3]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; GFX9-LABEL: name: test_fcos_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s64)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](s64)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT]](s64), [[INT1]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f64)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](f64)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT]](f64), [[INT1]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = G_FCOS %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -307,71 +307,71 @@ body: |
; SI-LABEL: name: test_fcos_v2s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT1]], [[C1]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C1]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C1]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT3]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; VI-LABEL: name: test_fcos_v2s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s16)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s16)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](s16)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f16)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f16)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; GFX9-LABEL: name: test_fcos_v2s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT]](s16), [[INT1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FCOS %0
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f16)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT]](f16), [[INT1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FCOS %0
$vgpr0 = COPY %1
...
@@ -381,64 +381,64 @@ body: |
bb.0:
; SI-LABEL: name: test_fcos_v3s16
- ; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT3]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT2]], [[C]]
- ; SI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; SI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](s32)
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT5]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
- ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; SI: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT3]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[C]]
+ ; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](f32)
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT5]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC1]](f16)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; VI-LABEL: name: test_fcos_v3s16
- ; VI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s16)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s16)
- ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; VI-NEXT: [[INT4:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s16)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT3]](s16)
- ; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT5]](s16)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; VI: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f16)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f16)
+ ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; VI-NEXT: [[INT4:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f16)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT3]](f16)
+ ; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT5]](f16)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; GFX9-LABEL: name: test_fcos_v3s16
- ; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](s16)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL2]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT2]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s16>) = G_IMPLICIT_DEF
- %1:_(<3 x s16>) = G_FCOS %0
- %2:_(<3 x s32>) = G_ANYEXT %1
+ ; GFX9: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f16)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](f16)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL2]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT2]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
+ %0:_(<3 x f16>) = G_IMPLICIT_DEF
+ %1:_(<3 x f16>) = G_FCOS %0
+ %2:_(<3 x i32>) = G_ANYEXT %1
S_NOP 0, implicit %2
...
@@ -451,120 +451,120 @@ body: |
; SI-LABEL: name: test_fcos_v4s16
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT1]], [[C1]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT3]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT2]], [[C1]]
- ; SI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; SI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](s32)
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT5]](s32)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT3]], [[C1]]
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](s32)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT6]](s32)
- ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT7]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C1]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C1]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT3]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[C1]]
+ ; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](f32)
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT5]](f32)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT3]], [[C1]]
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](f32)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT6]](f32)
+ ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT7]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; VI-LABEL: name: test_fcos_v4s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s16)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s16)
- ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[C1]]
- ; VI-NEXT: [[INT4:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s16)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](s16)
- ; VI-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[C1]]
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](s16)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT6]](s16)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](s16)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f16)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f16)
+ ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[C1]]
+ ; VI-NEXT: [[INT4:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f16)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT4]](f16)
+ ; VI-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[C1]]
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](f16)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT6]](f16)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[INT5]](s16)
- ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[INT7]](s16)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[INT5]](f16)
+ ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[INT7]](f16)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX9-LABEL: name: test_fcos_v4s16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](s16)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[C1]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL2]](s16)
- ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[C1]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL3]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT]](s16), [[INT1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT2]](s16), [[INT3]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = G_FCOS %0
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f16)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL1]](f16)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[C1]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL2]](f16)
+ ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[C1]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT]](f16), [[INT1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT2]](f16), [[INT3]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = G_FCOS %0
$vgpr0_vgpr1 = COPY %1
...
@@ -577,33 +577,33 @@ body: |
; SI-LABEL: name: test_fcos_s32_flags
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; VI-LABEL: name: test_fcos_s32_flags
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; GFX9-LABEL: name: test_fcos_s32_flags
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan G_FCOS %0
$vgpr0 = COPY %1
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
index dd34cb1b5c72b..24000c55fdb65 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
@@ -21,15 +21,15 @@ body: |
; SI-LABEL: name: test_fdiv_s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -39,20 +39,20 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](s32), [[FPEXT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT6]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](f32), [[FPEXT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT6]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fdiv_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -69,19 +69,19 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; VI-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FADD1]]
; VI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](s16), [[TRUNC]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](f16), [[TRUNC]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fdiv_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -98,19 +98,19 @@ body: |
; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FADD1]]
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](s16), [[TRUNC]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](f16), [[TRUNC]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fdiv_s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -127,19 +127,19 @@ body: |
; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FADD1]]
; GFX10-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](s16), [[TRUNC]](s16)
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](f16), [[TRUNC]](f16)
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX11-LABEL: name: test_fdiv_s16
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -153,15 +153,15 @@ body: |
; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX11-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FMA1]]
; GFX11-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
- ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](s16), [[TRUNC]](s16)
- ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_TRUNC %1
- %4:_(s16) = G_FDIV %2, %3
- %5:_(s32) = G_ANYEXT %4
+ ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC1]](f16), [[TRUNC]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(f16) = G_TRUNC %0
+ %3:_(f16) = G_TRUNC %1
+ %4:_(f16) = G_FDIV %2, %3
+ %5:_(i32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
@@ -181,71 +181,71 @@ body: |
; SI-LABEL: name: test_fdiv_s16_afn
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = afn G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = afn G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](s32)
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[FPEXT]], [[INT]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = afn G_FPTRUNC [[FMUL]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = afn G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = afn G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[FPEXT]], [[INT]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = afn G_FPTRUNC [[FMUL]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fdiv_s16_afn
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](s16)
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = afn G_FMUL [[TRUNC]], [[INT]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMUL]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](f16)
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = afn G_FMUL [[TRUNC]], [[INT]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMUL]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fdiv_s16_afn
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](s16)
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = afn G_FMUL [[TRUNC]], [[INT]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMUL]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = afn G_FMUL [[TRUNC]], [[INT]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMUL]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fdiv_s16_afn
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](s16)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = afn G_FMUL [[TRUNC]], [[INT]]
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMUL]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = afn G_FMUL [[TRUNC]], [[INT]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMUL]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX11-LABEL: name: test_fdiv_s16_afn
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(s16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](s16)
- ; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(s16) = afn G_FMUL [[TRUNC]], [[INT]]
- ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMUL]](s16)
- ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_TRUNC %1
- %4:_(s16) = afn G_FDIV %2, %3
- %5:_(s32) = G_ANYEXT %4
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f16) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC1]](f16)
+ ; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f16) = afn G_FMUL [[TRUNC]], [[INT]]
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMUL]](f16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(f16) = G_TRUNC %0
+ %3:_(f16) = G_TRUNC %1
+ %4:_(f16) = afn G_FDIV %2, %3
+ %5:_(i32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
@@ -265,11 +265,11 @@ body: |
; SI-LABEL: name: test_fdiv_s32_denorms_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -279,17 +279,17 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; VI-LABEL: name: test_fdiv_s32_denorms_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -299,17 +299,17 @@ body: |
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_denorms_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -319,17 +319,17 @@ body: |
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_denorms_on
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -339,17 +339,17 @@ body: |
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_denorms_on
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -359,11 +359,11 @@ body: |
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -383,50 +383,50 @@ body: |
; SI-LABEL: name: test_fdiv_s32_denorms_on_afn
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; SI-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; VI-LABEL: name: test_fdiv_s32_denorms_on_afn
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; VI-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_denorms_on_afn
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_denorms_on_afn
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; GFX10-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; GFX10-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_denorms_on_afn
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; GFX11-NEXT: $vgpr0 = COPY [[FMUL]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = afn G_FDIV %0, %1
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; GFX11-NEXT: $vgpr0 = COPY [[FMUL]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = afn G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -447,11 +447,11 @@ body: |
; SI-LABEL: name: test_fdiv_s32_denorms_off
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -463,17 +463,17 @@ body: |
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; VI-LABEL: name: test_fdiv_s32_denorms_off
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; VI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -485,17 +485,17 @@ body: |
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_denorms_off
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX9-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -507,17 +507,17 @@ body: |
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_denorms_off
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX10-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -529,17 +529,17 @@ body: |
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_denorms_off
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX11-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -551,11 +551,11 @@ body: |
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -575,50 +575,50 @@ body: |
; SI-LABEL: name: test_fdiv_s32_denorms_off_afn
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; SI-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; VI-LABEL: name: test_fdiv_s32_denorms_off_afn
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; VI-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_denorms_off_afn
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_denorms_off_afn
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; GFX10-NEXT: $vgpr0 = COPY [[FMUL]](s32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; GFX10-NEXT: $vgpr0 = COPY [[FMUL]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_denorms_off_afn
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](s32)
- ; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(s32) = afn G_FMUL [[COPY]], [[INT]]
- ; GFX11-NEXT: $vgpr0 = COPY [[FMUL]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = afn G_FDIV %0, %1
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY1]](f32)
+ ; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = afn G_FMUL [[COPY]], [[INT]]
+ ; GFX11-NEXT: $vgpr0 = COPY [[FMUL]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = afn G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -638,11 +638,11 @@ body: |
; SI-LABEL: name: test_fdiv_s32_denorms_off_arcp
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = arcp G_FNEG [[INT]]
; SI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -654,17 +654,17 @@ body: |
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = arcp G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; VI-LABEL: name: test_fdiv_s32_denorms_off_arcp
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = arcp G_FNEG [[INT]]
; VI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -676,17 +676,17 @@ body: |
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = arcp G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_denorms_off_arcp
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = arcp G_FNEG [[INT]]
; GFX9-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -698,17 +698,17 @@ body: |
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = arcp G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_denorms_off_arcp
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = arcp G_FNEG [[INT]]
; GFX10-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -720,17 +720,17 @@ body: |
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = arcp G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_denorms_off_arcp
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s32), [[COPY1]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f32), [[COPY1]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = arcp G_FNEG [[INT]]
; GFX11-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -742,11 +742,11 @@ body: |
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = arcp G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](s32), [[COPY]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = arcp G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = arcp G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY1]](f32), [[COPY]](f32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = arcp G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -766,22 +766,22 @@ body: |
; SI-LABEL: name: test_fdiv_s64
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 0
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 0
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; SI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; SI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 1
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 1
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](s64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY1]](f64)
; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](i64)
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[INT]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
@@ -791,91 +791,91 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](i32), [[UV5]]
; SI-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[XOR]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](s64), [[COPY]](s64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](f64), [[COPY]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; VI-LABEL: name: test_fdiv_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 0
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 0
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; VI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 1
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 1
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](s64), [[COPY]](s64)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](f64), [[COPY]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX9-LABEL: name: test_fdiv_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 0
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 0
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 1
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 1
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](s64), [[COPY]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](f64), [[COPY]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX10-LABEL: name: test_fdiv_s64
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
; GFX10-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 0
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 0
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX10-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX10-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 1
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 1
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](s64), [[COPY]](s64)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](f64), [[COPY]](f64)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX11-LABEL: name: test_fdiv_s64
; GFX11: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
; GFX11-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 0
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 0
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX11-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX11-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](s64), [[COPY1]](s64), 1
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[COPY]](f64), [[COPY1]](f64), 1
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](s64), [[COPY]](s64)
- ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY1]](f64), [[COPY]](f64)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FDIV %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -895,13 +895,13 @@ body: |
; SI-LABEL: name: test_fdiv_v2s32
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -913,9 +913,9 @@ body: |
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; SI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; SI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -927,20 +927,20 @@ body: |
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; SI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; SI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fdiv_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; VI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -952,9 +952,9 @@ body: |
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; VI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; VI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; VI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; VI-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -966,20 +966,20 @@ body: |
; VI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; VI-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; VI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; VI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fdiv_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX9-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -991,9 +991,9 @@ body: |
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; GFX9-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; GFX9-NEXT: S_SETREG_IMM32_B32 3, 2305, implicit-def $mode, implicit $mode
@@ -1005,20 +1005,20 @@ body: |
; GFX9-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX9-NEXT: S_SETREG_IMM32_B32 0, 2305, implicit-def $mode, implicit $mode
; GFX9-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX10-LABEL: name: test_fdiv_v2s32
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX10-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -1030,9 +1030,9 @@ body: |
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; GFX10-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; GFX10-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -1044,20 +1044,20 @@ body: |
; GFX10-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX10-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX10-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX11-LABEL: name: test_fdiv_v2s32
; GFX11: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX11-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -1069,9 +1069,9 @@ body: |
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; GFX11-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; GFX11-NEXT: S_DENORM_MODE 15, implicit-def $mode, implicit $mode
@@ -1083,12 +1083,12 @@ body: |
; GFX11-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX11-NEXT: S_DENORM_MODE 12, implicit-def $mode, implicit $mode
; GFX11-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = G_FDIV %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -1101,13 +1101,13 @@ body: |
; SI-LABEL: name: test_fdiv_v2s32_flags
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1117,9 +1117,9 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; SI-NEXT: [[INT11:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT7]]
; SI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1129,20 +1129,20 @@ body: |
; SI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; SI-NEXT: [[INT12:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fdiv_v2s32_flags
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1152,9 +1152,9 @@ body: |
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; VI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; VI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; VI-NEXT: [[INT11:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT7]]
; VI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1164,20 +1164,20 @@ body: |
; VI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; VI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; VI-NEXT: [[INT12:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; VI-NEXT: [[INT13:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[INT13:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fdiv_v2s32_flags
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1187,9 +1187,9 @@ body: |
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; GFX9-NEXT: [[INT11:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT7]]
; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1199,20 +1199,20 @@ body: |
; GFX9-NEXT: [[FMA8:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; GFX9-NEXT: [[FMA9:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX9-NEXT: [[INT12:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX10-LABEL: name: test_fdiv_v2s32_flags
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT]]
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1222,9 +1222,9 @@ body: |
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; GFX10-NEXT: [[INT11:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT7]]
; GFX10-NEXT: [[FMA5:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1234,20 +1234,20 @@ body: |
; GFX10-NEXT: [[FMA8:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; GFX10-NEXT: [[FMA9:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX10-NEXT: [[INT12:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX11-LABEL: name: test_fdiv_v2s32_flags
; GFX11: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV2]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV2]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT]]
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1257,9 +1257,9 @@ body: |
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](s32), [[UV]](s32)
- ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 0
- ; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV3]](s32), 1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV2]](f32), [[UV]](f32)
+ ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 0
+ ; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV3]](f32), 1
; GFX11-NEXT: [[INT11:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = nnan G_FNEG [[INT7]]
; GFX11-NEXT: [[FMA5:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1269,12 +1269,12 @@ body: |
; GFX11-NEXT: [[FMA8:%[0-9]+]]:_(f32) = nnan G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; GFX11-NEXT: [[FMA9:%[0-9]+]]:_(f32) = nnan G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX11-NEXT: [[INT12:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](s32), [[UV1]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32)
- ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = nnan G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV3]](f32), [[UV1]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = nnan G_FDIV %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -1287,13 +1287,13 @@ body: |
; SI-LABEL: name: test_fdiv_v3s32
; SI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; SI-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; SI-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1303,9 +1303,9 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](s32), [[UV]](s32)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 0
- ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 1
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](f32), [[UV]](f32)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 0
+ ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 1
; SI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; SI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1315,9 +1315,9 @@ body: |
; SI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; SI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](s32), [[UV1]](s32)
- ; SI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 0
- ; SI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 1
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](f32), [[UV1]](f32)
+ ; SI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 0
+ ; SI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 1
; SI-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; SI-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; SI-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C]]
@@ -1327,20 +1327,20 @@ body: |
; SI-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; SI-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; SI-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; SI-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](s32), [[UV2]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32), [[INT20]](s32)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; SI-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](f32), [[UV2]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32), [[INT20]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; VI-LABEL: name: test_fdiv_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; VI-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; VI-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1350,9 +1350,9 @@ body: |
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](s32), [[UV]](s32)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 0
- ; VI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 1
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](f32), [[UV]](f32)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 0
+ ; VI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 1
; VI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; VI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1362,9 +1362,9 @@ body: |
; VI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; VI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; VI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; VI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](s32), [[UV1]](s32)
- ; VI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 0
- ; VI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 1
+ ; VI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](f32), [[UV1]](f32)
+ ; VI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 0
+ ; VI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 1
; VI-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; VI-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; VI-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C]]
@@ -1374,20 +1374,20 @@ body: |
; VI-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; VI-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; VI-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; VI-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](s32), [[UV2]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32), [[INT20]](s32)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; VI-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](f32), [[UV2]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32), [[INT20]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; GFX9-LABEL: name: test_fdiv_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1397,9 +1397,9 @@ body: |
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](s32), [[UV]](s32)
- ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 0
- ; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 1
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](f32), [[UV]](f32)
+ ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 0
+ ; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 1
; GFX9-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1409,9 +1409,9 @@ body: |
; GFX9-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; GFX9-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX9-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](s32), [[UV1]](s32)
- ; GFX9-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 0
- ; GFX9-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 1
+ ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](f32), [[UV1]](f32)
+ ; GFX9-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 0
+ ; GFX9-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 1
; GFX9-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; GFX9-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; GFX9-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C]]
@@ -1421,20 +1421,20 @@ body: |
; GFX9-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; GFX9-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; GFX9-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; GFX9-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](s32), [[UV2]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32), [[INT20]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX9-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](f32), [[UV2]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32), [[INT20]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; GFX10-LABEL: name: test_fdiv_v3s32
; GFX10: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX10-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX10-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1444,9 +1444,9 @@ body: |
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](s32), [[UV]](s32)
- ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 0
- ; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 1
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](f32), [[UV]](f32)
+ ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 0
+ ; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 1
; GFX10-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; GFX10-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1456,9 +1456,9 @@ body: |
; GFX10-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; GFX10-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX10-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](s32), [[UV1]](s32)
- ; GFX10-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 0
- ; GFX10-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 1
+ ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](f32), [[UV1]](f32)
+ ; GFX10-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 0
+ ; GFX10-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 1
; GFX10-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; GFX10-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; GFX10-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C]]
@@ -1468,20 +1468,20 @@ body: |
; GFX10-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; GFX10-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; GFX10-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; GFX10-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](s32), [[UV2]](s32)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32), [[INT20]](s32)
- ; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX10-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](f32), [[UV2]](f32)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32), [[INT20]](f32)
+ ; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; GFX11-LABEL: name: test_fdiv_v3s32
; GFX11: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX11-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX11-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s32), [[UV3]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f32), [[UV3]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -1491,9 +1491,9 @@ body: |
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](s32), [[UV]](s32)
- ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 0
- ; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s32), [[UV4]](s32), 1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[UV3]](f32), [[UV]](f32)
+ ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 0
+ ; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f32), [[UV4]](f32), 1
; GFX11-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; GFX11-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -1503,9 +1503,9 @@ body: |
; GFX11-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; GFX11-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; GFX11-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](s32), [[UV1]](s32)
- ; GFX11-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 0
- ; GFX11-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](s32), [[UV5]](s32), 1
+ ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[UV4]](f32), [[UV1]](f32)
+ ; GFX11-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 0
+ ; GFX11-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV2]](f32), [[UV5]](f32), 1
; GFX11-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; GFX11-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; GFX11-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C]]
@@ -1515,12 +1515,12 @@ body: |
; GFX11-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; GFX11-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; GFX11-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; GFX11-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](s32), [[UV2]](s32)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT6]](s32), [[INT13]](s32), [[INT20]](s32)
- ; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- %2:_(<3 x s32>) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[UV5]](f32), [[UV2]](f32)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT6]](f32), [[INT13]](f32), [[INT20]](f32)
+ ; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ %2:_(<3 x f32>) = G_FDIV %0, %1
$vgpr0_vgpr1_vgpr2 = COPY %2
...
@@ -1533,24 +1533,24 @@ body: |
; SI-LABEL: name: test_fdiv_v2s64
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 0
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 0
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; SI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; SI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 1
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 1
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](s64)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[UV2]](s64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[UV2]](f64)
; SI-NEXT: [[UV6:%[0-9]+]]:_(i32), [[UV7:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](i64)
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[INT]](f64)
; SI-NEXT: [[UV8:%[0-9]+]]:_(i32), [[UV9:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
@@ -1560,20 +1560,20 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV7]](i32), [[UV9]]
; SI-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[XOR]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](s64), [[UV]](s64)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 0
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](f64), [[UV]](f64)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 0
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INT7]]
; SI-NEXT: [[INT9:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f64)
; SI-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[INT9]], [[C]]
; SI-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[INT9]], [[FMA5]], [[INT9]]
; SI-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMA6]], [[C]]
- ; SI-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 1
+ ; SI-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 1
; SI-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA6]], [[FMA7]], [[FMA6]]
; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INT10]], [[FMA8]]
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMUL1]], [[INT10]]
- ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](s64)
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64)
; SI-NEXT: [[UV12:%[0-9]+]]:_(i32), [[UV13:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST4]](i64)
- ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(i64) = G_BITCAST [[UV3]](s64)
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(i64) = G_BITCAST [[UV3]](f64)
; SI-NEXT: [[UV14:%[0-9]+]]:_(i32), [[UV15:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST5]](i64)
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(i64) = G_BITCAST [[INT7]](f64)
; SI-NEXT: [[UV16:%[0-9]+]]:_(i32), [[UV17:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST6]](i64)
@@ -1583,152 +1583,152 @@ body: |
; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV15]](i32), [[UV17]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP3]]
; SI-NEXT: [[INT12:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f64), [[FMA8]](f64), [[FMUL1]](f64), [[XOR1]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](s64), [[UV1]](s64)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT6]](s64), [[INT13]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](f64), [[UV1]](f64)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT6]](f64), [[INT13]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; VI-LABEL: name: test_fdiv_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 0
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 0
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; VI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 1
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 1
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](s64), [[UV]](s64)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 0
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](f64), [[UV]](f64)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 0
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INT7]]
; VI-NEXT: [[INT9:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f64)
; VI-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[INT9]], [[C]]
; VI-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[INT9]], [[FMA5]], [[INT9]]
; VI-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMA6]], [[C]]
- ; VI-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 1
+ ; VI-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 1
; VI-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA6]], [[FMA7]], [[FMA6]]
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INT10]], [[FMA8]]
; VI-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMUL1]], [[INT10]]
; VI-NEXT: [[INT12:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f64), [[FMA8]](f64), [[FMUL1]](f64), [[INT11]](s1)
- ; VI-NEXT: [[INT13:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](s64), [[UV1]](s64)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT6]](s64), [[INT13]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[INT13:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](f64), [[UV1]](f64)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT6]](f64), [[INT13]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; GFX9-LABEL: name: test_fdiv_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 0
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 0
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 1
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 1
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](s64), [[UV]](s64)
- ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 0
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](f64), [[UV]](f64)
+ ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 0
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INT7]]
; GFX9-NEXT: [[INT9:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f64)
; GFX9-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[INT9]], [[C]]
; GFX9-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[INT9]], [[FMA5]], [[INT9]]
; GFX9-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMA6]], [[C]]
- ; GFX9-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 1
+ ; GFX9-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 1
; GFX9-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA6]], [[FMA7]], [[FMA6]]
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INT10]], [[FMA8]]
; GFX9-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMUL1]], [[INT10]]
; GFX9-NEXT: [[INT12:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f64), [[FMA8]](f64), [[FMUL1]](f64), [[INT11]](s1)
- ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](s64), [[UV1]](s64)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT6]](s64), [[INT13]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; GFX9-NEXT: [[INT13:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](f64), [[UV1]](f64)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT6]](f64), [[INT13]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; GFX10-LABEL: name: test_fdiv_v2s64
; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
; GFX10-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 0
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 0
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX10-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX10-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 1
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 1
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](s64), [[UV]](s64)
- ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 0
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](f64), [[UV]](f64)
+ ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 0
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INT7]]
; GFX10-NEXT: [[INT9:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f64)
; GFX10-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[INT9]], [[C]]
; GFX10-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[INT9]], [[FMA5]], [[INT9]]
; GFX10-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMA6]], [[C]]
- ; GFX10-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 1
+ ; GFX10-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 1
; GFX10-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA6]], [[FMA7]], [[FMA6]]
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INT10]], [[FMA8]]
; GFX10-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMUL1]], [[INT10]]
; GFX10-NEXT: [[INT12:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f64), [[FMA8]](f64), [[FMUL1]](f64), [[INT11]](s1)
- ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](s64), [[UV1]](s64)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT6]](s64), [[INT13]](s64)
- ; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; GFX10-NEXT: [[INT13:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](f64), [[UV1]](f64)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT6]](f64), [[INT13]](f64)
+ ; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; GFX11-LABEL: name: test_fdiv_v2s64
; GFX11: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
; GFX11-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 0
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 0
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX11-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX11-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](s64), [[UV2]](s64), 1
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV]](f64), [[UV2]](f64), 1
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](s64), [[UV]](s64)
- ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 0
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[UV2]](f64), [[UV]](f64)
+ ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f64), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 0
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[INT7]]
; GFX11-NEXT: [[INT9:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f64)
; GFX11-NEXT: [[FMA5:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[INT9]], [[C]]
; GFX11-NEXT: [[FMA6:%[0-9]+]]:_(f64) = G_FMA [[INT9]], [[FMA5]], [[INT9]]
; GFX11-NEXT: [[FMA7:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMA6]], [[C]]
- ; GFX11-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](s64), [[UV3]](s64), 1
+ ; GFX11-NEXT: [[INT10:%[0-9]+]]:_(f64), [[INT11:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[UV1]](f64), [[UV3]](f64), 1
; GFX11-NEXT: [[FMA8:%[0-9]+]]:_(f64) = G_FMA [[FMA6]], [[FMA7]], [[FMA6]]
; GFX11-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[INT10]], [[FMA8]]
; GFX11-NEXT: [[FMA9:%[0-9]+]]:_(f64) = G_FMA [[FNEG1]], [[FMUL1]], [[INT10]]
; GFX11-NEXT: [[INT12:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f64), [[FMA8]](f64), [[FMUL1]](f64), [[INT11]](s1)
- ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](s64), [[UV1]](s64)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT6]](s64), [[INT13]](s64)
- ; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- %2:_(<2 x s64>) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT13:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f64), [[UV3]](f64), [[UV1]](f64)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT6]](f64), [[INT13]](f64)
+ ; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ %2:_(<2 x f64>) = G_FDIV %0, %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...
@@ -1741,22 +1741,22 @@ body: |
; SI-LABEL: name: test_fdiv_v2s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -1766,12 +1766,12 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](s32), [[FPEXT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT6]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](s32), [[FPEXT3]](s32), 0
- ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](s32), [[FPEXT3]](s32), 1
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](f32), [[FPEXT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT6]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](f32), [[FPEXT3]](f32), 0
+ ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](f32), [[FPEXT3]](f32), 1
; SI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; SI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C1]]
@@ -1781,31 +1781,31 @@ body: |
; SI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; SI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[FPEXT3]](s32), [[FPEXT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT13]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[FPEXT3]](f32), [[FPEXT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT13]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
;
; VI-LABEL: name: test_fdiv_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](s16)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -1822,9 +1822,9 @@ body: |
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; VI-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FADD1]]
; VI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC2]](s16), [[TRUNC]](s16)
- ; VI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
- ; VI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](s16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC2]](f16), [[TRUNC]](f16)
+ ; VI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; VI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; VI-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -1840,30 +1840,30 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; VI-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD5]]
; VI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC3]](s16), [[TRUNC1]](s16)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](s16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC3]](f16), [[TRUNC1]](f16)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST6]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST6]](<2 x f16>)
;
; GFX9-LABEL: name: test_fdiv_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](s16)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -1880,9 +1880,9 @@ body: |
; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FADD1]]
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC2]](s16), [[TRUNC]](s16)
- ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](s16)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC2]](f16), [[TRUNC]](f16)
+ ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -1898,26 +1898,26 @@ body: |
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX9-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD5]]
; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC3]](s16), [[TRUNC1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT1]](s16), [[INT3]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC3]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT1]](f16), [[INT3]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
;
; GFX10-LABEL: name: test_fdiv_v2s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](s16)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -1934,9 +1934,9 @@ body: |
; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FADD1]]
; GFX10-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC2]](s16), [[TRUNC]](s16)
- ; GFX10-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX10-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](s16)
+ ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC2]](f16), [[TRUNC]](f16)
+ ; GFX10-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX10-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -1952,19 +1952,19 @@ body: |
; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX10-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD5]]
; GFX10-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC3]](s16), [[TRUNC1]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT1]](s16), [[INT3]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC3]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT1]](f16), [[INT3]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
;
; GFX11-LABEL: name: test_fdiv_v2s16
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
- ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
- ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](s16)
- ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](s16)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<2 x f16>)
+ ; GFX11-NEXT: [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY1]](<2 x f16>)
+ ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](f16)
+ ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](f16)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -1978,9 +1978,9 @@ body: |
; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX11-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FMA1]]
; GFX11-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
- ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[UV2]](s16), [[UV]](s16)
- ; GFX11-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](s16)
- ; GFX11-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](s16)
+ ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[UV2]](f16), [[UV]](f16)
+ ; GFX11-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](f16)
+ ; GFX11-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](f16)
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX11-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -1993,12 +1993,12 @@ body: |
; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX11-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FMA4]]
; GFX11-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[UV3]](s16), [[UV1]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT1]](s16), [[INT3]](s16)
- ; GFX11-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[UV3]](f16), [[UV1]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT1]](f16), [[INT3]](f16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -2011,12 +2011,12 @@ body: |
; SI-LABEL: name: test_fdiv_v3s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
+ ; SI-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
@@ -2026,12 +2026,12 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](s32), [[FPEXT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT6]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](s32), [[FPEXT3]](s32), 0
- ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](s32), [[FPEXT3]](s32), 1
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](f32), [[FPEXT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT6]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](f32), [[FPEXT3]](f32), 0
+ ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](f32), [[FPEXT3]](f32), 1
; SI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; SI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C]]
@@ -2041,12 +2041,12 @@ body: |
; SI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; SI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[FPEXT3]](s32), [[FPEXT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT13]](s32)
- ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](s32), [[FPEXT5]](s32), 0
- ; SI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](s32), [[FPEXT5]](s32), 1
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[FPEXT3]](f32), [[FPEXT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT13]](f32)
+ ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](f32), [[FPEXT5]](f32), 0
+ ; SI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](f32), [[FPEXT5]](f32), 1
; SI-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; SI-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; SI-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C]]
@@ -2056,20 +2056,20 @@ body: |
; SI-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; SI-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; SI-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; SI-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[FPEXT5]](s32), [[FPEXT4]](s32)
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT20]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
- ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; SI-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[FPEXT5]](f32), [[FPEXT4]](f32)
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT20]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC1]](f16)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; VI-LABEL: name: test_fdiv_v3s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2086,9 +2086,9 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; VI-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FADD1]]
; VI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](s16), [[DEF]](s16)
- ; VI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; VI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; VI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; VI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; VI-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2104,9 +2104,9 @@ body: |
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; VI-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FADD5]]
; VI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](s16), [[DEF]](s16)
- ; VI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; VI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; VI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; VI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; VI-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; VI-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2122,19 +2122,19 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; VI-NEXT: [[FADD11:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD9]]
; VI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD11]](f32)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](s16), [[DEF]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT3]](s16)
- ; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT5]](s16)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT3]](f16)
+ ; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT5]](f16)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; GFX9-LABEL: name: test_fdiv_v3s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2151,9 +2151,9 @@ body: |
; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FADD1]]
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2169,9 +2169,9 @@ body: |
; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX9-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FADD5]]
; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX9-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX9-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX9-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; GFX9-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2187,19 +2187,19 @@ body: |
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; GFX9-NEXT: [[FADD11:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD9]]
; GFX9-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD11]](f32)
- ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT3]](s16)
- ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT5]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT3]](f16)
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT5]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; GFX10-LABEL: name: test_fdiv_v3s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2216,9 +2216,9 @@ body: |
; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FADD1]]
; GFX10-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX10-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX10-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX10-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX10-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX10-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2234,9 +2234,9 @@ body: |
; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX10-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FADD5]]
; GFX10-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX10-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX10-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX10-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX10-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX10-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; GFX10-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2252,19 +2252,19 @@ body: |
; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; GFX10-NEXT: [[FADD11:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD9]]
; GFX10-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD11]](f32)
- ; GFX10-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX10-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT3]](s16)
- ; GFX10-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT5]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; GFX10-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX10-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT3]](f16)
+ ; GFX10-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT5]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; GFX10-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; GFX11-LABEL: name: test_fdiv_v3s16
; GFX11: liveins: $vgpr0, $vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2278,9 +2278,9 @@ body: |
; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX11-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FMA1]]
; GFX11-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
- ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX11-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX11-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX11-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX11-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX11-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2293,9 +2293,9 @@ body: |
; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX11-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FMA4]]
; GFX11-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX11-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
- ; GFX11-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](s16)
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX11-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; GFX11-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
; GFX11-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; GFX11-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2308,16 +2308,16 @@ body: |
; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; GFX11-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FMA7]]
; GFX11-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
- ; GFX11-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](s16), [[DEF]](s16)
- ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX11-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT3]](s16)
- ; GFX11-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT5]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; GFX11-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s16>) = G_IMPLICIT_DEF
- %1:_(<3 x s16>) = G_IMPLICIT_DEF
- %2:_(<3 x s16>) = G_FDIV %0, %1
- %3:_(<3 x s32>) = G_ANYEXT %2
+ ; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[DEF]](f16), [[DEF]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX11-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT3]](f16)
+ ; GFX11-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT5]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; GFX11-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
+ %0:_(<3 x f16>) = G_IMPLICIT_DEF
+ %1:_(<3 x f16>) = G_IMPLICIT_DEF
+ %2:_(<3 x f16>) = G_FDIV %0, %1
+ %3:_(<3 x i32>) = G_ANYEXT %2
S_NOP 0, implicit %3
...
@@ -2330,32 +2330,32 @@ body: |
; SI-LABEL: name: test_fdiv_v4s16
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
+ ; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -2365,12 +2365,12 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](s32), [[FPEXT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT6]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](s32), [[FPEXT3]](s32), 0
- ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](s32), [[FPEXT3]](s32), 1
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](f32), [[FPEXT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT6]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32), [[INT8:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](f32), [[FPEXT3]](f32), 0
+ ; SI-NEXT: [[INT9:%[0-9]+]]:_(f32), [[INT10:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT2]](f32), [[FPEXT3]](f32), 1
; SI-NEXT: [[INT11:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT7]](f32)
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[INT7]]
; SI-NEXT: [[FMA5:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[INT11]], [[C1]]
@@ -2380,12 +2380,12 @@ body: |
; SI-NEXT: [[FMA8:%[0-9]+]]:_(f32) = G_FMA [[FMA7]], [[FMA6]], [[FMUL1]]
; SI-NEXT: [[FMA9:%[0-9]+]]:_(f32) = G_FMA [[FNEG1]], [[FMA8]], [[INT9]]
; SI-NEXT: [[INT12:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA9]](f32), [[FMA6]](f32), [[FMA8]](f32), [[INT10]](s1)
- ; SI-NEXT: [[INT13:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[FPEXT3]](s32), [[FPEXT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT13]](s32)
- ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC6]](s16)
- ; SI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](s32), [[FPEXT5]](s32), 0
- ; SI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](s32), [[FPEXT5]](s32), 1
+ ; SI-NEXT: [[INT13:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT12]](f32), [[FPEXT3]](f32), [[FPEXT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT13]](f32)
+ ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
+ ; SI-NEXT: [[INT14:%[0-9]+]]:_(f32), [[INT15:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](f32), [[FPEXT5]](f32), 0
+ ; SI-NEXT: [[INT16:%[0-9]+]]:_(f32), [[INT17:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT4]](f32), [[FPEXT5]](f32), 1
; SI-NEXT: [[INT18:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT14]](f32)
; SI-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[INT14]]
; SI-NEXT: [[FMA10:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[INT18]], [[C1]]
@@ -2395,12 +2395,12 @@ body: |
; SI-NEXT: [[FMA13:%[0-9]+]]:_(f32) = G_FMA [[FMA12]], [[FMA11]], [[FMUL2]]
; SI-NEXT: [[FMA14:%[0-9]+]]:_(f32) = G_FMA [[FNEG2]], [[FMA13]], [[INT16]]
; SI-NEXT: [[INT19:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA14]](f32), [[FMA11]](f32), [[FMA13]](f32), [[INT17]](s1)
- ; SI-NEXT: [[INT20:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[FPEXT5]](s32), [[FPEXT4]](s32)
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT20]](s32)
- ; SI-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC7]](s16)
- ; SI-NEXT: [[INT21:%[0-9]+]]:_(f32), [[INT22:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT6]](s32), [[FPEXT7]](s32), 0
- ; SI-NEXT: [[INT23:%[0-9]+]]:_(f32), [[INT24:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT6]](s32), [[FPEXT7]](s32), 1
+ ; SI-NEXT: [[INT20:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT19]](f32), [[FPEXT5]](f32), [[FPEXT4]](f32)
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT20]](f32)
+ ; SI-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
+ ; SI-NEXT: [[INT21:%[0-9]+]]:_(f32), [[INT22:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT6]](f32), [[FPEXT7]](f32), 0
+ ; SI-NEXT: [[INT23:%[0-9]+]]:_(f32), [[INT24:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT6]](f32), [[FPEXT7]](f32), 1
; SI-NEXT: [[INT25:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT21]](f32)
; SI-NEXT: [[FNEG3:%[0-9]+]]:_(f32) = G_FNEG [[INT21]]
; SI-NEXT: [[FMA15:%[0-9]+]]:_(f32) = G_FMA [[FNEG3]], [[INT25]], [[C1]]
@@ -2410,47 +2410,47 @@ body: |
; SI-NEXT: [[FMA18:%[0-9]+]]:_(f32) = G_FMA [[FMA17]], [[FMA16]], [[FMUL3]]
; SI-NEXT: [[FMA19:%[0-9]+]]:_(f32) = G_FMA [[FNEG3]], [[FMA18]], [[INT23]]
; SI-NEXT: [[INT26:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA19]](f32), [[FMA16]](f32), [[FMA18]](f32), [[INT24]](s1)
- ; SI-NEXT: [[INT27:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT26]](f32), [[FPEXT7]](s32), [[FPEXT6]](s32)
- ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT27]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[INT27:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT26]](f32), [[FPEXT7]](f32), [[FPEXT6]](f32)
+ ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT27]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; VI-LABEL: name: test_fdiv_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](s16)
+ ; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; VI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; VI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2467,9 +2467,9 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; VI-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD1]]
; VI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC4]](s16), [[TRUNC]](s16)
- ; VI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
- ; VI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](s16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC4]](f16), [[TRUNC]](f16)
+ ; VI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; VI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; VI-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2485,9 +2485,9 @@ body: |
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; VI-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST7]], [[FADD5]]
; VI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC5]](s16), [[TRUNC1]](s16)
- ; VI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](s16)
- ; VI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](s16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC5]](f16), [[TRUNC1]](f16)
+ ; VI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; VI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
; VI-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; VI-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2503,9 +2503,9 @@ body: |
; VI-NEXT: [[BITCAST9:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; VI-NEXT: [[FADD11:%[0-9]+]]:_(f32) = G_FADD [[BITCAST9]], [[FADD9]]
; VI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD11]](f32)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[TRUNC6]](s16), [[TRUNC2]](s16)
- ; VI-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](s16)
- ; VI-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](s16)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[TRUNC6]](f16), [[TRUNC2]](f16)
+ ; VI-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; VI-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
; VI-NEXT: [[FNEG3:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT7]]
; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT7]](f32)
; VI-NEXT: [[FMUL15:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT6]], [[INT6]]
@@ -2521,46 +2521,46 @@ body: |
; VI-NEXT: [[BITCAST11:%[0-9]+]]:_(f32) = G_BITCAST [[AND3]](i32)
; VI-NEXT: [[FADD15:%[0-9]+]]:_(f32) = G_FADD [[BITCAST11]], [[FADD13]]
; VI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD15]](f32)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[TRUNC7]](s16), [[TRUNC3]](s16)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](s16)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[TRUNC7]](f16), [[TRUNC3]](f16)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[INT5]](s16)
- ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[INT7]](s16)
+ ; VI-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[INT5]](f16)
+ ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[INT7]](f16)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST12]](<2 x s16>), [[BITCAST13]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; VI-NEXT: [[BITCAST13:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST12]](<2 x f16>), [[BITCAST13]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX9-LABEL: name: test_fdiv_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](s16)
+ ; GFX9-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX9-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX9-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2577,9 +2577,9 @@ body: |
; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX9-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD1]]
; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC4]](s16), [[TRUNC]](s16)
- ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](s16)
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC4]](f16), [[TRUNC]](f16)
+ ; GFX9-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
; GFX9-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX9-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2595,9 +2595,9 @@ body: |
; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX9-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST7]], [[FADD5]]
; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC5]](s16), [[TRUNC1]](s16)
- ; GFX9-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX9-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](s16)
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC5]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX9-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
; GFX9-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; GFX9-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2613,9 +2613,9 @@ body: |
; GFX9-NEXT: [[BITCAST9:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; GFX9-NEXT: [[FADD11:%[0-9]+]]:_(f32) = G_FADD [[BITCAST9]], [[FADD9]]
; GFX9-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD11]](f32)
- ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[TRUNC6]](s16), [[TRUNC2]](s16)
- ; GFX9-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX9-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](s16)
+ ; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[TRUNC6]](f16), [[TRUNC2]](f16)
+ ; GFX9-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX9-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
; GFX9-NEXT: [[FNEG3:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT7]]
; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT7]](f32)
; GFX9-NEXT: [[FMUL15:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT6]], [[INT6]]
@@ -2631,38 +2631,38 @@ body: |
; GFX9-NEXT: [[BITCAST11:%[0-9]+]]:_(f32) = G_BITCAST [[AND3]](i32)
; GFX9-NEXT: [[FADD15:%[0-9]+]]:_(f32) = G_FADD [[BITCAST11]], [[FADD13]]
; GFX9-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD15]](f32)
- ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[TRUNC7]](s16), [[TRUNC3]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT1]](s16), [[INT3]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT5]](s16), [[INT7]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX9-NEXT: [[INT7:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[TRUNC7]](f16), [[TRUNC3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT1]](f16), [[INT3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT5]](f16), [[INT7]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX10-LABEL: name: test_fdiv_v4s16
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX10-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](s16)
- ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](s16)
+ ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX10-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX10-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2679,9 +2679,9 @@ body: |
; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FADD1]]
; GFX10-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC4]](s16), [[TRUNC]](s16)
- ; GFX10-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX10-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](s16)
+ ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[TRUNC4]](f16), [[TRUNC]](f16)
+ ; GFX10-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
; GFX10-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX10-NEXT: [[FMUL5:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2697,9 +2697,9 @@ body: |
; GFX10-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX10-NEXT: [[FADD7:%[0-9]+]]:_(f32) = G_FADD [[BITCAST7]], [[FADD5]]
; GFX10-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD7]](f32)
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC5]](s16), [[TRUNC1]](s16)
- ; GFX10-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX10-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](s16)
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[TRUNC5]](f16), [[TRUNC1]](f16)
+ ; GFX10-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX10-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
; GFX10-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; GFX10-NEXT: [[FMUL10:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2715,9 +2715,9 @@ body: |
; GFX10-NEXT: [[BITCAST9:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; GFX10-NEXT: [[FADD11:%[0-9]+]]:_(f32) = G_FADD [[BITCAST9]], [[FADD9]]
; GFX10-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD11]](f32)
- ; GFX10-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[TRUNC6]](s16), [[TRUNC2]](s16)
- ; GFX10-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX10-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](s16)
+ ; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[TRUNC6]](f16), [[TRUNC2]](f16)
+ ; GFX10-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX10-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
; GFX10-NEXT: [[FNEG3:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT7]]
; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT7]](f32)
; GFX10-NEXT: [[FMUL15:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT6]], [[INT6]]
@@ -2733,21 +2733,21 @@ body: |
; GFX10-NEXT: [[BITCAST11:%[0-9]+]]:_(f32) = G_BITCAST [[AND3]](i32)
; GFX10-NEXT: [[FADD15:%[0-9]+]]:_(f32) = G_FADD [[BITCAST11]], [[FADD13]]
; GFX10-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD15]](f32)
- ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[TRUNC7]](s16), [[TRUNC3]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT1]](s16), [[INT3]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT5]](s16), [[INT7]](s16)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX10-NEXT: [[INT7:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[TRUNC7]](f16), [[TRUNC3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT1]](f16), [[INT3]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT5]](f16), [[INT7]](f16)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX11-LABEL: name: test_fdiv_v4s16
; GFX11: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX11-NEXT: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](s16)
- ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV4]](s16)
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f16), [[UV1:%[0-9]+]]:_(f16), [[UV2:%[0-9]+]]:_(f16), [[UV3:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX11-NEXT: [[UV4:%[0-9]+]]:_(f16), [[UV5:%[0-9]+]]:_(f16), [[UV6:%[0-9]+]]:_(f16), [[UV7:%[0-9]+]]:_(f16) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX11-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[UV]](f16)
+ ; GFX11-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[UV4]](f16)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT1]]
; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT1]](f32)
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[INT]]
@@ -2761,9 +2761,9 @@ body: |
; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[AND]](i32)
; GFX11-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[BITCAST1]], [[FMA1]]
; GFX11-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
- ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[UV4]](s16), [[UV]](s16)
- ; GFX11-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](s16)
- ; GFX11-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV5]](s16)
+ ; GFX11-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC]](f16), [[UV4]](f16), [[UV]](f16)
+ ; GFX11-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[UV1]](f16)
+ ; GFX11-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[UV5]](f16)
; GFX11-NEXT: [[FNEG1:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT3]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT3]](f32)
; GFX11-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[INT2]]
@@ -2776,9 +2776,9 @@ body: |
; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[AND1]](i32)
; GFX11-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[BITCAST3]], [[FMA4]]
; GFX11-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[UV5]](s16), [[UV1]](s16)
- ; GFX11-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](s16)
- ; GFX11-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[UV6]](s16)
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC1]](f16), [[UV5]](f16), [[UV1]](f16)
+ ; GFX11-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[UV2]](f16)
+ ; GFX11-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[UV6]](f16)
; GFX11-NEXT: [[FNEG2:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT5]]
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT5]](f32)
; GFX11-NEXT: [[FMUL4:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[INT4]]
@@ -2791,9 +2791,9 @@ body: |
; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[AND2]](i32)
; GFX11-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[BITCAST5]], [[FMA7]]
; GFX11-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
- ; GFX11-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[UV6]](s16), [[UV2]](s16)
- ; GFX11-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](s16)
- ; GFX11-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[UV7]](s16)
+ ; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC2]](f16), [[UV6]](f16), [[UV2]](f16)
+ ; GFX11-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[UV3]](f16)
+ ; GFX11-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[UV7]](f16)
; GFX11-NEXT: [[FNEG3:%[0-9]+]]:_(f32) = G_FNEG [[FPEXT7]]
; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FPEXT7]](f32)
; GFX11-NEXT: [[FMUL6:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT6]], [[INT6]]
@@ -2806,14 +2806,14 @@ body: |
; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[AND3]](i32)
; GFX11-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[BITCAST7]], [[FMA10]]
; GFX11-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
- ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[UV7]](s16), [[UV3]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT1]](s16), [[INT3]](s16)
- ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT5]](s16), [[INT7]](s16)
- ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
- %2:_(<4 x s16>) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT7:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[FPTRUNC3]](f16), [[UV7]](f16), [[UV3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT1]](f16), [[INT3]](f16)
+ ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT5]](f16), [[INT7]](f16)
+ ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ %2:_(<4 x f16>) = G_FDIV %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -2826,14 +2826,14 @@ body: |
; SI-LABEL: name: test_fdiv_s16_constant_one_rcp
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.000000e+00
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.000000e+00
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -2843,51 +2843,51 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](s32), [[FPEXT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT6]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](f32), [[FPEXT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT6]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fdiv_s16_constant_one_rcp
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fdiv_s16_constant_one_rcp
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fdiv_s16_constant_one_rcp
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](s16)
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](f16)
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX11-LABEL: name: test_fdiv_s16_constant_one_rcp
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](s16)
- ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s16) = G_FCONSTANT half 1.0
- %1:_(s32) = COPY $vgpr0
- %2:_(s16) = G_TRUNC %1
- %3:_(s16) = G_FDIV %0, %2
- %4:_(s32) = G_ANYEXT %3
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(f16) = G_FCONSTANT half 1.0
+ %1:_(i32) = COPY $vgpr0
+ %2:_(f16) = G_TRUNC %1
+ %3:_(f16) = G_FDIV %0, %2
+ %4:_(i32) = G_ANYEXT %3
$vgpr0 = COPY %4
...
@@ -2900,14 +2900,14 @@ body: |
; SI-LABEL: name: test_fdiv_s16_constant_negative_one_rcp
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half -1.000000e+00
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half -1.000000e+00
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](s32), [[FPEXT1]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[FPEXT]](f32), [[FPEXT1]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -2917,55 +2917,55 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](s32), [[FPEXT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT6]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[FPEXT1]](f32), [[FPEXT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT6]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fdiv_s16_constant_negative_one_rcp
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[TRUNC]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fdiv_s16_constant_negative_one_rcp
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[TRUNC]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fdiv_s16_constant_negative_one_rcp
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s16)
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[TRUNC]]
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](f16)
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX11-LABEL: name: test_fdiv_s16_constant_negative_one_rcp
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s16)
- ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s16) = G_FCONSTANT half -1.0
- %1:_(s32) = COPY $vgpr0
- %2:_(s16) = G_TRUNC %1
- %3:_(s16) = G_FDIV %0, %2
- %4:_(s32) = G_ANYEXT %3
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f16) = G_FNEG [[TRUNC]]
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](f16)
+ ; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX11-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(f16) = G_FCONSTANT half -1.0
+ %1:_(i32) = COPY $vgpr0
+ %2:_(f16) = G_TRUNC %1
+ %3:_(f16) = G_FDIV %0, %2
+ %4:_(i32) = G_ANYEXT %3
$vgpr0 = COPY %4
...
@@ -2978,105 +2978,100 @@ body: |
; SI-LABEL: name: test_fdiv_s32_constant_one_rcp
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
- ; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
+ ; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FMA]], [[INT4]], [[INT4]]
; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[FMA1]]
; SI-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; VI-LABEL: name: test_fdiv_s32_constant_one_rcp
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
- ; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
+ ; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FMA]], [[INT4]], [[INT4]]
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[FMA1]]
; VI-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_constant_one_rcp
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
- ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FMA]], [[INT4]], [[INT4]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[FMA1]]
; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_constant_one_rcp
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
- ; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
+ ; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
; GFX10-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FMA]], [[INT4]], [[INT4]]
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[FMA1]]
; GFX10-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_constant_one_rcp
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
- ; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
+ ; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C]]
; GFX11-NEXT: [[FMA1:%[0-9]+]]:_(f32) = G_FMA [[FMA]], [[INT4]], [[INT4]]
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[FMA1]]
; GFX11-NEXT: [[FMA2:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](s32)
- %0:_(s32) = G_FCONSTANT float 1.0
- %1:_(s32) = COPY $vgpr0
- %2:_(s32) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](f32)
+ %0:_(f32) = G_FCONSTANT float 1.0
+ %1:_(f32) = COPY $vgpr0
+ %2:_(f32) = G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -3089,11 +3084,11 @@ body: |
; SI-LABEL: name: test_fdiv_s32_constant_negative_one_rcp
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.000000e+00
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; SI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -3103,17 +3098,17 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; VI-LABEL: name: test_fdiv_s32_constant_negative_one_rcp
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.000000e+00
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; VI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; VI-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -3123,17 +3118,17 @@ body: |
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX9-LABEL: name: test_fdiv_s32_constant_negative_one_rcp
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; GFX9-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -3143,17 +3138,17 @@ body: |
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX10-LABEL: name: test_fdiv_s32_constant_negative_one_rcp
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.000000e+00
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX10-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; GFX10-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -3163,17 +3158,17 @@ body: |
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](s32)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; GFX10-NEXT: $vgpr0 = COPY [[INT6]](f32)
;
; GFX11-LABEL: name: test_fdiv_s32_constant_negative_one_rcp
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.000000e+00
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
; GFX11-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 0
- ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s32), [[COPY]](s32), 1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 0
+ ; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f32), [[INT3:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f32), [[COPY]](f32), 1
; GFX11-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f32)
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f32) = G_FNEG [[INT]]
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[INT4]], [[C1]]
@@ -3183,11 +3178,11 @@ body: |
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f32) = G_FMA [[FMA2]], [[FMA1]], [[FMUL]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f32), [[FMA1]](f32), [[FMA3]](f32), [[INT3]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](s32), [[C]](s32)
- ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](s32)
- %0:_(s32) = G_FCONSTANT float -1.0
- %1:_(s32) = COPY $vgpr0
- %2:_(s32) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f32), [[COPY]](f32), [[C]](f32)
+ ; GFX11-NEXT: $vgpr0 = COPY [[INT6]](f32)
+ %0:_(f32) = G_FCONSTANT float -1.0
+ %1:_(f32) = COPY $vgpr0
+ %2:_(f32) = G_FDIV %0, %1
$vgpr0 = COPY %2
...
@@ -3207,22 +3202,21 @@ body: |
; SI-LABEL: name: test_fdiv_s64_constant_one_rcp
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; SI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
- ; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
+ ; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
- ; SI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; SI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[C]](s64)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[C]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](i64)
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[INT]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
@@ -3232,91 +3226,87 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](i32), [[UV5]]
; SI-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[XOR]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; VI-LABEL: name: test_fdiv_s64_constant_one_rcp
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
- ; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
+ ; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
- ; VI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; VI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX9-LABEL: name: test_fdiv_s64_constant_one_rcp
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
- ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
+ ; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
- ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX10-LABEL: name: test_fdiv_s64_constant_one_rcp
; GFX10: liveins: $vgpr0_vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
- ; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
+ ; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX10-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
- ; GFX10-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; GFX10-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX11-LABEL: name: test_fdiv_s64_constant_one_rcp
; GFX11: liveins: $vgpr0_vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX11-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
- ; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
+ ; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C]]
; GFX11-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
- ; GFX11-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; GFX11-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C]]
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
- %0:_(s64) = G_FCONSTANT double 1.0
- %1:_(s64) = COPY $vgpr0_vgpr1
- %2:_(s64) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
+ %0:_(f64) = G_FCONSTANT double 1.0
+ %1:_(f64) = COPY $vgpr0_vgpr1
+ %2:_(f64) = G_FDIV %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -3336,22 +3326,22 @@ body: |
; SI-LABEL: name: test_fdiv_s64_constant_negative_one_rcp
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.000000e+00
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; SI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; SI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; SI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
; SI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; SI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; SI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; SI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[C]](s64)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i64) = G_BITCAST [[C]](f64)
; SI-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST]](i64)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](s64)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64)
; SI-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](i64)
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[INT]](f64)
; SI-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST2]](i64)
@@ -3361,90 +3351,90 @@ body: |
; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV3]](i32), [[UV5]]
; SI-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; SI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[XOR]](s1)
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; VI-LABEL: name: test_fdiv_s64_constant_negative_one_rcp
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.000000e+00
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; VI-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; VI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; VI-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
; VI-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; VI-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; VI-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; VI-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; VI-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX9-LABEL: name: test_fdiv_s64_constant_negative_one_rcp
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.000000e+00
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX9-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
; GFX9-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX9-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; GFX9-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX9-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX9-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; GFX9-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX10-LABEL: name: test_fdiv_s64_constant_negative_one_rcp
; GFX10: liveins: $vgpr0_vgpr1
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.000000e+00
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
; GFX10-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; GFX10-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX10-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
; GFX10-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX10-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; GFX10-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; GFX10-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX10-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX10-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
+ ; GFX10-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
;
; GFX11-LABEL: name: test_fdiv_s64_constant_negative_one_rcp
; GFX11: liveins: $vgpr0_vgpr1
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX11-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double -1.000000e+00
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
; GFX11-NEXT: [[C1:%[0-9]+]]:_(f64) = G_FCONSTANT double 1.000000e+00
- ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 0
+ ; GFX11-NEXT: [[INT:%[0-9]+]]:_(f64), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 0
; GFX11-NEXT: [[FNEG:%[0-9]+]]:_(f64) = G_FNEG [[INT]]
; GFX11-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](f64)
; GFX11-NEXT: [[FMA:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[INT2]], [[C1]]
; GFX11-NEXT: [[FMA1:%[0-9]+]]:_(f64) = G_FMA [[INT2]], [[FMA]], [[INT2]]
; GFX11-NEXT: [[FMA2:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMA1]], [[C1]]
- ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](s64), [[COPY]](s64), 1
+ ; GFX11-NEXT: [[INT3:%[0-9]+]]:_(f64), [[INT4:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.scale), [[C]](f64), [[COPY]](f64), 1
; GFX11-NEXT: [[FMA3:%[0-9]+]]:_(f64) = G_FMA [[FMA1]], [[FMA2]], [[FMA1]]
; GFX11-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[INT3]], [[FMA3]]
; GFX11-NEXT: [[FMA4:%[0-9]+]]:_(f64) = G_FMA [[FNEG]], [[FMUL]], [[INT3]]
; GFX11-NEXT: [[INT5:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[FMA4]](f64), [[FMA3]](f64), [[FMUL]](f64), [[INT4]](s1)
- ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](s64), [[C]](s64)
- ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](s64)
- %0:_(s64) = G_FCONSTANT double -1.0
- %1:_(s64) = COPY $vgpr0_vgpr1
- %2:_(s64) = G_FDIV %0, %1
+ ; GFX11-NEXT: [[INT6:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fixup), [[INT5]](f64), [[COPY]](f64), [[C]](f64)
+ ; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INT6]](f64)
+ %0:_(f64) = G_FCONSTANT double -1.0
+ %1:_(f64) = COPY $vgpr0_vgpr1
+ %2:_(f64) = G_FDIV %0, %1
$vgpr0_vgpr1 = COPY %2
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
index f7c5924a38b1a..8326d66a3a688 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
@@ -18,57 +18,57 @@ body: |
; GFX6-LABEL: name: test_fmad_s16_flush
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX7-LABEL: name: test_fmad_s16_flush
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC1]], [[TRUNC2]]
- ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAD]](s16)
- ; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC]], [[TRUNC1]], [[TRUNC2]]
+ ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMAD]](f16)
+ ; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fmad_s16_flush
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC1]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC2]]
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr1
- %3:_(s16) = G_TRUNC %0
- %4:_(s16) = G_TRUNC %1
- %5:_(s16) = G_TRUNC %2
- %6:_(s16) = G_FMAD %3, %4, %5
- %7:_(s32) = G_ANYEXT %6
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC1]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC2]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(i32) = COPY $vgpr1
+ %3:_(f16) = G_TRUNC %0
+ %4:_(f16) = G_TRUNC %1
+ %5:_(f16) = G_TRUNC %2
+ %6:_(f16) = G_FMAD %3, %4, %5
+ %7:_(i32) = G_ANYEXT %6
$vgpr0 = COPY %7
...
@@ -86,102 +86,102 @@ body: |
; GFX6-LABEL: name: test_fmad_v2s16_flush
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT6]], [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT6]], [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x f16>)
;
; GFX7-LABEL: name: test_fmad_v2s16_flush
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX7-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC2]], [[TRUNC4]]
- ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC1]], [[TRUNC3]], [[TRUNC5]]
- ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD]](s16)
- ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD1]](s16)
+ ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC]], [[TRUNC2]], [[TRUNC4]]
+ ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC1]], [[TRUNC3]], [[TRUNC5]]
+ ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD]](f16)
+ ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD1]](f16)
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
+ ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x f16>)
;
; GFX10-LABEL: name: test_fmad_v2s16_flush
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC2]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC4]]
- ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[TRUNC3]]
- ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[FMUL1]], [[TRUNC5]]
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = COPY $vgpr2
- %3:_(<2 x s16>) = G_FMAD %0, %1, %2
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC2]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC4]]
+ ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[TRUNC3]]
+ ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[FMUL1]], [[TRUNC5]]
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = COPY $vgpr2
+ %3:_(<2 x f16>) = G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -199,183 +199,183 @@ body: |
; GFX6-LABEL: name: test_fmad_v4s16_flush
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX6-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC8]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC9]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT6]], [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC6]](s16)
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT8]], [[FPEXT9]]
- ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL2]](s32)
- ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC4]](s16)
- ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC10]](s16)
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT10]], [[FPEXT11]]
- ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
- ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC7]](s16)
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT12]], [[FPEXT13]]
- ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL3]](s32)
- ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
- ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC11]](s16)
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT14]], [[FPEXT15]]
- ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC8]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC9]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT6]], [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT8]], [[FPEXT9]]
+ ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL2]](f32)
+ ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC4]](f16)
+ ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC10]](f16)
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FPEXT10]], [[FPEXT11]]
+ ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
+ ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT12]], [[FPEXT13]]
+ ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL3]](f32)
+ ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC6]](f16)
+ ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC11]](f16)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FPEXT14]], [[FPEXT15]]
+ ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](s16)
- ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC7]](s16)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](f16)
+ ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC7]](f16)
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x f16>), [[BITCAST7]](<2 x f16>)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX7-LABEL: name: test_fmad_v4s16_flush
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX7-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX7-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX7-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX7-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX7-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX7-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX7-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC4]], [[TRUNC8]]
- ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC1]], [[TRUNC5]], [[TRUNC9]]
- ; GFX7-NEXT: [[FMAD2:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC2]], [[TRUNC6]], [[TRUNC10]]
- ; GFX7-NEXT: [[FMAD3:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC3]], [[TRUNC7]], [[TRUNC11]]
- ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD]](s16)
- ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD1]](s16)
+ ; GFX7-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC]], [[TRUNC4]], [[TRUNC8]]
+ ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC1]], [[TRUNC5]], [[TRUNC9]]
+ ; GFX7-NEXT: [[FMAD2:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC2]], [[TRUNC6]], [[TRUNC10]]
+ ; GFX7-NEXT: [[FMAD3:%[0-9]+]]:_(f16) = G_FMAD [[TRUNC3]], [[TRUNC7]], [[TRUNC11]]
+ ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD]](f16)
+ ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD1]](f16)
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX7-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX7-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD2]](s16)
- ; GFX7-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD3]](s16)
+ ; GFX7-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX7-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD2]](f16)
+ ; GFX7-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FMAD3]](f16)
; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX7-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX7-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX7-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x f16>), [[BITCAST7]](<2 x f16>)
+ ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX10-LABEL: name: test_fmad_v4s16_flush
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX10-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX10-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX10-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX10-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC4]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC8]]
- ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[TRUNC5]]
- ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[FMUL1]], [[TRUNC9]]
- ; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[TRUNC6]]
- ; GFX10-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[FMUL2]], [[TRUNC10]]
- ; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[TRUNC7]]
- ; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[FMUL3]], [[TRUNC11]]
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD2]](s16), [[FADD3]](s16)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
- %2:_(<4 x s16>) = COPY $vgpr4_vgpr5
- %3:_(<4 x s16>) = G_FMAD %0, %1, %2
+ ; GFX10-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC4]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC8]]
+ ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[TRUNC5]]
+ ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[FMUL1]], [[TRUNC9]]
+ ; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[TRUNC6]]
+ ; GFX10-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[FMUL2]], [[TRUNC10]]
+ ; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[TRUNC7]]
+ ; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f16) = G_FADD [[FMUL3]], [[TRUNC11]]
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD2]](f16), [[FADD3]](f16)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ %2:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ %3:_(<4 x f16>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
@@ -394,58 +394,58 @@ body: |
; GFX6-LABEL: name: test_fmad_s16_denorm
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX7-LABEL: name: test_fmad_s16_denorm
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC1]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC2]]
- ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC1]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC2]]
+ ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fmad_s16_denorm
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC1]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC2]]
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr1
- %3:_(s16) = G_TRUNC %0
- %4:_(s16) = G_TRUNC %1
- %5:_(s16) = G_TRUNC %2
- %6:_(s16) = G_FMAD %3, %4, %5
- %7:_(s32) = G_ANYEXT %6
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC1]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC2]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(i32) = COPY $vgpr1
+ %3:_(f16) = G_TRUNC %0
+ %4:_(f16) = G_TRUNC %1
+ %5:_(f16) = G_TRUNC %2
+ %6:_(f16) = G_FMAD %3, %4, %5
+ %7:_(i32) = G_ANYEXT %6
$vgpr0 = COPY %7
...
@@ -463,58 +463,58 @@ body: |
; GFX6-LABEL: name: test_fmad_s16_denorm_flags
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX7-LABEL: name: test_fmad_s16_denorm_flags
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC]], [[TRUNC1]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL]], [[TRUNC2]]
- ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC]], [[TRUNC1]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL]], [[TRUNC2]]
+ ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX10-LABEL: name: test_fmad_s16_denorm_flags
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC]], [[TRUNC1]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL]], [[TRUNC2]]
- ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr1
- %3:_(s16) = G_TRUNC %0
- %4:_(s16) = G_TRUNC %1
- %5:_(s16) = G_TRUNC %2
- %6:_(s16) = nnan G_FMAD %3, %4, %5
- %7:_(s32) = G_ANYEXT %6
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[COPY2]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC]], [[TRUNC1]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL]], [[TRUNC2]]
+ ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(i32) = COPY $vgpr1
+ %3:_(f16) = G_TRUNC %0
+ %4:_(f16) = G_TRUNC %1
+ %5:_(f16) = G_TRUNC %2
+ %6:_(f16) = nnan G_FMAD %3, %4, %5
+ %7:_(i32) = G_ANYEXT %6
$vgpr0 = COPY %7
...
@@ -532,104 +532,104 @@ body: |
; GFX6-LABEL: name: test_fmad_v2s16_denorm
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT6]], [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT6]], [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x f16>)
;
; GFX7-LABEL: name: test_fmad_v2s16_denorm
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX7-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC2]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC4]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[TRUNC3]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[FMUL1]], [[TRUNC5]]
- ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC2]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC4]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[TRUNC3]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[FMUL1]], [[TRUNC5]]
+ ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
+ ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x f16>)
;
; GFX10-LABEL: name: test_fmad_v2s16_denorm
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC2]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC4]]
- ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[TRUNC3]]
- ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[FMUL1]], [[TRUNC5]]
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = COPY $vgpr2
- %3:_(<2 x s16>) = G_FMAD %0, %1, %2
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC2]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC4]]
+ ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[TRUNC3]]
+ ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[FMUL1]], [[TRUNC5]]
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = COPY $vgpr2
+ %3:_(<2 x f16>) = G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -647,104 +647,104 @@ body: |
; GFX6-LABEL: name: test_fmad_v2s16_denorm_flags
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC4]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT4]], [[FPEXT5]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL1]](s32)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC5]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT6]], [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT4]], [[FPEXT5]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT6]], [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x f16>)
;
; GFX7-LABEL: name: test_fmad_v2s16_denorm_flags
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX7-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC]], [[TRUNC2]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL]], [[TRUNC4]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC1]], [[TRUNC3]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL1]], [[TRUNC5]]
- ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC]], [[TRUNC2]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL]], [[TRUNC4]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC1]], [[TRUNC3]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL1]], [[TRUNC5]]
+ ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
+ ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX7-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x f16>)
;
; GFX10-LABEL: name: test_fmad_v2s16_denorm_flags
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC]], [[TRUNC2]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL]], [[TRUNC4]]
- ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC1]], [[TRUNC3]]
- ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL1]], [[TRUNC5]]
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = COPY $vgpr2
- %3:_(<2 x s16>) = nnan G_FMAD %0, %1, %2
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC]], [[TRUNC2]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL]], [[TRUNC4]]
+ ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC1]], [[TRUNC3]]
+ ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL1]], [[TRUNC5]]
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = COPY $vgpr2
+ %3:_(<2 x f16>) = nnan G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -762,187 +762,187 @@ body: |
; GFX6-LABEL: name: test_fmad_v4s16_denorm
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX6-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC8]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL1]](s32)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC9]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FPEXT6]], [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC6]](s16)
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT8]], [[FPEXT9]]
- ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL2]](s32)
- ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC4]](s16)
- ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC10]](s16)
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FPEXT10]], [[FPEXT11]]
- ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD2]](s32)
- ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC7]](s16)
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT12]], [[FPEXT13]]
- ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL3]](s32)
- ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC6]](s16)
- ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC11]](s16)
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FPEXT14]], [[FPEXT15]]
- ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD3]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC8]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT4]], [[FPEXT5]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC9]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FPEXT6]], [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT8]], [[FPEXT9]]
+ ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL2]](f32)
+ ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC4]](f16)
+ ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC10]](f16)
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FPEXT10]], [[FPEXT11]]
+ ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD2]](f32)
+ ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT12]], [[FPEXT13]]
+ ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMUL3]](f32)
+ ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(f32) = G_FPEXT [[FPTRUNC6]](f16)
+ ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC11]](f16)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FPEXT14]], [[FPEXT15]]
+ ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD3]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](s16)
- ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC7]](s16)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](f16)
+ ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC7]](f16)
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x f16>), [[BITCAST7]](<2 x f16>)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX7-LABEL: name: test_fmad_v4s16_denorm
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX7-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX7-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX7-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX7-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX7-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX7-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX7-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC4]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC8]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[TRUNC5]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[FMUL1]], [[TRUNC9]]
- ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[TRUNC6]]
- ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[FMUL2]], [[TRUNC10]]
- ; GFX7-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[TRUNC7]]
- ; GFX7-NEXT: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[FMUL3]], [[TRUNC11]]
- ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX7-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC4]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC8]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[TRUNC5]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[FMUL1]], [[TRUNC9]]
+ ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[TRUNC6]]
+ ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[FMUL2]], [[TRUNC10]]
+ ; GFX7-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[TRUNC7]]
+ ; GFX7-NEXT: [[FADD3:%[0-9]+]]:_(f16) = G_FADD [[FMUL3]], [[TRUNC11]]
+ ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX7-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX7-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](s16)
- ; GFX7-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FADD3]](s16)
+ ; GFX7-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX7-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](f16)
+ ; GFX7-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FADD3]](f16)
; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX7-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX7-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX7-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x f16>), [[BITCAST7]](<2 x f16>)
+ ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX10-LABEL: name: test_fmad_v4s16_denorm
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX10-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX10-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX10-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX10-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC4]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC8]]
- ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[TRUNC5]]
- ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s16) = G_FADD [[FMUL1]], [[TRUNC9]]
- ; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[TRUNC6]]
- ; GFX10-NEXT: [[FADD2:%[0-9]+]]:_(s16) = G_FADD [[FMUL2]], [[TRUNC10]]
- ; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[TRUNC7]]
- ; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(s16) = G_FADD [[FMUL3]], [[TRUNC11]]
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD2]](s16), [[FADD3]](s16)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
- %2:_(<4 x s16>) = COPY $vgpr4_vgpr5
- %3:_(<4 x s16>) = G_FMAD %0, %1, %2
+ ; GFX10-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[TRUNC4]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[FMUL]], [[TRUNC8]]
+ ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[TRUNC5]]
+ ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(f16) = G_FADD [[FMUL1]], [[TRUNC9]]
+ ; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[TRUNC6]]
+ ; GFX10-NEXT: [[FADD2:%[0-9]+]]:_(f16) = G_FADD [[FMUL2]], [[TRUNC10]]
+ ; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[TRUNC7]]
+ ; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f16) = G_FADD [[FMUL3]], [[TRUNC11]]
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD2]](f16), [[FADD3]](f16)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ %2:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ %3:_(<4 x f16>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
@@ -961,187 +961,187 @@ body: |
; GFX6-LABEL: name: test_fmad_v4s16_denorm_flags
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX6-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX6-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX6-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX6-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX6-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX6-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX6-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC4]](s16)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT]], [[FPEXT1]]
- ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL]](s32)
- ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC]](s16)
- ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC8]](s16)
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT2]], [[FPEXT3]]
- ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD]](s32)
- ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC1]](s16)
- ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC5]](s16)
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT4]], [[FPEXT5]]
- ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL1]](s32)
- ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC9]](s16)
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT6]], [[FPEXT7]]
- ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD1]](s32)
- ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC2]](s16)
- ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC6]](s16)
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT8]], [[FPEXT9]]
- ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL2]](s32)
- ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC4]](s16)
- ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC10]](s16)
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT10]], [[FPEXT11]]
- ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD2]](s32)
- ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC3]](s16)
- ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC7]](s16)
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = nnan G_FMUL [[FPEXT12]], [[FPEXT13]]
- ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FMUL3]](s32)
- ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(s32) = nnan G_FPEXT [[FPTRUNC6]](s16)
- ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC11]](s16)
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = nnan G_FADD [[FPEXT14]], [[FPEXT15]]
- ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(s16) = nnan G_FPTRUNC [[FADD3]](s32)
- ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
- ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; GFX6-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX6-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC4]](f16)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT]], [[FPEXT1]]
+ ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL]](f32)
+ ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC]](f16)
+ ; GFX6-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC8]](f16)
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT2]], [[FPEXT3]]
+ ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD]](f32)
+ ; GFX6-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC1]](f16)
+ ; GFX6-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC5]](f16)
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT4]], [[FPEXT5]]
+ ; GFX6-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL1]](f32)
+ ; GFX6-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC9]](f16)
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT6]], [[FPEXT7]]
+ ; GFX6-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD1]](f32)
+ ; GFX6-NEXT: [[FPEXT8:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC2]](f16)
+ ; GFX6-NEXT: [[FPEXT9:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC6]](f16)
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT8]], [[FPEXT9]]
+ ; GFX6-NEXT: [[FPTRUNC4:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL2]](f32)
+ ; GFX6-NEXT: [[FPEXT10:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC4]](f16)
+ ; GFX6-NEXT: [[FPEXT11:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC10]](f16)
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT10]], [[FPEXT11]]
+ ; GFX6-NEXT: [[FPTRUNC5:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD2]](f32)
+ ; GFX6-NEXT: [[FPEXT12:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC3]](f16)
+ ; GFX6-NEXT: [[FPEXT13:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC7]](f16)
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = nnan G_FMUL [[FPEXT12]], [[FPEXT13]]
+ ; GFX6-NEXT: [[FPTRUNC6:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FMUL3]](f32)
+ ; GFX6-NEXT: [[FPEXT14:%[0-9]+]]:_(f32) = nnan G_FPEXT [[FPTRUNC6]](f16)
+ ; GFX6-NEXT: [[FPEXT15:%[0-9]+]]:_(f32) = nnan G_FPEXT [[TRUNC11]](f16)
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = nnan G_FADD [[FPEXT14]], [[FPEXT15]]
+ ; GFX6-NEXT: [[FPTRUNC7:%[0-9]+]]:_(f16) = nnan G_FPTRUNC [[FADD3]](f32)
+ ; GFX6-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
+ ; GFX6-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](s16)
- ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC7]](s16)
+ ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX6-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC5]](f16)
+ ; GFX6-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC7]](f16)
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x f16>), [[BITCAST7]](<2 x f16>)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX7-LABEL: name: test_fmad_v4s16_denorm_flags
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX7-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX7-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX7-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX7-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX7-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX7-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX7-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX7-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX7-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX7-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX7-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX7-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX7-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX7-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC]], [[TRUNC4]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL]], [[TRUNC8]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC1]], [[TRUNC5]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL1]], [[TRUNC9]]
- ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC2]], [[TRUNC6]]
- ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL2]], [[TRUNC10]]
- ; GFX7-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC3]], [[TRUNC7]]
- ; GFX7-NEXT: [[FADD3:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL3]], [[TRUNC11]]
- ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](s16)
- ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](s16)
+ ; GFX7-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC]], [[TRUNC4]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL]], [[TRUNC8]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC1]], [[TRUNC5]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL1]], [[TRUNC9]]
+ ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC2]], [[TRUNC6]]
+ ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL2]], [[TRUNC10]]
+ ; GFX7-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC3]], [[TRUNC7]]
+ ; GFX7-NEXT: [[FADD3:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL3]], [[TRUNC11]]
+ ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FADD]](f16)
+ ; GFX7-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FADD1]](f16)
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; GFX7-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; GFX7-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](s16)
- ; GFX7-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FADD3]](s16)
+ ; GFX7-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; GFX7-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FADD2]](f16)
+ ; GFX7-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FADD3]](f16)
; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; GFX7-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; GFX7-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; GFX7-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x f16>), [[BITCAST7]](<2 x f16>)
+ ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX10-LABEL: name: test_fmad_v4s16_denorm_flags
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX10-NEXT: {{ $}}
- ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr4_vgpr5
- ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX10-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX10-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX10-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; GFX10-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX10-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; GFX10-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
- ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32)
+ ; GFX10-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY2]](<4 x f16>)
+ ; GFX10-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC8:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST4]](i32)
; GFX10-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](i32)
- ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x s16>)
- ; GFX10-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](i32)
+ ; GFX10-NEXT: [[TRUNC9:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR4]](i32)
+ ; GFX10-NEXT: [[BITCAST5:%[0-9]+]]:_(i32) = G_BITCAST [[UV5]](<2 x f16>)
+ ; GFX10-NEXT: [[TRUNC10:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST5]](i32)
; GFX10-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST5]], [[C]](i32)
- ; GFX10-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](i32)
- ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC]], [[TRUNC4]]
- ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL]], [[TRUNC8]]
- ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC1]], [[TRUNC5]]
- ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL1]], [[TRUNC9]]
- ; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC2]], [[TRUNC6]]
- ; GFX10-NEXT: [[FADD2:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL2]], [[TRUNC10]]
- ; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = nnan G_FMUL [[TRUNC3]], [[TRUNC7]]
- ; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(s16) = nnan G_FADD [[FMUL3]], [[TRUNC11]]
- ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD]](s16), [[FADD1]](s16)
- ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[FADD2]](s16), [[FADD3]](s16)
- ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
- %2:_(<4 x s16>) = COPY $vgpr4_vgpr5
- %3:_(<4 x s16>) = nnan G_FMAD %0, %1, %2
+ ; GFX10-NEXT: [[TRUNC11:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR5]](i32)
+ ; GFX10-NEXT: [[FMUL:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC]], [[TRUNC4]]
+ ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL]], [[TRUNC8]]
+ ; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC1]], [[TRUNC5]]
+ ; GFX10-NEXT: [[FADD1:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL1]], [[TRUNC9]]
+ ; GFX10-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC2]], [[TRUNC6]]
+ ; GFX10-NEXT: [[FADD2:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL2]], [[TRUNC10]]
+ ; GFX10-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = nnan G_FMUL [[TRUNC3]], [[TRUNC7]]
+ ; GFX10-NEXT: [[FADD3:%[0-9]+]]:_(f16) = nnan G_FADD [[FMUL3]], [[TRUNC11]]
+ ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD]](f16), [[FADD1]](f16)
+ ; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[FADD2]](f16), [[FADD3]](f16)
+ ; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ %2:_(<4 x f16>) = COPY $vgpr4_vgpr5
+ %3:_(<4 x f16>) = nnan G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
index df70bc6207ea3..c8e1a65a282a8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
@@ -20,40 +20,43 @@ body: |
; GFX6-LABEL: name: test_fmad_s32_flush
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMAD]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FMAD]](f32)
+ ;
; GFX7-LABEL: name: test_fmad_s32_flush
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
- ; GFX7-NEXT: $vgpr0 = COPY [[FMAD]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
+ ; GFX7-NEXT: $vgpr0 = COPY [[FMAD]](f32)
+ ;
; GFX101-LABEL: name: test_fmad_s32_flush
; GFX101: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
- ; GFX101-NEXT: $vgpr0 = COPY [[FMAD]](s32)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
+ ; GFX101-NEXT: $vgpr0 = COPY [[FMAD]](f32)
+ ;
; GFX103-LABEL: name: test_fmad_s32_flush
; GFX103: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr2
- %3:_(s32) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = COPY $vgpr2
+ %3:_(f32) = G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -71,40 +74,43 @@ body: |
; GFX6-LABEL: name: test_fmad_s32_flags_flush
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMAD]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(f32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FMAD]](f32)
+ ;
; GFX7-LABEL: name: test_fmad_s32_flags_flush
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
- ; GFX7-NEXT: $vgpr0 = COPY [[FMAD]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
+ ; GFX7-NEXT: $vgpr0 = COPY [[FMAD]](f32)
+ ;
; GFX101-LABEL: name: test_fmad_s32_flags_flush
; GFX101: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
- ; GFX101-NEXT: $vgpr0 = COPY [[FMAD]](s32)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(f32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
+ ; GFX101-NEXT: $vgpr0 = COPY [[FMAD]](f32)
+ ;
; GFX103-LABEL: name: test_fmad_s32_flags_flush
; GFX103: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[COPY1]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL]], [[COPY2]]
- ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr2
- %3:_(s32) = nnan G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[COPY1]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL]], [[COPY2]]
+ ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = COPY $vgpr2
+ %3:_(f32) = nnan G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -122,61 +128,64 @@ body: |
; GFX6-LABEL: name: test_fmad_v2s32_flush
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
- ; GFX6-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV3]], [[UV5]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
+ ; GFX6-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV3]], [[UV5]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ ;
; GFX7-LABEL: name: test_fmad_v2s32_flush
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
- ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV3]], [[UV5]]
- ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32)
- ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
+ ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV3]], [[UV5]]
+ ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32)
+ ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ ;
; GFX101-LABEL: name: test_fmad_v2s32_flush
; GFX101: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX101-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX101-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
- ; GFX101-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV3]], [[UV5]]
- ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32)
- ; GFX101-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX101-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX101-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV2]], [[UV4]]
+ ; GFX101-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV3]], [[UV5]]
+ ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32)
+ ; GFX101-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ ;
; GFX103-LABEL: name: test_fmad_v2s32_flush
; GFX103: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX103-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX103-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV2]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV4]]
- ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
- ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV5]]
- ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX103-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = COPY $vgpr4_vgpr5
- %3:_(<2 x s32>) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX103-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX103-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV2]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV4]]
+ ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV3]]
+ ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV5]]
+ ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX103-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ %3:_(<2 x f32>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
@@ -194,66 +203,69 @@ body: |
; GFX6-LABEL: name: test_fmad_v3s32_flush
; GFX6: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX6-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
- ; GFX6-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV4]], [[UV7]]
- ; GFX6-NEXT: [[FMAD2:%[0-9]+]]:_(s32) = G_FMAD [[UV2]], [[UV5]], [[UV8]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32), [[FMAD2]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX6-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
+ ; GFX6-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV4]], [[UV7]]
+ ; GFX6-NEXT: [[FMAD2:%[0-9]+]]:_(f32) = G_FMAD [[UV2]], [[UV5]], [[UV8]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32), [[FMAD2]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ ;
; GFX7-LABEL: name: test_fmad_v3s32_flush
; GFX7: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX7-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX7-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
- ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV4]], [[UV7]]
- ; GFX7-NEXT: [[FMAD2:%[0-9]+]]:_(s32) = G_FMAD [[UV2]], [[UV5]], [[UV8]]
- ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32), [[FMAD2]](s32)
- ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX7-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX7-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
+ ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV4]], [[UV7]]
+ ; GFX7-NEXT: [[FMAD2:%[0-9]+]]:_(f32) = G_FMAD [[UV2]], [[UV5]], [[UV8]]
+ ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32), [[FMAD2]](f32)
+ ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ ;
; GFX101-LABEL: name: test_fmad_v3s32_flush
; GFX101: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX101-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX101-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX101-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
- ; GFX101-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV4]], [[UV7]]
- ; GFX101-NEXT: [[FMAD2:%[0-9]+]]:_(s32) = G_FMAD [[UV2]], [[UV5]], [[UV8]]
- ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32), [[FMAD2]](s32)
- ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX101-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX101-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX101-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV3]], [[UV6]]
+ ; GFX101-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV4]], [[UV7]]
+ ; GFX101-NEXT: [[FMAD2:%[0-9]+]]:_(f32) = G_FMAD [[UV2]], [[UV5]], [[UV8]]
+ ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32), [[FMAD2]](f32)
+ ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ ;
; GFX103-LABEL: name: test_fmad_v3s32_flush
; GFX103: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX103-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX103-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX103-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV3]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV6]]
- ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV4]]
- ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV7]]
- ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
- ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV8]]
- ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
- ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- %2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- %3:_(<3 x s32>) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX103-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX103-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX103-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV3]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV6]]
+ ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV4]]
+ ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV7]]
+ ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV5]]
+ ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV8]]
+ ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32)
+ ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ %2:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ %3:_(<3 x f32>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1_vgpr2 = COPY %3
...
@@ -271,71 +283,74 @@ body: |
; GFX6-LABEL: name: test_fmad_v4s32_flush
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV4]], [[UV8]]
- ; GFX6-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV5]], [[UV9]]
- ; GFX6-NEXT: [[FMAD2:%[0-9]+]]:_(s32) = G_FMAD [[UV2]], [[UV6]], [[UV10]]
- ; GFX6-NEXT: [[FMAD3:%[0-9]+]]:_(s32) = G_FMAD [[UV3]], [[UV7]], [[UV11]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32), [[FMAD2]](s32), [[FMAD3]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX6-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV4]], [[UV8]]
+ ; GFX6-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV5]], [[UV9]]
+ ; GFX6-NEXT: [[FMAD2:%[0-9]+]]:_(f32) = G_FMAD [[UV2]], [[UV6]], [[UV10]]
+ ; GFX6-NEXT: [[FMAD3:%[0-9]+]]:_(f32) = G_FMAD [[UV3]], [[UV7]], [[UV11]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32), [[FMAD2]](f32), [[FMAD3]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ ;
; GFX7-LABEL: name: test_fmad_v4s32_flush
; GFX7: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX7-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV4]], [[UV8]]
- ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV5]], [[UV9]]
- ; GFX7-NEXT: [[FMAD2:%[0-9]+]]:_(s32) = G_FMAD [[UV2]], [[UV6]], [[UV10]]
- ; GFX7-NEXT: [[FMAD3:%[0-9]+]]:_(s32) = G_FMAD [[UV3]], [[UV7]], [[UV11]]
- ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32), [[FMAD2]](s32), [[FMAD3]](s32)
- ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX7-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX7-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV4]], [[UV8]]
+ ; GFX7-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV5]], [[UV9]]
+ ; GFX7-NEXT: [[FMAD2:%[0-9]+]]:_(f32) = G_FMAD [[UV2]], [[UV6]], [[UV10]]
+ ; GFX7-NEXT: [[FMAD3:%[0-9]+]]:_(f32) = G_FMAD [[UV3]], [[UV7]], [[UV11]]
+ ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32), [[FMAD2]](f32), [[FMAD3]](f32)
+ ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ ;
; GFX101-LABEL: name: test_fmad_v4s32_flush
; GFX101: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX101-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX101-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[UV]], [[UV4]], [[UV8]]
- ; GFX101-NEXT: [[FMAD1:%[0-9]+]]:_(s32) = G_FMAD [[UV1]], [[UV5]], [[UV9]]
- ; GFX101-NEXT: [[FMAD2:%[0-9]+]]:_(s32) = G_FMAD [[UV2]], [[UV6]], [[UV10]]
- ; GFX101-NEXT: [[FMAD3:%[0-9]+]]:_(s32) = G_FMAD [[UV3]], [[UV7]], [[UV11]]
- ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FMAD]](s32), [[FMAD1]](s32), [[FMAD2]](s32), [[FMAD3]](s32)
- ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX101-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX101-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX101-NEXT: [[FMAD:%[0-9]+]]:_(f32) = G_FMAD [[UV]], [[UV4]], [[UV8]]
+ ; GFX101-NEXT: [[FMAD1:%[0-9]+]]:_(f32) = G_FMAD [[UV1]], [[UV5]], [[UV9]]
+ ; GFX101-NEXT: [[FMAD2:%[0-9]+]]:_(f32) = G_FMAD [[UV2]], [[UV6]], [[UV10]]
+ ; GFX101-NEXT: [[FMAD3:%[0-9]+]]:_(f32) = G_FMAD [[UV3]], [[UV7]], [[UV11]]
+ ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FMAD]](f32), [[FMAD1]](f32), [[FMAD2]](f32), [[FMAD3]](f32)
+ ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ ;
; GFX103-LABEL: name: test_fmad_v4s32_flush
; GFX103: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX103-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX103-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV4]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV8]]
- ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV5]]
- ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV9]]
- ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV6]]
- ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV10]]
- ; GFX103-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[UV3]], [[UV7]]
- ; GFX103-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[UV11]]
- ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32), [[FADD3]](s32)
- ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- %2:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %3:_(<4 x s32>) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX103-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX103-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV4]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV8]]
+ ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV5]]
+ ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV9]]
+ ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV6]]
+ ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV10]]
+ ; GFX103-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[UV7]]
+ ; GFX103-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[UV11]]
+ ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32), [[FADD3]](f32)
+ ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ %0:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ %2:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %3:_(<4 x f32>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
@@ -353,43 +368,46 @@ body: |
; GFX6-LABEL: name: test_fmad_s32_denorm
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ ;
; GFX7-LABEL: name: test_fmad_s32_denorm
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; GFX7-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; GFX7-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ ;
; GFX101-LABEL: name: test_fmad_s32_denorm
; GFX101: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; GFX101-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; GFX101-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ ;
; GFX103-LABEL: name: test_fmad_s32_denorm
; GFX103: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
- ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr2
- %3:_(s32) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[COPY1]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[COPY2]]
+ ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = COPY $vgpr2
+ %3:_(f32) = G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -407,43 +425,46 @@ body: |
; GFX6-LABEL: name: test_fmad_s32_flags_denorm
; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[COPY1]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL]], [[COPY2]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[COPY1]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL]], [[COPY2]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ ;
; GFX7-LABEL: name: test_fmad_s32_flags_denorm
; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[COPY1]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL]], [[COPY2]]
- ; GFX7-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[COPY1]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL]], [[COPY2]]
+ ; GFX7-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ ;
; GFX101-LABEL: name: test_fmad_s32_flags_denorm
; GFX101: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[COPY1]]
- ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL]], [[COPY2]]
- ; GFX101-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[COPY1]]
+ ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL]], [[COPY2]]
+ ; GFX101-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ ;
; GFX103-LABEL: name: test_fmad_s32_flags_denorm
; GFX103: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[COPY1]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[FMUL]], [[COPY2]]
- ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = COPY $vgpr2
- %3:_(s32) = nnan G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[COPY1]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[FMUL]], [[COPY2]]
+ ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = COPY $vgpr2
+ %3:_(f32) = nnan G_FMAD %0, %1, %2
$vgpr0 = COPY %3
...
@@ -461,67 +482,70 @@ body: |
; GFX6-LABEL: name: test_fmad_v2s32_denorm
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV2]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV4]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV5]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV2]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV4]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV3]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV5]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ ;
; GFX7-LABEL: name: test_fmad_v2s32_denorm
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV2]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV4]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV5]]
- ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX7-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV2]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV4]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV3]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV5]]
+ ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ ;
; GFX101-LABEL: name: test_fmad_v2s32_denorm
; GFX101: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX101-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX101-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV2]]
- ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV4]]
- ; GFX101-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
- ; GFX101-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV5]]
- ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX101-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX101-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX101-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV2]]
+ ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV4]]
+ ; GFX101-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV3]]
+ ; GFX101-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV5]]
+ ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX101-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ ;
; GFX103-LABEL: name: test_fmad_v2s32_denorm
; GFX103: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
- ; GFX103-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX103-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV2]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV4]]
- ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
- ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV5]]
- ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX103-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = COPY $vgpr4_vgpr5
- %3:_(<2 x s32>) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ ; GFX103-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX103-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<2 x f32>)
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV2]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV4]]
+ ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV3]]
+ ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV5]]
+ ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX103-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = COPY $vgpr4_vgpr5
+ %3:_(<2 x f32>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
@@ -539,75 +563,78 @@ body: |
; GFX6-LABEL: name: test_fmad_v3s32_denorm
; GFX6: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX6-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV3]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV6]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV4]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV7]]
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV8]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX6-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV3]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV6]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV4]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV7]]
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV5]]
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV8]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ ;
; GFX7-LABEL: name: test_fmad_v3s32_denorm
; GFX7: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX7-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX7-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV3]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV6]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV4]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV7]]
- ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
- ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV8]]
- ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
- ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX7-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX7-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV3]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV6]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV4]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV7]]
+ ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV5]]
+ ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV8]]
+ ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32)
+ ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ ;
; GFX101-LABEL: name: test_fmad_v3s32_denorm
; GFX101: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX101-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX101-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX101-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV3]]
- ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV6]]
- ; GFX101-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV4]]
- ; GFX101-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV7]]
- ; GFX101-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
- ; GFX101-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV8]]
- ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
- ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX101-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX101-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX101-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV3]]
+ ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV6]]
+ ; GFX101-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV4]]
+ ; GFX101-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV7]]
+ ; GFX101-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV5]]
+ ; GFX101-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV8]]
+ ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32)
+ ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ ;
; GFX103-LABEL: name: test_fmad_v3s32_denorm
; GFX103: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- ; GFX103-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX103-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
- ; GFX103-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV3]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV6]]
- ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV4]]
- ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV7]]
- ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
- ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV8]]
- ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
- ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
- %2:_(<3 x s32>) = COPY $vgpr6_vgpr7_vgpr8
- %3:_(<3 x s32>) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ ; GFX103-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX103-NEXT: [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<3 x f32>)
+ ; GFX103-NEXT: [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32), [[UV8:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<3 x f32>)
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV3]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV6]]
+ ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV4]]
+ ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV7]]
+ ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV5]]
+ ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV8]]
+ ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32)
+ ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = COPY $vgpr3_vgpr4_vgpr5
+ %2:_(<3 x f32>) = COPY $vgpr6_vgpr7_vgpr8
+ %3:_(<3 x f32>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1_vgpr2 = COPY %3
...
@@ -625,82 +652,85 @@ body: |
; GFX6-LABEL: name: test_fmad_v4s32_denorm
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV4]]
- ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV8]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV5]]
- ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV9]]
- ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV6]]
- ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV10]]
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[UV3]], [[UV7]]
- ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[UV11]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32), [[FADD3]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV4]]
+ ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV8]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV5]]
+ ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV9]]
+ ; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV6]]
+ ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV10]]
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[UV7]]
+ ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[UV11]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32), [[FADD3]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ ;
; GFX7-LABEL: name: test_fmad_v4s32_denorm
; GFX7: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX7-NEXT: {{ $}}
- ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX7-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV4]]
- ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV8]]
- ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV5]]
- ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV9]]
- ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV6]]
- ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV10]]
- ; GFX7-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[UV3]], [[UV7]]
- ; GFX7-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[UV11]]
- ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32), [[FADD3]](s32)
- ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX7-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX7-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX7-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX7-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV4]]
+ ; GFX7-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV8]]
+ ; GFX7-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV5]]
+ ; GFX7-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV9]]
+ ; GFX7-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV6]]
+ ; GFX7-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV10]]
+ ; GFX7-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[UV7]]
+ ; GFX7-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[UV11]]
+ ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32), [[FADD3]](f32)
+ ; GFX7-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ ;
; GFX101-LABEL: name: test_fmad_v4s32_denorm
; GFX101: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX101-NEXT: {{ $}}
- ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX101-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX101-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV4]]
- ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV8]]
- ; GFX101-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV5]]
- ; GFX101-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV9]]
- ; GFX101-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV6]]
- ; GFX101-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV10]]
- ; GFX101-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[UV3]], [[UV7]]
- ; GFX101-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[UV11]]
- ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32), [[FADD3]](s32)
- ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; GFX101-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX101-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX101-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX101-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX101-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX101-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX101-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV4]]
+ ; GFX101-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV8]]
+ ; GFX101-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV5]]
+ ; GFX101-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV9]]
+ ; GFX101-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV6]]
+ ; GFX101-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV10]]
+ ; GFX101-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[UV7]]
+ ; GFX101-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[UV11]]
+ ; GFX101-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32), [[FADD3]](f32)
+ ; GFX101-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ ;
; GFX103-LABEL: name: test_fmad_v4s32_denorm
; GFX103: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX103-NEXT: {{ $}}
- ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; GFX103-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; GFX103-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[UV4]]
- ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV8]]
- ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV5]]
- ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[FMUL1]], [[UV9]]
- ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV6]]
- ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL2]], [[UV10]]
- ; GFX103-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[UV3]], [[UV7]]
- ; GFX103-NEXT: [[FADD3:%[0-9]+]]:_(s32) = G_FADD [[FMUL3]], [[UV11]]
- ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32), [[FADD3]](s32)
- ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- %2:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %3:_(<4 x s32>) = G_FMAD %0, %1, %2
+ ; GFX103-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX103-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; GFX103-NEXT: [[COPY2:%[0-9]+]]:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; GFX103-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<4 x f32>)
+ ; GFX103-NEXT: [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32), [[UV6:%[0-9]+]]:_(f32), [[UV7:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<4 x f32>)
+ ; GFX103-NEXT: [[UV8:%[0-9]+]]:_(f32), [[UV9:%[0-9]+]]:_(f32), [[UV10:%[0-9]+]]:_(f32), [[UV11:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY2]](<4 x f32>)
+ ; GFX103-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[UV4]]
+ ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FMUL]], [[UV8]]
+ ; GFX103-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[UV5]]
+ ; GFX103-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[FMUL1]], [[UV9]]
+ ; GFX103-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[UV6]]
+ ; GFX103-NEXT: [[FADD2:%[0-9]+]]:_(f32) = G_FADD [[FMUL2]], [[UV10]]
+ ; GFX103-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[UV3]], [[UV7]]
+ ; GFX103-NEXT: [[FADD3:%[0-9]+]]:_(f32) = G_FADD [[FMUL3]], [[UV11]]
+ ; GFX103-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32), [[FADD2]](f32), [[FADD3]](f32)
+ ; GFX103-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x f32>)
+ %0:_(<4 x f32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x f32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ %2:_(<4 x f32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %3:_(<4 x f32>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
index d103869adf9c5..1ef4b0d3da095 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
@@ -18,16 +18,16 @@ body: |
; CHECK-LABEL: name: test_fmad_s64_flush
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = COPY $vgpr4_vgpr5
- %3:_(s64) = G_FMAD %0, %1, %2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY $vgpr4_vgpr5
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[FMUL]], [[COPY2]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = COPY $vgpr4_vgpr5
+ %3:_(f64) = G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
@@ -45,22 +45,22 @@ body: |
; CHECK-LABEL: name: test_fmad_v2s64_flush
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[UV2]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[UV4]]
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[UV3]]
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FMUL1]], [[UV5]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- %2:_(<2 x s64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %3:_(<2 x s64>) = G_FMAD %0, %1, %2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f64), [[UV5:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY2]](<2 x f64>)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[UV2]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[FMUL]], [[UV4]]
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[UV3]]
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[FMUL1]], [[UV5]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD]](f64), [[FADD1]](f64)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ %2:_(<2 x f64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %3:_(<2 x f64>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
@@ -78,16 +78,16 @@ body: |
; CHECK-LABEL: name: test_fmad_s64_denorm
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = COPY $vgpr4_vgpr5
- %3:_(s64) = G_FMAD %0, %1, %2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY $vgpr4_vgpr5
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[FMUL]], [[COPY2]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = COPY $vgpr4_vgpr5
+ %3:_(f64) = G_FMAD %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...
@@ -105,21 +105,21 @@ body: |
; CHECK-LABEL: name: test_fmad_v2s64_denorm
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY2]](<2 x s64>)
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[UV2]]
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[UV4]]
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[UV3]]
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FMUL1]], [[UV5]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
- ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
- %2:_(<2 x s64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
- %3:_(<2 x s64>) = G_FMAD %0, %1, %2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(f64), [[UV3:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY1]](<2 x f64>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(f64), [[UV5:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY2]](<2 x f64>)
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[UV2]]
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[FMUL]], [[UV4]]
+ ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[UV3]]
+ ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[FMUL1]], [[UV5]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD]](f64), [[FADD1]](f64)
+ ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
+ %2:_(<2 x f64>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
+ %3:_(<2 x f64>) = G_FMAD %0, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
index 13006ac161b21..6e458d1e30aa8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir
@@ -11,37 +11,37 @@ body: |
; GFX9-LABEL: name: test_fmaximum_f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[TRUNC]], [[TRUNC1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[SELECT]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[TRUNC]], [[TRUNC1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](f16), [[TRUNC1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f16) = COPY [[SELECT]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[COPY2]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fmaximum_f16
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s16) = G_FMAXIMUM [[TRUNC]], [[TRUNC1]]
- ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAXIMUM]](s16)
- ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f16) = G_FMAXIMUM [[TRUNC]], [[TRUNC1]]
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMAXIMUM]](f16)
+ ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0(s32)
- %2:_(s32) = COPY $vgpr1
- %3:_(s16) = G_TRUNC %2(s32)
- %4:_(s16) = G_FMAXIMUM %1, %3
- %5:_(s32) = G_ANYEXT %4(s16)
- $vgpr0 = COPY %5(s32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f16) = G_TRUNC %0(i32)
+ %2:_(i32) = COPY $vgpr1
+ %3:_(f16) = G_TRUNC %2(i32)
+ %4:_(f16) = G_FMAXIMUM %1, %3
+ %5:_(i32) = G_ANYEXT %4(f16)
+ $vgpr0 = COPY %5(i32)
SI_RETURN implicit $vgpr0
...
---
@@ -53,28 +53,28 @@ body: |
; GFX9-LABEL: name: test_fmaximum_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f32), [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fmaximum_f32
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f32) = G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMAXIMUM %0, %1
- $vgpr0 = COPY %2(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMAXIMUM %0, %1
+ $vgpr0 = COPY %2(f32)
SI_RETURN implicit $vgpr0
...
---
@@ -86,28 +86,28 @@ body: |
; GFX9-LABEL: name: test_fmaximum_f64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f64) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f64), [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY [[SELECT]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](f64)
; GFX9-NEXT: SI_RETURN implicit $vgpr0_vgpr1
;
; GFX12-LABEL: name: test_fmaximum_f64
; GFX12: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s64) = G_FMAXIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUM]](s64)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f64) = G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUM]](f64)
; GFX12-NEXT: SI_RETURN implicit $vgpr0_vgpr1
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FMAXIMUM %0, %1
- $vgpr0_vgpr1 = COPY %2(s64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FMAXIMUM %0, %1
+ $vgpr0_vgpr1 = COPY %2(f64)
SI_RETURN implicit $vgpr0_vgpr1
...
---
@@ -119,44 +119,44 @@ body: |
; GFX9-LABEL: name: test_fmaximum_v2f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC2]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC1]](s16), [[TRUNC3]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
- ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](f16), [[TRUNC2]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC1]](f16), [[TRUNC3]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half +qnan
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[TRUNC4]], [[C1]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[TRUNC5]], [[C1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SELECT]](s16), [[SELECT1]](s16)
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](<2 x s16>)
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[TRUNC4]], [[C1]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[TRUNC5]], [[C1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[SELECT]](f16), [[SELECT1]](f16)
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY [[BUILD_VECTOR]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](<2 x f16>)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fmaximum_v2f16
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<2 x s16>) = G_FMAXIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](<2 x s16>)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<2 x f16>) = G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](<2 x f16>)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = G_FMAXIMUM %0, %1
- $vgpr0 = COPY %2(<2 x s16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = G_FMAXIMUM %0, %1
+ $vgpr0 = COPY %2(<2 x f16>)
SI_RETURN implicit $vgpr0
...
---
@@ -168,45 +168,45 @@ body: |
; GFX9-LABEL: name: test_fmaximum_v2f32
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY2]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY2]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY1]], [[COPY3]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY1]](s32), [[COPY3]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](i1), [[FMAXNUM_IEEE1]], [[C]]
- ; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]](s32)
- ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $vgpr3
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY2]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f32), [[COPY2]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY [[SELECT]](f32)
+ ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY1]], [[COPY3]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY1]](f32), [[COPY3]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](i1), [[FMAXNUM_IEEE1]], [[C]]
+ ; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]](f32)
+ ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
;
; GFX12-LABEL: name: test_fmaximum_v2f32
; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY]], [[COPY2]]
- ; GFX12-NEXT: [[FMAXIMUM1:%[0-9]+]]:_(s32) = G_FMAXIMUM [[COPY1]], [[COPY3]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
- ; GFX12-NEXT: $vgpr1 = COPY [[FMAXIMUM1]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $vgpr3
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f32) = G_FMAXIMUM [[COPY]], [[COPY2]]
+ ; GFX12-NEXT: [[FMAXIMUM1:%[0-9]+]]:_(f32) = G_FMAXIMUM [[COPY1]], [[COPY3]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](f32)
+ ; GFX12-NEXT: $vgpr1 = COPY [[FMAXIMUM1]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(<2 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32)
- %3:_(s32) = COPY $vgpr2
- %4:_(s32) = COPY $vgpr3
- %5:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32)
- %6:_(<2 x s32>) = G_FMAXIMUM %2, %5
- %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(<2 x s32>)
- $vgpr0 = COPY %7(s32)
- $vgpr1 = COPY %8(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(<2 x f32>) = G_BUILD_VECTOR %0(f32), %1(f32)
+ %3:_(f32) = COPY $vgpr2
+ %4:_(f32) = COPY $vgpr3
+ %5:_(<2 x f32>) = G_BUILD_VECTOR %3(f32), %4(f32)
+ %6:_(<2 x f32>) = G_FMAXIMUM %2, %5
+ %7:_(f32), %8:_(f32) = G_UNMERGE_VALUES %6(<2 x f32>)
+ $vgpr0 = COPY %7(f32)
+ $vgpr1 = COPY %8(f32)
SI_RETURN implicit $vgpr0, implicit $vgpr1
...
---
@@ -218,28 +218,28 @@ body: |
; GFX9-LABEL: name: test_fmaximum_nsz_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f32), [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[FMAXNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fmaximum_nsz_f32
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = nsz G_FMAXIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f32) = nsz G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nsz G_FMAXIMUM %0, %1
- $vgpr0 = COPY %2(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nsz G_FMAXIMUM %0, %1
+ $vgpr0 = COPY %2(f32)
SI_RETURN implicit $vgpr0
...
---
@@ -251,25 +251,25 @@ body: |
; GFX9-LABEL: name: test_fmaximum_nnan_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FMAXNUM_IEEE]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[FMAXNUM_IEEE]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fmaximum_nnan_f32
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = nnan G_FMAXIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMAXIMUM:%[0-9]+]]:_(f32) = nnan G_FMAXIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMAXIMUM]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nnan G_FMAXIMUM %0, %1
- $vgpr0 = COPY %2(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nnan G_FMAXIMUM %0, %1
+ $vgpr0 = COPY %2(f32)
SI_RETURN implicit $vgpr0
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
index f6ab150e89c09..1c6ab1487400d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
@@ -17,35 +17,35 @@ body: |
; SI-LABEL: name: test_fmaxnum_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -61,29 +61,29 @@ body: |
; SI-LABEL: name: test_fmaxnum_s32_ieee_mode_off
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FMAXNUM:%[0-9]+]]:_(f32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM]](f32)
;
; VI-LABEL: name: test_fmaxnum_s32_ieee_mode_off
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(f32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_s32_ieee_mode_off
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM:%[0-9]+]]:_(f32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -96,29 +96,29 @@ body: |
; SI-LABEL: name: test_fmaxnum_s32_nnan
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_s32_nnan
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nnan G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nnan G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -132,32 +132,32 @@ body: |
; SI-LABEL: name: test_fmaxnum_s32_nnan_lhs
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_s32_nnan_lhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan_lhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = nnan COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = nnan COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -171,32 +171,32 @@ body: |
; SI-LABEL: name: test_fmaxnum_s32_nnan_rhs
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_s32_nnan_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -209,29 +209,29 @@ body: |
; SI-LABEL: name: test_fmaxnum_s32_nnan_lhs_rhs
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_s32_nnan_lhs_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan_lhs_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = nnan COPY $vgpr0
- %1:_(s32) = nnan COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = nnan COPY $vgpr0
+ %1:_(f32) = nnan COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -244,35 +244,35 @@ body: |
; SI-LABEL: name: test_fmaxnum_s64
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](f64)
;
; VI-LABEL: name: test_fmaxnum_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](f64)
;
; GFX9-LABEL: name: test_fmaxnum_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FMAXNUM %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -285,48 +285,48 @@ body: |
; SI-LABEL: name: test_fmaxnum_s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fmaxnum_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAXNUM_IEEE]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMAXNUM_IEEE]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fmaxnum_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAXNUM_IEEE]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_TRUNC %1
- %4:_(s16) = G_FMAXNUM %2, %3
- %5:_(s32) = G_ANYEXT %4
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMAXNUM_IEEE]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(f16) = G_TRUNC %0
+ %3:_(f16) = G_TRUNC %1
+ %4:_(f16) = G_FMAXNUM %2, %3
+ %5:_(i32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
@@ -339,53 +339,53 @@ body: |
; SI-LABEL: name: test_fmaxnum_v2s32
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV2]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV1]]
- ; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV3]]
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](s32), [[FMAXNUM_IEEE1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV2]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV1]]
+ ; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV3]]
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](f32), [[FMAXNUM_IEEE1]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fmaxnum_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV2]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV3]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](s32), [[FMAXNUM_IEEE1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV2]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV3]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](f32), [[FMAXNUM_IEEE1]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fmaxnum_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV2]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV1]]
- ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV3]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](s32), [[FMAXNUM_IEEE1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV2]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV1]]
+ ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV3]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](f32), [[FMAXNUM_IEEE1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = G_FMAXNUM %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -398,71 +398,71 @@ body: |
; SI-LABEL: name: test_fmaxnum_v2s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
;
; VI-LABEL: name: test_fmaxnum_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC2]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC3]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC2]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC3]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
;
; GFX9-LABEL: name: test_fmaxnum_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -474,127 +474,127 @@ body: |
; SI-LABEL: name: test_fmaxnum_v3s16
; SI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; SI-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[UV3:%[0-9]+]]:_(<2 x f16>), [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<6 x f16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE1]](s32)
- ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT4]], [[FPEXT5]]
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE2]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE1]](f32)
+ ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT4]], [[FPEXT5]]
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE2]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C1]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C1]], [[SHL1]]
- ; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
+ ; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>), [[BITCAST6]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
;
; VI-LABEL: name: test_fmaxnum_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; VI-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[UV3:%[0-9]+]]:_(<2 x f16>), [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<6 x f16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC3]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC4]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC2]]
- ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC5]]
- ; VI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC3]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC4]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC2]]
+ ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC5]]
+ ; VI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE2]](s16)
+ ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE2]](f16)
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C1]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C1]], [[SHL1]]
- ; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
+ ; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>), [[BITCAST6]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
;
; GFX9-LABEL: name: test_fmaxnum_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV3]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV1]]
- ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV4]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(<2 x f16>), [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<6 x f16>)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV3]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV1]]
+ ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV4]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMAXNUM_IEEE]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FMAXNUM_IEEE1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- %0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- %2:_(<3 x s16>), %3:_(<3 x s16>) = G_UNMERGE_VALUES %0
- %4:_(<3 x s16>), %5:_(<3 x s16>) = G_UNMERGE_VALUES %1
- %6:_(<3 x s16>) = G_FMAXNUM %2, %4
- %7:_(<3 x s16>) = G_IMPLICIT_DEF
- %8:_(<6 x s16>) = G_CONCAT_VECTORS %6, %7
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FMAXNUM_IEEE1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[DEF]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>), [[BUILD_VECTOR2]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
+ %0:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ %2:_(<3 x f16>), %3:_(<3 x f16>) = G_UNMERGE_VALUES %0
+ %4:_(<3 x f16>), %5:_(<3 x f16>) = G_UNMERGE_VALUES %1
+ %6:_(<3 x f16>) = G_FMAXNUM %2, %4
+ %7:_(<3 x f16>) = G_IMPLICIT_DEF
+ %8:_(<6 x f16>) = G_CONCAT_VECTORS %6, %7
$vgpr0_vgpr1_vgpr2 = COPY %8
...
@@ -608,123 +608,123 @@ body: |
; SI-LABEL: name: test_fmaxnum_v4s16
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE1]](s32)
- ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC6]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT4]], [[FPEXT5]]
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE2]](s32)
- ; SI-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC7]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE3:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT6]], [[FPEXT7]]
- ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE1]](f32)
+ ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT4]], [[FPEXT5]]
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE2]](f32)
+ ; SI-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE3:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT6]], [[FPEXT7]]
+ ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE3]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; VI-LABEL: name: test_fmaxnum_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC4]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC5]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC2]]
- ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC6]]
- ; VI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
- ; VI-NEXT: [[FCANONICALIZE6:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC3]]
- ; VI-NEXT: [[FCANONICALIZE7:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC7]]
- ; VI-NEXT: [[FMAXNUM_IEEE3:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE6]], [[FCANONICALIZE7]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC4]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC5]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC2]]
+ ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC6]]
+ ; VI-NEXT: [[FMAXNUM_IEEE2:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
+ ; VI-NEXT: [[FCANONICALIZE6:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC3]]
+ ; VI-NEXT: [[FCANONICALIZE7:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC7]]
+ ; VI-NEXT: [[FMAXNUM_IEEE3:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE6]], [[FCANONICALIZE7]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE2]](s16)
- ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE3]](s16)
+ ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE2]](f16)
+ ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE3]](f16)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX9-LABEL: name: test_fmaxnum_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV2]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV1]]
- ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV3]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[FMAXNUM_IEEE]](<2 x s16>), [[FMAXNUM_IEEE1]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
- %2:_(<4 x s16>) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV2]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV1]]
+ ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV3]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[FMAXNUM_IEEE]](<2 x f16>), [[FMAXNUM_IEEE1]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ %2:_(<4 x f16>) = G_FMAXNUM %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -740,46 +740,46 @@ body: |
; SI-LABEL: name: test_fmaxnum_with_fmaxnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1, $vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](f32)
;
; VI-LABEL: name: test_fmaxnum_with_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_with_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
- %3:_(s32) = COPY $vgpr2
- %4:_(s32) = G_FMAXNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
+ %3:_(f32) = COPY $vgpr2
+ %4:_(f32) = G_FMAXNUM %2, %3
$vgpr0 = COPY %4
...
@@ -795,43 +795,43 @@ body: |
; SI-LABEL: name: test_fmaxnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](f32)
;
; VI-LABEL: name: test_fmaxnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCONSTANT float 0.000000e+00
- %2:_(s32) = G_FMAXNUM %0, %1
- %3:_(s32) = COPY $vgpr1
- %4:_(s32) = G_FMAXNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCONSTANT float 0.000000e+00
+ %2:_(f32) = G_FMAXNUM %0, %1
+ %3:_(f32) = COPY $vgpr1
+ %4:_(f32) = G_FMAXNUM %2, %3
$vgpr0 = COPY %4
...
@@ -847,46 +847,46 @@ body: |
; SI-LABEL: name: test_fmaxnum_with_fminnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1, $vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_with_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_with_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
- %3:_(s32) = COPY $vgpr2
- %4:_(s32) = G_FMAXNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
+ %3:_(f32) = COPY $vgpr2
+ %4:_(f32) = G_FMAXNUM %2, %3
$vgpr0 = COPY %4
...
@@ -902,43 +902,43 @@ body: |
; SI-LABEL: name: test_fmaxnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCONSTANT float 0.000000e+00
- %2:_(s32) = G_FMINNUM %0, %1
- %3:_(s32) = COPY $vgpr1
- %4:_(s32) = G_FMAXNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCONSTANT float 0.000000e+00
+ %2:_(f32) = G_FMINNUM %0, %1
+ %3:_(f32) = COPY $vgpr1
+ %4:_(f32) = G_FMAXNUM %2, %3
$vgpr0 = COPY %4
...
@@ -954,32 +954,32 @@ body: |
; SI-LABEL: name: test_fmaxnum_with_constant_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fmaxnum_with_constant_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fmaxnum_with_constant_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCONSTANT float 0.000000e+00
- %2:_(s32) = G_FMAXNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCONSTANT float 0.000000e+00
+ %2:_(f32) = G_FMAXNUM %0, %1
$vgpr0 = COPY %2
...
@@ -995,63 +995,63 @@ body: |
; SI-LABEL: name: test_fmaxnum_with_constant_vector_argument_v2s16_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMAXNUM_IEEE1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C1]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; VI-LABEL: name: test_fmaxnum_with_constant_vector_argument_v2s16_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[C]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[C]]
- ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[C]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[C]]
+ ; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMAXNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C1]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; GFX9-LABEL: name: test_fmaxnum_with_constant_vector_argument_v2s16_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(s16) = G_FCONSTANT half 0xH0000
- %2:_(<2 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16)
- %3:_(<2 x s16>) = G_FMAXNUM %0, %2
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[C]](f16), [[C]](f16)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(f16) = G_FCONSTANT half 0xH0000
+ %2:_(<2 x f16>) = G_BUILD_VECTOR %1(f16), %1(f16)
+ %3:_(<2 x f16>) = G_FMAXNUM %0, %2
$vgpr0 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
index 456c27dc469e8..910a8fcc2f2ab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir
@@ -11,37 +11,37 @@ body: |
; GFX9-LABEL: name: test_fminimum_f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[TRUNC]], [[TRUNC1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[SELECT]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[TRUNC]], [[TRUNC1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](f16), [[TRUNC1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f16) = COPY [[SELECT]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[COPY2]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fminimum_f16
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s16) = G_FMINIMUM [[TRUNC]], [[TRUNC1]]
- ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMINIMUM]](s16)
- ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(f16) = G_FMINIMUM [[TRUNC]], [[TRUNC1]]
+ ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMINIMUM]](f16)
+ ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0(s32)
- %2:_(s32) = COPY $vgpr1
- %3:_(s16) = G_TRUNC %2(s32)
- %4:_(s16) = G_FMINIMUM %1, %3
- %5:_(s32) = G_ANYEXT %4(s16)
- $vgpr0 = COPY %5(s32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f16) = G_TRUNC %0(i32)
+ %2:_(i32) = COPY $vgpr1
+ %3:_(f16) = G_TRUNC %2(i32)
+ %4:_(f16) = G_FMINIMUM %1, %3
+ %5:_(i32) = G_ANYEXT %4(f16)
+ $vgpr0 = COPY %5(i32)
SI_RETURN implicit $vgpr0
...
---
@@ -53,28 +53,28 @@ body: |
; GFX9-LABEL: name: test_fminimum_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f32), [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fminimum_f32
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = G_FMINIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMINIMUM %0, %1
- $vgpr0 = COPY %2(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMINIMUM %0, %1
+ $vgpr0 = COPY %2(f32)
SI_RETURN implicit $vgpr0
...
---
@@ -86,28 +86,28 @@ body: |
; GFX9-LABEL: name: test_fminimum_f64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f64) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f64), [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f64) = COPY [[SELECT]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](f64)
; GFX9-NEXT: SI_RETURN implicit $vgpr0_vgpr1
;
; GFX12-LABEL: name: test_fminimum_f64
; GFX12: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s64) = G_FMINIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUM]](s64)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(f64) = G_FMINIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUM]](f64)
; GFX12-NEXT: SI_RETURN implicit $vgpr0_vgpr1
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FMINIMUM %0, %1
- $vgpr0_vgpr1 = COPY %2(s64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FMINIMUM %0, %1
+ $vgpr0_vgpr1 = COPY %2(f64)
SI_RETURN implicit $vgpr0_vgpr1
...
---
@@ -119,44 +119,44 @@ body: |
; GFX9-LABEL: name: test_fminimum_v2f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](s16), [[TRUNC2]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC1]](s16), [[TRUNC3]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half +qnan
- ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMINNUM_IEEE]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC]](f16), [[TRUNC2]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[TRUNC1]](f16), [[TRUNC3]]
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half +qnan
+ ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[FMINNUM_IEEE]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](i1), [[TRUNC4]], [[C1]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[FCMP1]](i1), [[TRUNC5]], [[C1]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SELECT]](s16), [[SELECT1]](s16)
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](<2 x s16>)
+ ; GFX9-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f16) = G_SELECT [[FCMP]](i1), [[TRUNC4]], [[C1]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f16) = G_SELECT [[FCMP1]](i1), [[TRUNC5]], [[C1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[SELECT]](f16), [[SELECT1]](f16)
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(<2 x f16>) = COPY [[BUILD_VECTOR]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](<2 x f16>)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fminimum_v2f16
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(<2 x s16>) = G_FMINIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](<2 x s16>)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(<2 x f16>) = G_FMINIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](<2 x f16>)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = G_FMINIMUM %0, %1
- $vgpr0 = COPY %2(<2 x s16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = G_FMINIMUM %0, %1
+ $vgpr0 = COPY %2(<2 x f16>)
SI_RETURN implicit $vgpr0
...
---
@@ -168,45 +168,45 @@ body: |
; GFX9-LABEL: name: test_fminimum_v2f32
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY2]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY2]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY1]], [[COPY3]]
- ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY1]](s32), [[COPY3]]
- ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[FCMP1]](i1), [[FMINNUM_IEEE1]], [[C]]
- ; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]](s32)
- ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $vgpr3
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY2]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f32), [[COPY2]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(f32) = COPY [[SELECT]](f32)
+ ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY1]], [[COPY3]]
+ ; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY1]](f32), [[COPY3]]
+ ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](i1), [[FMINNUM_IEEE1]], [[C]]
+ ; GFX9-NEXT: [[COPY5:%[0-9]+]]:_(f32) = COPY [[SELECT1]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]](f32)
+ ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
;
; GFX12-LABEL: name: test_fminimum_v2f32
; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY]], [[COPY2]]
- ; GFX12-NEXT: [[FMINIMUM1:%[0-9]+]]:_(s32) = G_FMINIMUM [[COPY1]], [[COPY3]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
- ; GFX12-NEXT: $vgpr1 = COPY [[FMINIMUM1]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(f32) = COPY $vgpr3
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = G_FMINIMUM [[COPY]], [[COPY2]]
+ ; GFX12-NEXT: [[FMINIMUM1:%[0-9]+]]:_(f32) = G_FMINIMUM [[COPY1]], [[COPY3]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](f32)
+ ; GFX12-NEXT: $vgpr1 = COPY [[FMINIMUM1]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(<2 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32)
- %3:_(s32) = COPY $vgpr2
- %4:_(s32) = COPY $vgpr3
- %5:_(<2 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32)
- %6:_(<2 x s32>) = G_FMINIMUM %2, %5
- %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(<2 x s32>)
- $vgpr0 = COPY %7(s32)
- $vgpr1 = COPY %8(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(<2 x f32>) = G_BUILD_VECTOR %0(f32), %1(f32)
+ %3:_(f32) = COPY $vgpr2
+ %4:_(f32) = COPY $vgpr3
+ %5:_(<2 x f32>) = G_BUILD_VECTOR %3(f32), %4(f32)
+ %6:_(<2 x f32>) = G_FMINIMUM %2, %5
+ %7:_(f32), %8:_(f32) = G_UNMERGE_VALUES %6(<2 x f32>)
+ $vgpr0 = COPY %7(f32)
+ $vgpr1 = COPY %8(f32)
SI_RETURN implicit $vgpr0, implicit $vgpr1
...
---
@@ -218,28 +218,28 @@ body: |
; GFX9-LABEL: name: test_fminimum_nsz_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](s32), [[COPY1]]
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float +qnan
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(i1) = G_FCMP floatpred(ord), [[COPY]](f32), [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float +qnan
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](i1), [[FMINNUM_IEEE]], [[C]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[SELECT]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fminimum_nsz_f32
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = nsz G_FMINIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = nsz G_FMINIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nsz G_FMINIMUM %0, %1
- $vgpr0 = COPY %2(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nsz G_FMINIMUM %0, %1
+ $vgpr0 = COPY %2(f32)
SI_RETURN implicit $vgpr0
...
---
@@ -251,25 +251,25 @@ body: |
; GFX9-LABEL: name: test_fminimum_nnan_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FMINNUM_IEEE]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY [[FMINNUM_IEEE]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[COPY2]](f32)
; GFX9-NEXT: SI_RETURN implicit $vgpr0
;
; GFX12-LABEL: name: test_fminimum_nnan_f32
; GFX12: liveins: $vgpr0, $vgpr1
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
- ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](s32)
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX12-NEXT: [[FMINIMUM:%[0-9]+]]:_(f32) = nnan G_FMINIMUM [[COPY]], [[COPY1]]
+ ; GFX12-NEXT: $vgpr0 = COPY [[FMINIMUM]](f32)
; GFX12-NEXT: SI_RETURN implicit $vgpr0
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nnan G_FMINIMUM %0, %1
- $vgpr0 = COPY %2(s32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nnan G_FMINIMUM %0, %1
+ $vgpr0 = COPY %2(f32)
SI_RETURN implicit $vgpr0
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
index 7fd1345167bbf..b3ef220879bbc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
@@ -17,35 +17,35 @@ body: |
; SI-LABEL: name: test_fminnum_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -61,29 +61,29 @@ body: |
; SI-LABEL: name: test_fminnum_s32_ieee_mode_off
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM]](f32)
;
; VI-LABEL: name: test_fminnum_s32_ieee_mode_off
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM]](f32)
;
; GFX9-LABEL: name: test_fminnum_s32_ieee_mode_off
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM:%[0-9]+]]:_(f32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -96,29 +96,29 @@ body: |
; SI-LABEL: name: test_fminnum_s32_nnan
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_s32_nnan
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_s32_nnan
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = nnan G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = nnan G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -132,32 +132,32 @@ body: |
; SI-LABEL: name: test_fminnum_s32_nnan_lhs
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_s32_nnan_lhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = nnan COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = nnan COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -171,32 +171,32 @@ body: |
; SI-LABEL: name: test_fminnum_s32_nnan_rhs
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_s32_nnan_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_s32_nnan_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -209,29 +209,29 @@ body: |
; SI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = nnan COPY $vgpr0
- %1:_(s32) = nnan COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = nnan COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = nnan COPY $vgpr1
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = nnan COPY $vgpr0
+ %1:_(f32) = nnan COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -244,35 +244,35 @@ body: |
; SI-LABEL: name: test_fminnum_s64
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](f64)
;
; VI-LABEL: name: test_fminnum_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](f64)
;
; GFX9-LABEL: name: test_fminnum_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f64) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FMINNUM %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -285,48 +285,48 @@ body: |
; SI-LABEL: name: test_fminnum_s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fminnum_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMINNUM_IEEE]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMINNUM_IEEE]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fminnum_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMINNUM_IEEE]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_TRUNC %1
- %4:_(s16) = G_FMINNUM %2, %3
- %5:_(s32) = G_ANYEXT %4
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FMINNUM_IEEE]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(f16) = G_TRUNC %0
+ %3:_(f16) = G_TRUNC %1
+ %4:_(f16) = G_FMINNUM %2, %3
+ %5:_(i32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
@@ -339,53 +339,53 @@ body: |
; SI-LABEL: name: test_fminnum_v2s32
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV2]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV1]]
- ; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV3]]
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](s32), [[FMINNUM_IEEE1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV2]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV1]]
+ ; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV3]]
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](f32), [[FMINNUM_IEEE1]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fminnum_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV2]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV3]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](s32), [[FMINNUM_IEEE1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV2]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV3]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](f32), [[FMINNUM_IEEE1]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fminnum_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV2]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV1]]
- ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV3]]
- ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](s32), [[FMINNUM_IEEE1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV2]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV1]]
+ ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[UV3]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](f32), [[FMINNUM_IEEE1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = G_FMINNUM %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -398,71 +398,71 @@ body: |
; SI-LABEL: name: test_fminnum_v2s16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
;
; VI-LABEL: name: test_fminnum_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC2]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC3]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC2]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC3]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x f16>)
;
; GFX9-LABEL: name: test_fminnum_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = COPY $vgpr1
- %2:_(<2 x s16>) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = COPY $vgpr1
+ %2:_(<2 x f16>) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -474,127 +474,127 @@ body: |
; SI-LABEL: name: test_fminnum_v3s16
; SI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; SI-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[UV3:%[0-9]+]]:_(<2 x f16>), [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<6 x f16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE1]](s32)
- ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT4]], [[FPEXT5]]
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE2]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE1]](f32)
+ ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT4]], [[FPEXT5]]
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE2]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C1]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C1]], [[SHL1]]
- ; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
+ ; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>), [[BITCAST6]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
;
; VI-LABEL: name: test_fminnum_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; VI-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[UV3:%[0-9]+]]:_(<2 x f16>), [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<6 x f16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x s16>)
- ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC3]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC4]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC2]]
- ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC5]]
- ; VI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV4]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC3]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC4]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC2]]
+ ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC5]]
+ ; VI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE2]](s16)
+ ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE2]](f16)
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C1]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C1]], [[SHL1]]
- ; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
+ ; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR2]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>), [[BITCAST6]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
;
; GFX9-LABEL: name: test_fminnum_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV3]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV1]]
- ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV4]]
- ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMINNUM_IEEE]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>), [[UV2:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<6 x f16>)
+ ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[UV3:%[0-9]+]]:_(<2 x f16>), [[UV4:%[0-9]+]]:_(<2 x f16>), [[UV5:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<6 x f16>)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV3]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV1]]
+ ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV4]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[FMINNUM_IEEE]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FMINNUM_IEEE1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- %0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- %2:_(<3 x s16>), %3:_(<3 x s16>) = G_UNMERGE_VALUES %0
- %4:_(<3 x s16>), %5:_(<3 x s16>) = G_UNMERGE_VALUES %1
- %6:_(<3 x s16>) = G_FMINNUM %2, %4
- %7:_(<3 x s16>) = G_IMPLICIT_DEF
- %8:_(<6 x s16>) = G_CONCAT_VECTORS %6, %7
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[FMINNUM_IEEE1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[TRUNC]](f16), [[TRUNC1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[TRUNC2]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[DEF]](f16), [[DEF]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>), [[BUILD_VECTOR2]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x f16>)
+ %0:_(<6 x f16>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<6 x f16>) = COPY $vgpr3_vgpr4_vgpr5
+ %2:_(<3 x f16>), %3:_(<3 x f16>) = G_UNMERGE_VALUES %0
+ %4:_(<3 x f16>), %5:_(<3 x f16>) = G_UNMERGE_VALUES %1
+ %6:_(<3 x f16>) = G_FMINNUM %2, %4
+ %7:_(<3 x f16>) = G_IMPLICIT_DEF
+ %8:_(<6 x f16>) = G_CONCAT_VECTORS %6, %7
$vgpr0_vgpr1_vgpr2 = COPY %8
...
@@ -608,123 +608,123 @@ body: |
; SI-LABEL: name: test_fminnum_v4s16
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC4]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC5]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE1]](s32)
- ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC6]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT4]], [[FPEXT5]]
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE2]](s32)
- ; SI-NEXT: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC7]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE3:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT6]], [[FPEXT7]]
- ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC4]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC5]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE1]](f32)
+ ; SI-NEXT: [[FPEXT4:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FPEXT5:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC6]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT4]], [[FPEXT5]]
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE2]](f32)
+ ; SI-NEXT: [[FPEXT6:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FPEXT7:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC7]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE3:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT6]], [[FPEXT7]]
+ ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE3]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; VI-LABEL: name: test_fminnum_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x s16>)
- ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV2]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC4:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST2]](i32)
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
- ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32)
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x s16>)
- ; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32)
+ ; VI-NEXT: [[TRUNC5:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR2]](i32)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV3]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC6:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST3]](i32)
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32)
- ; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC4]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC5]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC2]]
- ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC6]]
- ; VI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
- ; VI-NEXT: [[FCANONICALIZE6:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC3]]
- ; VI-NEXT: [[FCANONICALIZE7:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC7]]
- ; VI-NEXT: [[FMINNUM_IEEE3:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE6]], [[FCANONICALIZE7]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR3]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC4]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC5]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[FCANONICALIZE4:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC2]]
+ ; VI-NEXT: [[FCANONICALIZE5:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC6]]
+ ; VI-NEXT: [[FMINNUM_IEEE2:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE4]], [[FCANONICALIZE5]]
+ ; VI-NEXT: [[FCANONICALIZE6:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC3]]
+ ; VI-NEXT: [[FCANONICALIZE7:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC7]]
+ ; VI-NEXT: [[FMINNUM_IEEE3:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE6]], [[FCANONICALIZE7]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE2]](s16)
- ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE3]](s16)
+ ; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE2]](f16)
+ ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE3]](f16)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x f16>), [[BITCAST5]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX9-LABEL: name: test_fminnum_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV2]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV1]]
- ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[UV3]]
- ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[FMINNUM_IEEE]](<2 x s16>), [[FMINNUM_IEEE1]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
- %2:_(<4 x s16>) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(<2 x f16>), [[UV3:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY1]](<4 x f16>)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV2]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV1]]
+ ; GFX9-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[UV3]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[FMINNUM_IEEE]](<2 x f16>), [[FMINNUM_IEEE1]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = COPY $vgpr2_vgpr3
+ %2:_(<4 x f16>) = G_FMINNUM %0, %1
$vgpr0_vgpr1 = COPY %2
...
@@ -740,46 +740,46 @@ body: |
; SI-LABEL: name: test_fminnum_with_fminnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1, $vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](f32)
;
; VI-LABEL: name: test_fminnum_with_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](f32)
;
; GFX9-LABEL: name: test_fminnum_with_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMINNUM %0, %1
- %3:_(s32) = COPY $vgpr2
- %4:_(s32) = G_FMINNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMINNUM %0, %1
+ %3:_(f32) = COPY $vgpr2
+ %4:_(f32) = G_FMINNUM %2, %3
$vgpr0 = COPY %4
...
@@ -795,43 +795,43 @@ body: |
; SI-LABEL: name: test_fminnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](f32)
;
; VI-LABEL: name: test_fminnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](f32)
;
; GFX9-LABEL: name: test_fminnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCONSTANT float 0.000000e+00
- %2:_(s32) = G_FMINNUM %0, %1
- %3:_(s32) = COPY $vgpr1
- %4:_(s32) = G_FMINNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCONSTANT float 0.000000e+00
+ %2:_(f32) = G_FMINNUM %0, %1
+ %3:_(f32) = COPY $vgpr1
+ %4:_(f32) = G_FMINNUM %2, %3
$vgpr0 = COPY %4
...
@@ -847,46 +847,46 @@ body: |
; SI-LABEL: name: test_fminnum_with_fmaxnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1, $vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; SI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_with_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_with_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FMAXNUM %0, %1
- %3:_(s32) = COPY $vgpr2
- %4:_(s32) = G_FMINNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(f32) = COPY $vgpr2
+ ; GFX9-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY2]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE2]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FMAXNUM %0, %1
+ %3:_(f32) = COPY $vgpr2
+ %4:_(f32) = G_FMINNUM %2, %3
$vgpr0 = COPY %4
...
@@ -902,43 +902,43 @@ body: |
; SI-LABEL: name: test_fminnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCONSTANT float 0.000000e+00
- %2:_(s32) = G_FMAXNUM %0, %1
- %3:_(s32) = COPY $vgpr1
- %4:_(s32) = G_FMINNUM %2, %3
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(f32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY1]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCONSTANT float 0.000000e+00
+ %2:_(f32) = G_FMAXNUM %0, %1
+ %3:_(f32) = COPY $vgpr1
+ %4:_(f32) = G_FMINNUM %2, %3
$vgpr0 = COPY %4
...
@@ -954,32 +954,32 @@ body: |
; SI-LABEL: name: test_fminnum_with_constant_argument_s32_ieee_mode_on
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; VI-LABEL: name: test_fminnum_with_constant_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
;
; GFX9-LABEL: name: test_fminnum_with_constant_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCONSTANT float 0.000000e+00
- %2:_(s32) = G_FMINNUM %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f32) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCONSTANT float 0.000000e+00
+ %2:_(f32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2
...
@@ -995,63 +995,63 @@ body: |
; SI-LABEL: name: test_fminnum_with_constant_vector_argument_v2s16_ieee_mode_on
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
- ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE1]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[C]](f16)
+ ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f32) = G_FMINNUM_IEEE [[FPEXT2]], [[FPEXT3]]
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[FMINNUM_IEEE1]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C1]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; VI-LABEL: name: test_fminnum_with_constant_vector_argument_v2s16_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
- ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[C]]
- ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
- ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC1]]
- ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[C]]
- ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](s16)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC]]
+ ; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[C]]
+ ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
+ ; VI-NEXT: [[FCANONICALIZE2:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[TRUNC1]]
+ ; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(f16) = G_FCANONICALIZE [[C]]
+ ; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(f16) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FMINNUM_IEEE1]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C1]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; GFX9-LABEL: name: test_fminnum_with_constant_vector_argument_v2s16_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0.000000e+00
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
- ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[COPY]]
- ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(s16) = G_FCONSTANT half 0xH0000
- %2:_(<2 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16)
- %3:_(<2 x s16>) = G_FMINNUM %0, %2
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 0.000000e+00
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[C]](f16), [[C]](f16)
+ ; GFX9-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(<2 x f16>) = G_FCANONICALIZE [[COPY]]
+ ; GFX9-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(<2 x f16>) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[BUILD_VECTOR]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(f16) = G_FCONSTANT half 0xH0000
+ %2:_(<2 x f16>) = G_BUILD_VECTOR %1(f16), %1(f16)
+ %3:_(<2 x f16>) = G_FMINNUM %0, %2
$vgpr0 = COPY %3
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
index 248dbcf94f7ce..4439208fb8437 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
@@ -14,33 +14,33 @@ body: |
; SI-LABEL: name: test_fsin_s32
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; VI-LABEL: name: test_fsin_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; GFX9-LABEL: name: test_fsin_s32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FSIN %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FSIN %0
$vgpr0 = COPY %1
...
@@ -53,33 +53,33 @@ body: |
; SI-LABEL: name: test_fsin_s64
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](f64)
;
; VI-LABEL: name: test_fsin_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](f64)
;
; GFX9-LABEL: name: test_fsin_s64
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FSIN %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FSIN %0
$vgpr0_vgpr1 = COPY %1
...
---
@@ -91,43 +91,43 @@ body: |
; SI-LABEL: name: test_fsin_s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fsin_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fsin_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FSIN %1
- %3:_(s32) = G_ANYEXT %2
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f16) = G_TRUNC %0
+ %2:_(f16) = G_FSIN %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -140,47 +140,47 @@ body: |
; SI-LABEL: name: test_fsin_v2s32
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fsin_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; GFX9-LABEL: name: test_fsin_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT]](s32), [[INT1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = G_FSIN %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f32)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT]](f32), [[INT1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = G_FSIN %0
$vgpr0_vgpr1 = COPY %1
...
@@ -193,55 +193,55 @@ body: |
; SI-LABEL: name: test_fsin_v3s32
; SI: liveins: $vgpr0_vgpr1_vgpr2
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; SI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; SI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]](s32)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32), [[INT5]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; VI-LABEL: name: test_fsin_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; VI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32), [[INT5]](s32)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; VI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](f32)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32), [[INT5]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
;
; GFX9-LABEL: name: test_fsin_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](s32)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[C]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL2]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[INT]](s32), [[INT1]](s32), [[INT2]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- %1:_(<3 x s32>) = G_FSIN %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<3 x f32>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f32)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](f32)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV2]], [[C]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL2]](f32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x f32>) = G_BUILD_VECTOR [[INT]](f32), [[INT1]](f32), [[INT2]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x f32>)
+ %0:_(<3 x f32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x f32>) = G_FSIN %0
$vgpr0_vgpr1_vgpr2 = COPY %1
...
@@ -254,47 +254,47 @@ body: |
; SI-LABEL: name: test_fsin_v2s64
; SI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s64)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s64)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT1]](s64), [[INT3]](s64)
- ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f64)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f64)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f64)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT1]](f64), [[INT3]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; VI-LABEL: name: test_fsin_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s64)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s64)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT1]](s64), [[INT3]](s64)
- ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f64)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f64)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f64)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT1]](f64), [[INT3]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
;
; GFX9-LABEL: name: test_fsin_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[UV]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s64)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](s64)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[INT]](s64), [[INT1]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- %1:_(<2 x s64>) = G_FSIN %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[UV]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f64)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f64) = G_FMUL [[UV1]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](f64)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[INT]](f64), [[INT1]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>)
+ %0:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<2 x f64>) = G_FSIN %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...
@@ -307,71 +307,71 @@ body: |
; SI-LABEL: name: test_fsin_v2s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT1]], [[C1]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT3]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C1]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C1]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT3]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; VI-LABEL: name: test_fsin_v2s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s16)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s16)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](s16)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f16)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f16)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x f16>)
;
; GFX9-LABEL: name: test_fsin_v2s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr0
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT]](s16), [[INT1]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $vgpr0
- %1:_(<2 x s16>) = G_FSIN %0
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f16)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT]](f16), [[INT1]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x f16>)
+ %0:_(<2 x f16>) = COPY $vgpr0
+ %1:_(<2 x f16>) = G_FSIN %0
$vgpr0 = COPY %1
...
@@ -381,64 +381,64 @@ body: |
bb.0:
; SI-LABEL: name: test_fsin_v3s16
- ; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT3]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[DEF]](s16)
- ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT2]], [[C]]
- ; SI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; SI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](s32)
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT5]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
- ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; SI: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT3]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[DEF]](f16)
+ ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[C]]
+ ; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](f32)
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT5]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC1]](f16)
+ ; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; VI-LABEL: name: test_fsin_v3s16
- ; VI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s16)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s16)
- ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; VI-NEXT: [[INT4:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s16)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT3]](s16)
- ; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT5]](s16)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
+ ; VI: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f16)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f16)
+ ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; VI-NEXT: [[INT4:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f16)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT3]](f16)
+ ; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT5]](f16)
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
;
; GFX9-LABEL: name: test_fsin_v3s16
- ; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](s16)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[DEF]], [[C]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL2]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[INT2]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
- ; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- %0:_(<3 x s16>) = G_IMPLICIT_DEF
- %1:_(<3 x s16>) = G_FSIN %0
- %2:_(<3 x s32>) = G_ANYEXT %1
+ ; GFX9: [[DEF:%[0-9]+]]:_(f16) = G_IMPLICIT_DEF
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f16)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](f16)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[DEF]], [[C]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL2]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(i32) = G_ANYEXT [[INT2]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x i32>) = G_BUILD_VECTOR [[ANYEXT]](i32), [[ANYEXT1]](i32), [[ANYEXT2]](i32)
+ ; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x i32>)
+ %0:_(<3 x f16>) = G_IMPLICIT_DEF
+ %1:_(<3 x f16>) = G_FSIN %0
+ %2:_(<3 x i32>) = G_ANYEXT %1
S_NOP 0, implicit %2
...
@@ -451,120 +451,120 @@ body: |
; SI-LABEL: name: test_fsin_v4s16
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; SI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; SI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C1]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT1]], [[C1]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s32)
- ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT3]](s32)
- ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC2]](s16)
- ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT2]], [[C1]]
- ; SI-NEXT: [[INT4:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s32)
- ; SI-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](s32)
- ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT5]](s32)
- ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC3]](s16)
- ; SI-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT3]], [[C1]]
- ; SI-NEXT: [[INT6:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](s32)
- ; SI-NEXT: [[INT7:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT6]](s32)
- ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT7]](s32)
- ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](s16)
- ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](s16)
+ ; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C1]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT1]], [[C1]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f32)
+ ; SI-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT3]](f32)
+ ; SI-NEXT: [[FPEXT2:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC2]](f16)
+ ; SI-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT2]], [[C1]]
+ ; SI-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f32)
+ ; SI-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](f32)
+ ; SI-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT5]](f32)
+ ; SI-NEXT: [[FPEXT3:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC3]](f16)
+ ; SI-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT3]], [[C1]]
+ ; SI-NEXT: [[INT6:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](f32)
+ ; SI-NEXT: [[INT7:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT6]](f32)
+ ; SI-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT7]](f32)
+ ; SI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
; SI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; SI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](s16)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](s16)
+ ; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC2]](f16)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; VI-LABEL: name: test_fsin_v4s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; VI-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s16)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s16)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](s16)
- ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[C1]]
- ; VI-NEXT: [[INT4:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](s16)
- ; VI-NEXT: [[INT5:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](s16)
- ; VI-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[C1]]
- ; VI-NEXT: [[INT6:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](s16)
- ; VI-NEXT: [[INT7:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT6]](s16)
- ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](s16)
- ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](s16)
+ ; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f16)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f16)
+ ; VI-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT2]](f16)
+ ; VI-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[C1]]
+ ; VI-NEXT: [[INT4:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL2]](f16)
+ ; VI-NEXT: [[INT5:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT4]](f16)
+ ; VI-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[C1]]
+ ; VI-NEXT: [[INT6:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL3]](f16)
+ ; VI-NEXT: [[INT7:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT6]](f16)
+ ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[INT1]](f16)
+ ; VI-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[INT3]](f16)
; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32)
; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]]
- ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
- ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[INT5]](s16)
- ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[INT7]](s16)
+ ; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR]](i32)
+ ; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[INT5]](f16)
+ ; VI-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[INT7]](f16)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]]
- ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
- ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
+ ; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR1]](i32)
+ ; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x f16>), [[BITCAST3]](<2 x f16>)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
;
; GFX9-LABEL: name: test_fsin_v4s16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](i32)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x f16>), [[UV1:%[0-9]+]]:_(<2 x f16>) = G_UNMERGE_VALUES [[COPY]](<4 x f16>)
+ ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST]](i32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32)
- ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR]](i32)
+ ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x f16>)
+ ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(f16) = G_TRUNC [[BITCAST1]](i32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C1]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s16)
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC1]], [[C1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](s16)
- ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC2]], [[C1]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL2]](s16)
- ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC3]], [[C1]]
- ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL3]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT]](s16), [[INT1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[INT2]](s16), [[INT3]](s16)
- ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
- %1:_(<4 x s16>) = G_FSIN %0
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(f16) = G_TRUNC [[LSHR1]](i32)
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C1]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f16)
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC1]], [[C1]]
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL1]](f16)
+ ; GFX9-NEXT: [[FMUL2:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC2]], [[C1]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL2]](f16)
+ ; GFX9-NEXT: [[FMUL3:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC3]], [[C1]]
+ ; GFX9-NEXT: [[INT3:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL3]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT]](f16), [[INT1]](f16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f16>) = G_BUILD_VECTOR [[INT2]](f16), [[INT3]](f16)
+ ; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x f16>), [[BUILD_VECTOR1]](<2 x f16>)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x f16>)
+ %0:_(<4 x f16>) = COPY $vgpr0_vgpr1
+ %1:_(<4 x f16>) = G_FSIN %0
$vgpr0_vgpr1 = COPY %1
...
@@ -577,33 +577,33 @@ body: |
; SI-LABEL: name: test_fsin_s32_flags
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; VI-LABEL: name: test_fsin_s32_flags
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; GFX9-LABEL: name: test_fsin_s32_flags
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = nnan G_FSIN %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = nnan G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = nnan G_FSIN %0
$vgpr0 = COPY %1
...
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