[llvm] [AMDGPU][True16] Fix MadMix selection (PR #205431)

[Petar Avramovic via llvm-commits]

https://github.com/petar-avramovic commented:

What I had in mind was something like
```
def : GCNPat <
  (f32 (fma (f32 (VOP3PMadMixModsExt16 f16:$src0, i32:$src0_mods)),
            (f32 (VOP3PMadMixMods16    f16:$src1, i32:$src1_mods)),
            (f32 (VOP3PMadMixMods16    f16:$src2, i32:$src2_mods)))),
  (V_FMA_MIX_F32
     $src0_mods, (REG_SEQUENCE VGPR_32, $src0, lo16, (i16 (IMPLICIT_DEF)), hi16),
     $src1_mods, (REG_SEQUENCE VGPR_32, $src1, lo16, (i16 (IMPLICIT_DEF)), hi16),
     $src2_mods, (REG_SEQUENCE VGPR_32, $src2, lo16, (i16 (IMPLICIT_DEF)), hi16),
     DSTCLAMP.NONE)>;
```
VOP3PMadMixMods16 matches 16 bit source, while VOP3PMadMixMods32 would match 32 bit source

this would work for the case where all inputs are 16 bit, but then this should pick up total of 8 other combinations as well, for example for f16 f32 f16 should have pattern like
```
def : GCNPat <
  (f32 (fma (f32 (VOP3PMadMixModsExt16 f16:$src0, i32:$src0_mods)),
            (f32 (VOP3PMadMixMods32    f16:$src1, i32:$src1_mods)),
            (f32 (VOP3PMadMixMods16    f16:$src2, i32:$src2_mods)))),
  (V_FMA_MIX_F32
     $src0_mods, (REG_SEQUENCE VGPR_32, $src0, lo16, (i16 (IMPLICIT_DEF)), hi16),
     $src1_mods, $src1,
     $src2_mods, (REG_SEQUENCE VGPR_32, $src2, lo16, (i16 (IMPLICIT_DEF)), hi16),
     DSTCLAMP.NONE)>;
```

which is not so great. afaik there is no cpp hook on instruction build?

So don't really know, maybe do full manual match and conditional reg sequence inst build
```
  case AMDGPU::G_FMA:
    return selectV_FMA_MIX_F32(I);
```

@Sisyph @kosarev thoughts? 


https://github.com/llvm/llvm-project/pull/205431